Asynchronous circuit timing sequence checking method based on static analysis

A technology of asynchronous timing and asynchronous circuits, applied in the direction of electrical digital data processing, special data processing applications, instruments, etc., can solve problems such as design failures, and achieve the effect of improving quality and efficiency

CN106096171AInactive Publication Date: 2016-11-09SHENZHEN PANGO MICROSYST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2016-11-09
Estimated Expiration
Not applicable · inactive patent

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Abstract

The invention provides an asynchronous circuit timing sequence checking method based on static analysis. The method includes the steps that a logic design file is analyzed, and a timing sequence diagram is established; a timing sequence constraint file is read in, and timing sequence constraint is established on the timing sequence diagram; timing sequence inspection is conducted; when abnormity is not found in timing sequence inspection, an asynchronous timing sequence path is extracted out of the timing sequence diagram and analyzed, and the delay information of the asynchronous timing sequence path is calculated; timing sequence allowance information is calculated according to the delay information of the asynchronous timing sequence path and delay information required by a device in a library file, and whether user design meets the timing sequence requirement or not is judged according to the timing sequence allowance information. By means of the asynchronous circuit timing sequence checking method, whether a timing sequence problem occurs in an asynchronous circuit or not can be judged, a reference is provided for integrated circuit designers, and design quality is guaranteed.
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Description

technical field

[0001] The invention relates to the technical field of programmable integrated circuit design, in particular to a method for checking timing of asynchronous circuits based on static analysis. Background technique

[0002] In the process of designing an integrated circuit, it is usually necessary to analyze and check the timing of the designed circuit to ensure that the design can meet the timing requirements. Generally speaking, timing checks can be classified into static checks and dynamic checks. The dynamic inspection is carried out on an EDA (Electronic Design Automation, electronic design automation) simulation platform by constructing test vectors. This kind of inspection has relatively high accuracy and can verify the function, but it is limited by the simulation speed of the EDA platform, and the inspection process takes a long time. Static inspection does not simulate the function, but uses the exhaustive method to replace the test vector with math...

Examples

Embodiment Construction

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0032] The present invention provides a method for checking the timing of asynchronous circuits based on static analysis, such as figure 1 As shown, the method includes:

[0033] S11. Analyze the logic design file and create a sequence diagram.

[0034] Specifically, analyze the netlist file and extract timing-related information, and back-...