A dual independent closed-loop surge suppression circuit
A surge suppression circuit and dual-independent technology, applied in the direction of electrical components, output power conversion devices, etc., can solve the problems that are not conducive to the refinement of airborne circuits, occupy a large volume, and high production costs, so as to achieve a small footprint and reduce Effect of power loss and production cost reduction
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Publication Date
- 2020-05-26
Smart Images

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Abstract
Description
technical field
[0001] The invention belongs to the technical field of aviation power electronic control, and relates to a surge suppression circuit, in particular to a double independent closed-loop surge suppression circuit. Background technique
[0002] The power supply equipment of existing airborne high-power transmitters usually adopts a DC power supply circuit, wherein the DC power supply can be provided by the airborne AC power after rectification and transformation, and an inductor, a capacitor and a field effect transistor are connected in series in the power supply circuit. The inductance and capacitor form a filter, which is connected to the DC power supply through the FET, and the rear stage of the filter is connected to the load, and the power supply of the load can be switched by controlling the on-off.
[0003] In order to adapt to the large power fluctuation of the transmitter during pulse transmission, the capacitance of the capacitor is usually very large,...
Examples
Embodiment 1
[0024] The present invention provides a double independent closed-loop surge suppression circuit, and its preferred embodiment is as figure 1 shown. It includes a DC power supply Vdc, an inductor L, a capacitor C, a field effect transistor Q, an error amplifier U, a single-pole double-throw analog switch K and a hysteresis comparator Com; the negative pole of the DC power supply Vdc is connected to the The source of the field effect transistor Q is connected to the ground; the positive pole of the DC power supply Vdc is connected to the drain of the field effect transistor Q through the inductance L and the capacitor C connected in series; the output terminal of the error amplifier U is connected to the The gate of the field effect transistor Q is connected, and at the same time, input to the input terminal of the hysteresis comparator Com; the positive input terminal of the error amplifier U inputs the control reference voltage Vref, and the negative input terminal of the err...