Dual redundant decoding drive circuit for satellites to prevent single point failure, and medium
A decoding circuit and a single-point failure technology are applied in the application of error detection coding of multiple parity bits, error correction/detection, and encoding using block codes, which can solve single-point failures that are difficult to meet the high requirements of satellite systems. Reliability requirements, command output failures and other issues, to achieve the effect of ensuring reliability, preventing internal circuit damage, and preventing output of wrong commands
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Publication Date
- 2018-10-19
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] The invention belongs to the field of integrated circuits, and relates to a command decoding drive circuit for satellites, in particular to a double-redundant decoding drive circuit and medium for preventing single-point failures for satellites. The application of dual redundant backup with point failure. Background technique
[0002] The command decoding drive circuit is the core component of the satellite remote control subsystem. Most of the command actions it outputs are key actions related to the success or failure of the satellite, such as the deployment of solar panels and the detonation of pyrotechnics. Therefore, the reliability requirements for it are very high.
[0003] Affected by space particles during the satellite’s in-orbit operation, various single-event effects often occur in the command decoding drive circuit built with discrete combinational logic devices, including single-event transient pulse (SET), single-event latch-up (SEL), si...
Examples
Embodiment Construction
[0054]The invention relates to a dual redundant decoding drive circuit for preventing single-point failure for satellites, comprising a dual redundant decoding circuit and a dual redundant output drive circuit. The dual redundant decoding circuit is composed of two independent decoding circuits with the same structure, they share a set of input signals, perform decoding respectively, and output two sets of independent decoding signals to complete the dual redundant decoding function and As the control signal of the dual-redundant output drive circuit of the subsequent stage; the dual-redundant output drive circuit adopts the structure of 4 PMOS output drive tubes of "two parallels and two series", which are controlled by two independent decoding signals of the previous stage. When all the output PMOS transistors are turned on, the output is high level, and the circuit can also output normally when a single PMOS transistor is open or short-circuited. The double-redundant decodi...