Detection method, system, storage medium and test equipment for the shortest pulse of power on and off

Abstract

The present invention discloses a detection method, system, storage medium and test equipment for the shortest on / off pulse, wherein the detection method comprises: after the serial port DTR pin of the device to be tested is connected to the on / off pin, the high and low levels of the serial port DTR pin are controlled to cyclically input the on / off pulse time to the device to be tested so that the device to be tested can be turned on / off; the on / off state of the device to be tested is obtained, and the shortest on / off pulse is detected according to the on / off state of the device to be tested and the cyclically input on / off pulse time. The method can accurately calculate the shortest on / off pulse time, and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

Description

Technical Field

[0001] The present invention relates to the technical field of software testing, and in particular to a method for detecting the shortest power-on / off pulse, a system for detecting the shortest power-on / off pulse, a computer-readable storage medium and a testing device. Background Art

[0002] Regarding the verification of the minimum pulse time for hardware-based power on and off in communication modules, the related technologies generally use manual rough verification, special instruments or special hardware circuits to simulate the pulse time, and verify whether the power can be turned on normally under the simulated specific pulse time. However, the above technologies have the disadvantages of high testing cost, complex circuit design, uncontrollable test accuracy, and the pulse circuit design requires the theoretical pulse time to be known in advance. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the related art to a certain extent. To this end, the first object of the present invention is to provide a method for detecting the shortest on / off pulse. The method can accurately calculate the shortest on / off pulse time and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0004] A second object of the present invention is to provide a computer-readable storage medium.

[0005] The third object of the present invention is to provide a testing device.

[0006] A fourth objective of the present invention is to provide a detection system for the shortest pulse of power on / off.

[0007] To achieve the above-mentioned purpose, the first aspect of the embodiment of the present invention proposes a method for detecting the shortest power-on / off pulse, comprising the following steps: after the serial port DTR pin of the device under test is connected to the power-on / off pin, by controlling the high and low levels of the serial port DTR pin to cyclically input the power-on / off pulse time to the device under test so that the device under test can be turned on and off; obtaining the power-on / off state of the device under test, and detecting the shortest power-on / off pulse according to the power-on / off state of the device under test and the cyclically input power-on / off pulse time.

[0008] The method for detecting the shortest power-on and power-off pulse in the embodiment of the present invention can accurately calculate the shortest power-on and power-off pulse time by controlling the high and low levels of the serial port DTR (Data Terminal Ready) pin and automatically detecting the power-on status by cyclically detecting the power-on reporting information and other interface loading status. The method has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0009] In addition, the method for detecting the shortest power-on / off pulse according to the above embodiment of the present invention may also have the following additional technical features:

[0010] According to an embodiment of the present invention, when the power on / off pulse time is cyclically input to the device under test, the power on / off pulse time is controlled to increase in integer multiples in sequence according to a preset accuracy requirement.

[0011] According to one embodiment of the present invention, the shortest on / off pulse is detected according to the on / off state of the device under test and the on / off pulse time of the cyclic input, including: obtaining a preliminary shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; repeatedly applying the preliminary shortest on / off pulse to the device under test so that the device under test is repeatedly turned on and off; confirming whether the preliminary shortest on / off pulse is reliable according to the on / off state of the device under test, and when confirming that the preliminary shortest on / off pulse is reliable, using the preliminary shortest on / off pulse as the final shortest on / off pulse.

[0012] According to an embodiment of the present invention, when it is confirmed that the preliminary shortest on / off pulse is unreliable, the on / off pulse time is gradually increased according to a preset accuracy requirement.

[0013] To achieve the above objectives, a second embodiment of the present invention proposes a computer-readable storage medium on which a detection program for the shortest power-on / off pulse is stored. When the detection program is executed by a processor, the above-mentioned method for detecting the shortest power-on / off pulse can be used.

[0014] The computer-readable storage medium of an embodiment of the present invention can accurately calculate the shortest on / off pulse time when the computer program corresponding to the above-mentioned on / off shortest pulse detection method is executed by a processor. It has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0015] To achieve the above-mentioned purpose, the third aspect of the present invention proposes a testing device, including a memory, a processor, and a detection program for the shortest power-on and power-off pulse stored in the memory and executable on the processor. When the processor executes the detection program, the above-mentioned method for detecting the shortest power-on and power-off pulse can be implemented.

[0016] The test equipment of the embodiment of the present invention, when its processor executes the detection program of the shortest power-on and power-off pulse stored in the memory, can accurately calculate the shortest power-on and power-off pulse time, and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0017] To achieve the above-mentioned purpose, the fourth aspect of the present invention proposes a detection system for the shortest power-on / off pulse, including: a pulse control module, which is used to control the high and low levels of the serial port DTR pin of the device under test after the serial port DTR pin is connected to the power-on / off pin, so as to cyclically input the power-on / off pulse time to the device under test so as to turn the device under test on and off; an acquisition module, which is used to obtain the power-on / off state of the device under test; and a shortest power-on / off pulse detection module, which is used to detect the shortest power-on / off pulse according to the power-on / off state of the device under test and the cyclically input power-on / off pulse time.

[0018] The detection system for the shortest power-on and power-off pulse of the embodiment of the present invention can accurately calculate the shortest power-on and power-off pulse time by controlling the high and low levels of the serial port DTR pin and automatically detecting the power-on status by cyclically detecting the power-on reporting information and other interface loading status. It has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0019] In addition, the detection system for the shortest power-on / off pulse according to the above embodiment of the present invention may also have the following additional technical features:

[0020] According to an embodiment of the present invention, the pulse control module is further used to control the power on / off pulse time to increase in integer multiples in sequence according to a preset accuracy requirement when cyclically inputting the power on / off pulse time to the device under test.

[0021] According to one embodiment of the present invention, the shortest on-off pulse detection module is also used to obtain a preliminary shortest on-off pulse according to the on-off state of the device under test and the on-off pulse time of a cyclic input; repeatedly apply the preliminary shortest on-off pulse to the device under test through the pulse control module so that the device under test is repeatedly turned on and off; confirm whether the preliminary shortest on-off pulse is reliable according to the on-off state of the device under test, and when confirming that the preliminary shortest on-off pulse is reliable, use the preliminary shortest on-off pulse as the final shortest on-off pulse.

[0022] According to an embodiment of the present invention, the shortest on / off pulse detection module is further configured to gradually increase the on / off pulse time according to a preset accuracy requirement through the pulse control module when it is determined that the preliminary shortest on / off pulse is unreliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0024] Figure 1 is a flow chart of a method for detecting the shortest power-on / off pulse according to an embodiment of the present invention;

[0025] Figure 2 is a flow chart of a method for detecting the shortest pulse of a power on / off machine according to a specific example of the present invention;

[0026] Figure 3 The invention is a structural block diagram of a detection system for the shortest pulse of power on and off according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0028] The following describes the detection method, system, storage medium, and testing equipment for the shortest power-on / off pulse according to the embodiments of the present invention with reference to the accompanying drawings.

[0029] Figure 1 FIG. 1 is a flow chart of a method for detecting the shortest pulse for powering on and off according to an embodiment of the present invention. Figure 1 As shown, the detection method comprises the following steps:

[0030] S1, after the serial port DTR pin of the device under test is connected to the power on / off pin, the power on / off pulse time is cyclically input to the device under test by controlling the high and low levels of the serial port DTR pin, so that the device under test can be turned on and off.

[0031] Specifically, after connecting the serial port DTR pin of the device under test to the power on / off pin, the perl language can be used to communicate with the serial port through the serial port to control the high and low levels of the serial port DTR pin, that is, to achieve the control of pulling up or pulling down the serial port DTR pin. For example, through the "$ob->dtr_active(F)" statement, the serial port DTR pin can be pulled up, and through the "$ob->dtr_active(T)" statement, the serial port DTR pin can be pulled down. By controlling the high and low levels of the serial port DTR pin and through the select() function in the perl language, such as "select(undef,undef,undef,p*N)", the power on / off pulse time is controlled, thereby achieving the power on / off of the device under test according to the power on / off pulse time p*N. Among them, N is a variable parameter, and its value is an integer greater than 0.

[0032] S2, obtaining the on / off state of the device under test, and detecting the shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input.

[0033] In the embodiment of the present invention, Figure 2As shown, when starting the test, you can pre-configure test parameters such as pulse detection accuracy p (in milliseconds), number of consecutive power on / off successes s, etc. For example, you can configure the pulse detection accuracy p to 10ms and the number of consecutive power on / off successes s to 100 times. Figure 2 , you can also set the variable parameter n, for example, the initial value of n can be 0.

[0034] Specifically, as an example, Figure 2 As shown, during the power on / off test, let N=n++, and realize the power on test of the device under test by controlling the high / low level of the serial port DTR pin. Get the power on / off status. If the power on success mark such as "RDY" is detected according to the power on / off status, and the test shows that the serial port can communicate normally, it is determined that the device under test has been successfully powered on. When it is determined that the device under test has been successfully powered on, the device under test is controlled to be powered off according to the current power on / off pulse time p*N. Get the power on / off status again. If the shutdown is determined to be successful according to the power on / off status, return to the power on test step. Repeat this process until the value of the number of successful power on / off times r reaches the number of continuous successful power on / off times s. At this time, it can be determined that the above-mentioned current power on / off pulse time p*n is the shortest power on / off pulse.

[0035] In one embodiment of the present invention, when the power on / off pulse time is cyclically input to the device under test, the power on / off pulse time is controlled to increase in integer multiples in sequence according to a preset accuracy requirement, for example, n increases with a preset step size of 1.

[0036] Specifically, as another example, Figure 2 As shown, during the power on / off test, if the device under test fails to start up, or the power on / off according to p*N fails, then N=n++ is returned, and the value of N increases, so that the power on / off pulse time p*N increases.

[0037] For example, take p=10ms, s=100 times, and n=0 as an example. The first power on / off test is performed at 10ms. During the first test, if the number of consecutive power on / off successes reaches 50 times (less than 100 times), it is detected that the device under test fails to start up or shut down, then the power on / off pulse time is reset, and the power on / off pulse time is doubled to 20ms. The second power on / off test is performed at 20ms. Similarly, when the power on / off test is performed at 20ms, if the number of consecutive power on / off successes reaches 100 times, it is detected that the device under test fails to start up or shut down, then the power on / off pulse time is set to 30ms, and so on. If the number of consecutive power on / off successes reaches 100 times during the power on / off test at 50ms (the fifth test), 50ms is used as the shortest power on / off pulse time.

[0038] In one embodiment of the present invention, the shortest on / off pulse is detected according to the on / off state of the device under test and the on / off pulse time of the cyclic input, including: obtaining a preliminary shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; repeatedly applying the preliminary shortest on / off pulse to the device under test so that the device under test is repeatedly turned on and off; confirming whether the preliminary shortest on / off pulse is reliable according to the on / off state of the device under test, and when confirming that the preliminary shortest on / off pulse is reliable, using the preliminary shortest on / off pulse as the final shortest on / off pulse.

[0039] Specifically, when a power on / off test is performed according to a certain power on / off pulse time, such as 10ms*5=50ms, if the first power on / off test is successful, the initial shortest power on / off pulse time is determined to be 50ms, and the number of successful power on / off times r is increased by 1, and the shortest power on / off pulse corresponding to the 50ms is applied to the device under test again, so that the device under test can be repeatedly powered on and off. During the repeated power on / off process, whether 50ms is reliable is confirmed based on the power on / off status of the device under test. For example, in 100 power on / off tests, if the number of successful power on / offs (including the number of consecutive successful power on / offs) is greater than or equal to 95 times, then 50ms is considered reliable, and the initial shortest power on / off pulse time of 50ms is determined as the final shortest power on / off pulse time. Of course, if the power on / off is detected to be successful 95 times at any time between 95 and 100 times, the test can be stopped, and 50ms is directly determined as the final shortest power on / off pulse time.

[0040] In one embodiment of the present invention, when it is determined that the initial shortest on / off pulse is unreliable, the on / off pulse time is gradually increased according to a preset accuracy requirement.

[0041] Specifically, when the number of unsuccessful power on / off attempts is greater than or equal to a certain value, such as 5 times (including 5 consecutive unsuccessful attempts) in a preset number of tests, such as 100 times, the initial shortest power on / off pulse (such as 10ms*5=50ms) is considered unreliable, and the power on / off pulse time can be set to 10ms*10=100ms. If it is still unreliable, the power on / off pulse time is set to 10ms*15=150ms, and so on.

[0042] In summary, the method for detecting the shortest power-on / off pulse of the embodiment of the present invention can accurately calculate the shortest power-on / off pulse time by controlling the high and low levels of the serial port DTR pin and automatically detecting the power-on / off state by cyclically detecting the power-on reporting information and other interface loading states. This method has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0043] Furthermore, the present invention proposes a computer-readable storage medium on which a detection program for the shortest power-on / off pulse is stored. When the detection program is executed by a processor, the above-mentioned detection method for the shortest power-on / off pulse can be used.

[0044] The computer-readable storage medium of an embodiment of the present invention can accurately calculate the shortest on / off pulse time when the computer program corresponding to the above-mentioned on / off shortest pulse detection method is executed by a processor, and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0045] Furthermore, the present invention proposes a testing device, including a memory, a processor, and a detection program for the shortest power-on / off pulse stored in the memory and executable on the processor. When the processor executes the detection program, the above-mentioned detection method for the shortest power-on / off pulse can be implemented.

[0046] The test equipment of the embodiment of the present invention, when its processor executes the detection program of the shortest power-on and power-off pulse stored in the memory, can accurately calculate the shortest power-on and power-off pulse time, and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0047] Figure 3 FIG. 1 is a structural block diagram of a detection system for the shortest pulse of a power on / off machine according to an embodiment of the present invention. Figure 3 As shown, the detection system 100 for the shortest on / off pulse includes a pulse control module 10 , an acquisition module 20 and a shortest on / off pulse detection module 30 .

[0048] The pulse control module 10 is used to control the high and low levels of the serial port DTR pin after the serial port DTR pin of the device under test is connected to the power on / off pin, so as to cyclically input the power on / off pulse time to the device under test so as to power on / off the device under test.

[0049] Specifically, after the serial port DTR pin of the device under test is connected to the power on / off pin, the pulse control module 10 can use the perl language to communicate with the serial port through the serial port to control the high and low levels of the serial port DTR pin, that is, to achieve the control of pulling up or pulling down the serial port DTR pin, such as through the "$ob->dtr_active(F)" statement, the serial port DTR pin can be pulled up, and through the "$ob->dtr_active(T)" statement, the serial port DTR pin can be pulled down. By controlling the high and low levels of the serial port DTR pin, and through the select() function in the perl language, such as "select(undef,undef,undef,p*N)", the power on / off pulse time is controlled, thereby achieving the power on / off of the device under test according to the power on / off pulse time p*N. Wherein, N is a variable parameter, and its value is an integer greater than 0.

[0050] The acquisition module 20 is used to acquire the power on / off state of the device under test. The shortest power on / off pulse detection module 30 is used to detect the shortest power on / off pulse according to the power on / off state of the device under test and the power on / off pulse time input cyclically.

[0051] In the embodiment of the present invention, Figure 2 As shown, when starting the test, you can pre-configure test parameters such as pulse detection accuracy p (in milliseconds), number of consecutive power on / off successes s, etc. For example, you can configure the pulse detection accuracy p to 10ms and the number of consecutive power on / off successes s to 100 times. Figure 2 , you can also set the variable parameter n, for example, the initial value of n can be 0.

[0052] Specifically, as an example, Figure 2 As shown, during the power on / off test, let N=n++, and realize the power on test of the device under test by controlling the high / low level of the serial port DTR pin. The acquisition module 20 acquires the power on / off state of the device under test. If the shortest power on / off pulse detection module 30 detects a power on success mark such as "RDY" according to the power on / off state, and the serial port can communicate normally after testing, it is determined that the device under test has been successfully powered on. When it is determined that the device under test has been successfully powered on, the device under test is controlled to be powered off according to the current power on / off pulse time p*N. The acquisition module 20 acquires the power on / off state of the device under test again. If the shortest power on / off pulse detection module 30 determines that the shutdown is successful according to the power on / off state, it returns to the power on test step. This is repeated until the value of the number of successful power on / off times r reaches the number of continuous successful power on / off times s. At this time, it can be determined that the above-mentioned current power on / off pulse time p*n is the shortest power on / off pulse.

[0053] In one embodiment of the present invention, the pulse control module 10 is further used to control the power on / off pulse time to increase in integer multiples in sequence according to a preset accuracy requirement when cyclically inputting the power on / off pulse time to the device under test, for example, n increases with a preset step size of 1.

[0054] Specifically, as another example, Figure 2 As shown, during the power on / off test, if the device under test fails to start up, or the power on / off according to p*N fails, then N=n++ is returned, and the value of N increases, so that the power on / off pulse time p*N increases.

[0055] For example, take p=10ms, s=100 times, and n=0 as an example. The first power on / off test is performed at 10ms. During the first test, if the number of consecutive power on / off successes reaches 50 times (less than 100 times), it is detected that the device under test fails to start up or shut down, then the power on / off pulse time is reset, and the power on / off pulse time is doubled to 20ms. The second power on / off test is performed at 20ms. Similarly, when the power on / off test is performed at 20ms, if the number of consecutive power on / off successes reaches 100 times, it is detected that the device under test fails to start up or shut down, then the power on / off pulse time is set to 30ms, and so on. If the number of consecutive power on / off successes reaches 100 times during the power on / off test at 50ms (the fifth test), 50ms is used as the shortest power on / off pulse time.

[0056] In one embodiment of the present invention, the shortest on / off pulse detection module 30 is further used to obtain a preliminary shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; repeatedly apply the preliminary shortest on / off pulse to the device under test through the pulse control module 10 so that the device under test is repeatedly turned on and off; confirm whether the preliminary shortest on / off pulse is reliable according to the on / off state of the device under test, and when confirming that the preliminary shortest on / off pulse is reliable, use the preliminary shortest on / off pulse as the final shortest on / off pulse.

[0057] Specifically, when a power on / off test is performed according to a certain power on / off pulse time, such as 10ms*5=50ms, if the first power on / off test is successful, the initial shortest power on / off pulse time is determined to be 50ms, and the number of successful power on / off times r is increased by 1, and the shortest power on / off pulse corresponding to the 50ms is applied to the device under test again, so that the device under test can be repeatedly powered on and off. During the repeated power on / off process, whether 50ms is reliable is confirmed based on the power on / off status of the device under test. For example, in 100 power on / off tests, if the number of successful power on / offs (including the number of consecutive successful power on / offs) is greater than or equal to 95 times, then 50ms is considered reliable, and the initial shortest power on / off pulse time of 50ms is determined as the final shortest power on / off pulse time. Of course, if the power on / off is detected to be successful 95 times at any time between 95 and 100 times, the test can be stopped, and 50ms is directly determined as the final shortest power on / off pulse time.

[0058] In one embodiment of the present invention, the shortest on / off pulse detection module 30 is further configured to gradually increase the on / off pulse time according to a preset accuracy requirement through the pulse control module when it is determined that the preliminary shortest on / off pulse is unreliable.

[0059] Specifically, when the number of unsuccessful power on / off attempts is greater than or equal to a certain value, such as 5 times (including 5 consecutive unsuccessful attempts) in a preset number of tests, such as 100 times, the initial shortest power on / off pulse (such as 10ms*5=50ms) is considered unreliable, and the power on / off pulse time can be set to 10ms*10=100ms. If it is still unreliable, the power on / off pulse time is set to 10ms*15=150ms, and so on.

[0060] In summary, the detection system for the shortest power-on and power-off pulse of the embodiment of the present invention can accurately calculate the shortest power-on and power-off pulse time by controlling the high and low levels of the serial port DTR pin and automatically detecting the power-on status by cyclically detecting the power-on reporting information and other interface loading status, and has the advantages of low cost, high test accuracy, no need for special instrument circuit support, and short test cycle.

[0061] It should be noted that the logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in combination with these instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in combination with these instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer disk box (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing in other suitable ways if necessary, and then stored in a computer memory.

[0062] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0063] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0064] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0066] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0068] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A method for detecting the shortest pulse of power on / off, characterized in that: The following steps are involved: After the serial port DTR pin of the device under test is connected to the power on / off pin, the power on / off pulse time is cyclically input to the device under test by controlling the high and low levels of the serial port DTR pin, so that the device under test is turned on and off; Acquire the on / off state of the device under test, and detect the shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of cyclic input; When the power on / off pulse time is cyclically input to the device under test, the power on / off pulse time is controlled to increase in integer multiples in sequence according to a preset accuracy requirement.

2. The method for detecting the shortest pulse of power on / off according to claim 1, characterized in that: Detecting the shortest on / off pulse according to the on / off state of the device to be tested and the on / off pulse time of the cyclic input includes: Obtaining a preliminary shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; Repeatedly applying the preliminary shortest power-on / off pulse to the device under test so that the device under test is repeatedly powered on and off; Whether the preliminary shortest on / off pulse is reliable is confirmed according to the on / off state of the device under test, and when it is confirmed that the preliminary shortest on / off pulse is reliable, the preliminary shortest on / off pulse is used as the final shortest on / off pulse.

3. The method for detecting the shortest pulse of power on / off as claimed in claim 2, characterized in that: When it is confirmed that the preliminary shortest on / off pulse is unreliable, the on / off pulse time is gradually increased according to a preset accuracy requirement.

4. A computer-readable storage medium, characterized in that: A detection program for the shortest on / off pulse is stored thereon, and when the detection program is executed by a processor, a detection method for the shortest on / off pulse as described in any one of claims 1 to 3 is implemented.

5. A testing device, characterized in that: The invention comprises a memory, a processor and a detection program for the shortest power-on / off pulse stored in the memory and executable on the processor. When the processor executes the detection program, the detection method for the shortest power-on / off pulse according to any one of claims 1 to 3 is implemented.

6. A detection system for the shortest pulse of power on and off, characterized in that: include: A pulse control module is used to control the high and low levels of the serial port DTR pin to cyclically input the power on / off pulse time to the device under test after the serial port DTR pin of the device under test is connected to the power on / off pin, so as to power on / off the device under test; An acquisition module, used to acquire the power on / off status of the device under test; A shortest on / off pulse detection module, used to detect the shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; The pulse control module is also used to control the power on / off pulse time to increase in integer multiples in sequence according to a preset accuracy requirement when cyclically inputting the power on / off pulse time to the device under test.

7. The detection system for the shortest pulse of power on / off as claimed in claim 6, characterized in that: The shortest on / off pulse detection module is also used for: Obtaining a preliminary shortest on / off pulse according to the on / off state of the device under test and the on / off pulse time of the cyclic input; The pulse control module is used to repeatedly apply the preliminary shortest power-on and power-off pulse to the device under test, so that the device under test is repeatedly powered on and off; Whether the preliminary shortest on / off pulse is reliable is confirmed according to the on / off state of the device under test, and when it is confirmed that the preliminary shortest on / off pulse is reliable, the preliminary shortest on / off pulse is used as the final shortest on / off pulse.

8. The detection system for the shortest pulse of power on / off as claimed in claim 7, characterized in that: The shortest on / off pulse detection module is further configured to gradually increase the on / off pulse time according to a preset accuracy requirement through the pulse control module when it is determined that the preliminary shortest on / off pulse is unreliable.

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