Information matching detection circuit and electronic equipment

Abstract

The present invention discloses a detection circuit and electronic device for information matching, wherein the detection circuit comprises: a first switch, the number of which is multiple and the multiple first switches are connected in series to form a sub-circuit; a second switch, the number of which is at least one and each second switch is connected in series between a set power supply terminal and an input terminal of a first switch; wherein each first switch is controlled by a signal in a first signal group, and each second switch is controlled by a signal in a second signal group, so that when the information of the first signal group and the second signal group matches, the end of the sub-circuit is connected to the set power supply terminal through the closing of the first switch and the second switch to output a detection signal. The information matching detection circuit and electronic device provided by the present invention can save a lot of circuit area.

Description

Technical Field

[0001] The present invention relates to the technical field of device control, and more specifically, to an information matching detection circuit and electronic equipment. Background Art

[0002] In the field of device control, there may be a situation where a certain control process is associated with two signal groups. Specifically, multiple signals of the first signal group and one signal of the second signal group form multiple corresponding signal groups based on the cross-group correspondence of the signals. As long as one of these corresponding signal groups achieves information matching within the group, it means that the information of the two signal groups matches, and then corresponding control of the device is performed.

[0003] In the above control process, whether the information of the two signal groups matches needs to be detected by the detection circuit. The detection circuit outputs a detection signal by detecting multiple corresponding signal groups. If the detection signal indicates that there is a corresponding signal group with matching information within the group, the device is driven to perform corresponding control. At present, the detection circuit is constructed by basic logic circuits such as AND gate circuits, OR gate circuits and NOT gate circuits.

[0004] Since the detection circuit needs to detect multiple corresponding signal groups and detect whether the information carried by multiple signals in each corresponding signal group matches, more gate circuits are required, so the detection circuit requires a larger circuit area as a whole. Summary of the invention

[0005] In order to solve the problems existing in the above-mentioned prior art, the present invention provides an information matching detection circuit and electronic equipment, which can save a lot of circuit area.

[0006] According to a first aspect of the present invention, there is provided an information matching detection circuit, comprising:

[0007] There are a plurality of first switches, and the plurality of first switches are connected in series to form a sub-circuit;

[0008] There is at least one second switch, and each second switch is connected in series between the set power supply terminal and an input terminal of the first switch;

[0009] Wherein, each of the first switches is controlled by a signal in the first signal group, and each of the second switches is controlled by a signal in the second signal group, so that when the information of the first signal group and the second signal group matches, the end of the sub-circuit is connected to the set power supply end by closing the first switch and the second switch to output a detection signal.

[0010] Optionally, a plurality of the first switches on the subcircuit are controlled correspondingly by the signals of the first signal group in the order of appearance times from small to large in the corresponding signal group, and the signal with the largest appearance times controls the first switch connected in series with the end of the subcircuit;

[0011] The second switch connected to the input terminal of the target switch is controlled by a signal belonging to the second signal group in the current corresponding signal group, and the target switch is the first switch controlled by the signal with the least number of occurrences in the current corresponding signal group;

[0012] The corresponding signal group is a signal group formed by signals in the first signal group and the second signal group according to a cross-group correspondence relationship of the signals.

[0013] Optionally, the number of the first switches is equal to the number of signals in the first signal group, and the input end of each of the first switches is connected in series with a second switch.

[0014] Optionally, the number of the first switches is equal to the number of signals in the first signal group, and the number of the second switches is equal to the number of the corresponding signal groups.

[0015] Optionally, the first switch and the second switch are transistors of the same type.

[0016] Optionally, the detection circuit further includes:

[0017] Reset the power supply terminal;

[0018] The third transistor has a first channel end connected to the reset power supply end, a second channel end connected to the end of the sub-circuit, and a control end receiving a switch control signal of the detection circuit.

[0019] Optionally, the reset power supply terminal is a high-level power supply terminal, and the set power supply terminal is a low-level power supply terminal;

[0020] The third transistor is a PMOS transistor, the first channel end is a source of the PMOS transistor, the second channel end is a drain of the PMOS transistor, and the control end is a gate of the PMOS transistor;

[0021] The first switch is an NMOS tube, the input end of the first switch is the source of the NMOS tube and the output end is the drain of the NMOS tube, and the end of the first switch receiving the signal of the first signal group is the gate of the NMOS tube;

[0022] The second switch is an NMOS tube, one end of the second switch connected to the set power supply end is the NMOS tube source, one end connected to the first switch is the NMOS tube drain, and one end receiving the second signal group signal is the NMOS tube gate.

[0023] Optionally, the detection circuit further includes:

[0024] an inverter having an input terminal connected to a terminal of the sub-circuit;

[0025] A PMOS tube, a source connected to the high-level power supply terminal, a drain connected to the input terminal of the inverter, and a gate connected to the output terminal of the inverter;

[0026] Furthermore, the output end of the inverter serves as the detection signal output end of the detection circuit.

[0027] Optionally, the detection circuit further includes:

[0028] an inverter having an input terminal connected to a terminal of the sub-circuit;

[0029] An NMOS tube, a source connected to the low-level power supply terminal, a drain connected to the input terminal of the inverter, and a gate connected to the output terminal of the inverter;

[0030] Furthermore, the output end of the inverter serves as the detection signal output end of the detection circuit.

[0031] According to a second aspect of the present invention, an electronic device is provided, comprising a controlled device and the detection circuit according to the first aspect, wherein the controlled device and a detection signal output terminal of the detection circuit are connected to be controlled by the detection signal.

[0032] The beneficial effects of the embodiments of the present invention are:

[0033] By connecting a plurality of first switches in series and connecting a second switch in series between the first switch input terminal and the set power supply terminal, a circuit can simultaneously detect information matching for a plurality of corresponding signal groups, thereby improving circuit utilization and reducing the total area of ​​the detection circuit; and, the detection circuit constructed by the plurality of first switches and the second switches has fewer circuit elements, thereby achieving the purpose of reducing the circuit area occupied, and thus the circuit area of ​​the detection circuit is greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0035] Figure 1 A circuit diagram of a detection circuit in a first embodiment of the present invention is shown;

[0036] Figure 2 FIG. 2 is a circuit diagram showing another detection circuit in the first embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown in the drawings.

[0038] Many specific details of the present invention are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present invention. However, as those skilled in the art will appreciate, the present invention may be implemented without following these specific details.

[0039] In the field of device control, there may be a situation where a certain control process is associated with two signal groups. Specifically, multiple signals of the first signal group and one signal of the second signal group form multiple corresponding signal groups based on the cross-group correspondence of the signals. As long as one of these corresponding signal groups achieves information matching within the group, it means that the information of the two signal groups matches, and then corresponding control of the device is performed.

[0040] For example, there is a first area in the storage area of ​​the computer system hard disk that is only readable but not erasable, and the address decoding of the first area is 111, which is represented by high-level signals Y1, Y2 and Y3 (Y1=1, Y2=1 and Y3=1); there is a second area in the USB flash drive (universal serial bus disk, referred to as U disk) that is only readable but not erasable, and the address decoding of the second area is 11, which is represented by high-level signals Y2 and Y3 (Y2=1 and Y3=1), wherein the signals Y1, Y2 and Y3 are signals in the first signal group Y, namely Y={Y1, Y2, Y3}. Also, the operation signal of the computer system hard disk is signal X1, and the high-level signal X1 (X1=1) indicates that the computer system hard disk is operated; the operation signal of the USB flash drive is signal X2, and the high-level signal X2 (X2=1) indicates that the computer system hard disk is operated, wherein the signals X1 and X2 are signals in the second signal group X, namely X={X1, X2}. Here, there is a cross-group correspondence between signal X1 and signals Y1, Y2 and Y3, so that signal X1 and signals Y1, Y2 and Y3 form a corresponding signal group Z1={X1, Y1, Y2, Y3}; there is a cross-group correspondence between signal X2 and signals Y2 and Y3, so that signal X2 and signals Y2 and Y3 form a corresponding signal group Z1={X2, Y2, Y3}, therefore, when X1=1 and Y1=1, Y2=1, Y3=1, the information in the corresponding signal group Z1 matches; when X2=1 and Y2=1, Y3=1, the information in the corresponding signal group Z2 matches. If the information in the first signal group Y and the second signal group X is matched, and the information in the corresponding signal group Z1 and the corresponding signal group Z2 is matched, and then the storage device currently being operated is controlled to be readable but not erasable, which means: when operating the hard disk of the computer system, if the current operating area is determined to be the first area according to the information of the signal in the first signal group, then the control is performed so that it can only be read but not erased; when operating the USB flash drive, if the current operating area is determined to be the second area according to the information of the signal in the second signal group, then the control is performed so that it can only be read but not erased.

[0041] In the control process of the above storage system, whether the information of the first signal group Y representing the address decoding and the second signal group X representing the operation signal match needs to be detected by the detection circuit. The detection circuit detects the matching information of the first signal group Y and the second signal group X representing the operation signal by detecting the matching information of the first signal group Y and the second signal group X. w (w=1, 2, ..., u, u is the number of corresponding signal groups) and output a detection signal OUT. If the detection signal OUT indicates that there is a corresponding signal group Z with matching information within the group w The device is then driven to perform corresponding control. At present, the detection circuit of the storage system is built by basic logic circuits such as AND gate circuits, OR gate circuits and NOT gate circuits. wDetect and detect each corresponding signal group Z w The information carried by multiple signals in the detection circuit is matched, so more gate circuits are required, so the detection circuit requires a larger circuit area as a whole. Based on this, the embodiment of the present invention provides an information matching detection circuit and electronic device to achieve the technical effect of reducing the area occupied by the detection circuit.

[0042] Figure 1 FIG. 1 is a circuit diagram of a detection circuit in the first embodiment of the present invention. Figure 1 A first embodiment of the present invention will be described in detail.

[0043] The information matching detection circuit includes:

[0044] The number of the first switches M1_i is m (m is an integer greater than 1), and the m first switches M1_i are connected in series to form a sub-circuit;

[0045] There is at least one second switch M2_j, and each second switch M2_j is connected in series between the set power supply terminal V1 and an input terminal of a first switch M1_i;

[0046] Each first switch M1_i receives a signal Y in the first signal group Y. i Each second switch M2_j is controlled by a signal X in the second signal group X. j The control is performed so that when the information of the first signal group Y and the second signal group X match, the terminal Q of the sub-circuit is connected to the setting power supply terminal V1 by closing the first switch M1_i and the second switch M2_j to output the detection signal OUT.

[0047] Specifically, when the information of the first signal group Y and the second signal group X matches, the end Q of the sub-circuit is connected to the set power supply terminal V1; when the information of the first signal group Y and the second signal group X does not match, the end Q of the sub-circuit is not connected to the set power supply terminal V1. In the two cases where the end Q of the sub-circuit is connected to the set power supply terminal V1 and is not connected to the set power supply terminal V1, the potential of the end Q of the sub-circuit is different, so the potential of the end Q of the sub-circuit can represent whether the information between the first signal group Y and the second signal group X matches, that is, the end Q of the sub-circuit can output the detection signal OUT to represent whether the information between the first signal group Y and the second signal group X matches through the detection signal OUT.

[0048] For the first switches M1_i, it should be noted that each first switch M1_i includes an input end and an output end, and m first switches M1_i are connected in series as a sub-circuit, which means: the input end of the first switch M1_1 is the starting end of the sub-circuit, and the output end of the m-th first switch M1_m is the end of the sub-circuit, and the series connection between the i-th first switch M1_i and the (i+1)-th first switch M1_(i+1) is that the output end of the i-th first switch M1_i is connected to the input end of the (i+1)-th first switch M1_(i+1).

[0049] As for the second switch M2_j, it should be noted that each second switch M2_j also includes an input terminal and an output terminal, the input terminal of each second switch M2_j is connected to the set power supply terminal V1 and the output terminal is connected to the input terminal of a first switch M1_i, and the input terminal of each first switch M1_i is connected to the output terminal of at most one second switch M2_j.

[0050] It should be understood that there are n (n is an integer greater than 0) optional circuits between the set power supply terminal V1 and the end Q of the sub-circuit, wherein the optional circuits and the second switches M2_j are in a one-to-one correspondence, and thus the above n is also the number of the second switches M2_j; and the starting element of each optional circuit is a second switch M2_j and the terminal element is a first switch M1_i. For each optional circuit, the signal X controlling a second switch M2_j j and a signal Y controlling at least one first switch M1_i i Form a corresponding signal group Z w , if all switch elements in the optional circuit are affected by the corresponding signal group Z w When (a second switch M2_j and at least one first switch M1_i) are closed, the optional circuit is turned on. The conduction of the optional circuit means that the corresponding signal group Z of all switch elements on the optional circuit is controlled. w And, when the end Q of the sub-circuit is connected to the set power supply terminal V1, the information of the first signal group Y and the second signal group X are matched. At this time, at least one optional circuit is turned on, which means that at least one corresponding signal group Z w Internal information matching.

[0051] The information matching detection circuit provided in the embodiment of the present invention can simultaneously detect multiple corresponding signal groups Z by connecting multiple first switches M1_i in series and connecting a second switch M2_j in series between the input terminal of the first switch M1_i and the set power supply terminal V1. wInformation matching detection is performed, which improves circuit utilization and reduces the total area of ​​the detection circuit; and, the detection circuit constructed by the plurality of first switches M1_i and second switches M2_j has fewer circuit elements, thereby achieving the purpose of reducing the circuit area occupied, and thus the circuit area of ​​the detection circuit is greatly reduced.

[0052] In an optional embodiment, the plurality of first switches M1_i on the sub-circuit are pressed by the first signal group Y signal to the corresponding signal group Z w The signal with the largest number of occurrences controls the first switch M1_i connected in series with the sub-circuit terminal Q; the second switch M2_j connected to the target switch input terminal controls the signal with the largest number of occurrences in the sequence from the least to the most occurrences; w The signal control of the second signal group X in the example above enables an information matching detection circuit to simultaneously detect all corresponding signal groups Z. w The target switch is the current corresponding signal group Z. w The first switch controlled by the signal with the least number of occurrences in the signal group Z; w It is a signal group formed by the signals in the first signal group Y and the second signal group X according to the cross-group correspondence of the signals.

[0053] For example, corresponding to signal group Z w There are 8 pixels in total, namely Z1={X1, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z2={X2, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z3={X3, Y3, Y4, Y5, Y6, Y7, Y8}, Z4={X4, Y4, Y5, Y6, Y7, Y8}, Z5={X5, Y5, Y6, Y7, Y8} , Z6={X6, Y6, Y7, Y8}, Z7={X7, Y7, Y8}, Z8={X8, Y8}, where signals X1, X2, X3, X4, X5, X6, X7, X8 are signals in the second signal group X, and signals Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 are signals in the first signal group Y. It can be seen that the signals in the first signal group Y are in the corresponding signal group Z w The order of occurrence from least to most is: Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8; and the number of first switches M1_i is 8 and the 8 first switches M1_i are connected in series as a sub-circuit in the order of M1_1, M1_2, M1_3, M1_4, M1_5, M1_6, M1_7, M1_8, so that the first switch M1_i is driven by the signal Y iThe corresponding control is performed, and the signal Y8 controls the first switch M1_8 connected in series with the sub-circuit end Q; in addition, the corresponding signal group Z w and the first switch M1_i, for the current signal group Z v For example, the target switch is the first switch M1_v, and the second switch M2_j connected to the input end of the target switch M1_v is connected to the input end of the target switch M1_v by the current corresponding signal group Z. v The signal X belonging to the second signal group X v Control; and, corresponding signal group Z w The number of first switches M1_i and second switches M2_j is 8. Accordingly, the number of target switches is 8, and the number of second switches M2_j is also 8. The connection method of the 8 first switches M1_i and the 8 second switches M2_j is as follows: Figure 1 shown.

[0054] It should be emphasized that, in the above example, the number of signals in the corresponding signal groups Z1 to Z8 decreases by 1 in sequence. Of course, the number of signals in the multiple corresponding signal groups may not decrease by 1 in sequence in the order of the signals contained from most to least. For example, the corresponding signal groups of the first group of signals Y and the second group of signals X can be Z1={X1, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z2={X5, Y5, Y6, Y7, Y8}, Z3={X8, Y8}. At this time, the corresponding control relationship between the first signal group Y and the eight first switches M1_i remains unchanged, while the number of target switches and the second switches M2_j are both 3 and only X1, X5 and X8 in the second signal group X participate in the control of the multiple second switches M2_j.

[0055] It should be noted that:

[0056] (1) The information matching detection circuit can be as follows Figure 1 The configuration shown is as follows: the number of first switches M1_i is equal to the number of signals in the first signal group Y, and the input end of each first switch M1_i is serially connected with a second switch M2_j, that is, the number of second switches M2_j is equal to the number of first switches M2_j, so that a detection circuit can detect the maximum number of corresponding signal groups Z. w and if the number of signals in the first signal group Y remains unchanged, the number of signals in the second signal group X changes but is never greater than the number of signals in the first signal group Y, and the corresponding signal group Z w If the number changes, the detection circuit is always available, that is, the universality of the detection circuit is better.

[0057] Among them, if the corresponding signal group Z wIf the signal changes, the control signals of each first switch M1_i and each second switch M2_j can be adjusted according to the control relationship between the first switch M1_i, the second switch M2_j and the first signal group Y, the second signal group X, which will not be repeated here.

[0058] It should be understood here that the corresponding signal group Z is formed by a signal in the second signal group X corresponding to a signal in the first signal group Y. w , so the corresponding signal group Z w The maximum number is limited by the number of signals in the second signal group X.

[0059] (2) The information matching detection circuit can also be configured as follows: the number of first switches M1_i is equal to the number of signals in the first signal group Y, and the number of second switches M2_j is equal to the number of signals in the corresponding signal group Z. w The number of is equal, so that the corresponding signal group Z constructed for the current first signal group Y and the second signal group X w In general, there is no dummy situation of the first switch M1_i and the second switch M2_j, that is, the number of the first switch M1_i and the second switch M2_j is the minimum, which is beneficial to save circuit area.

[0060] When the information matching detection circuit selects any of the above configuration modes, the arrangement of the first switch M1_i and the second switch M2_j on the circuit board can be as follows: Figure 1 As shown, the first switches M1_i are arranged in a column, and the second switches M2_j are arranged in a row. The column in which the first switches M1_i are arranged and the row in which the second switches M2_j are arranged are perpendicular to each other, and the first second switch M2_j is placed at the beginning of the column in which the first switches M1_i are arranged. Of course, the arrangement of the first switches M1_i and the second switches M2_j on the circuit board can also be: the first switches M1_i are arranged in a column, and the second switches M2_j are arranged near the target switch to be connected.

[0061] Furthermore, the first switch M1_i and the second switch M2_j are transistors of the same type, for example, the first switch M1_i and the second switch M2_j are both NMOS transistors; for another example, the first switch M1_i and the second switch M2_j are both PMOS transistors. w Internal information matching, that is: corresponding signal group Z w All internal signals are high level or corresponding to signal group Z w The internal signals are all low level, so the information matching detection circuit can detect the corresponding signal group Z w The level states of the signals in the corresponding signal group Z are exactly the same. wThe information carried by the internal signal in the high level state and the information carried in the low level state can be set according to the specific application scenario.

[0062] For the case where both the first switch M1_i and the second switch M2_j are NMOS transistors, if the corresponding signal group Z w There are 8 of them, and they are Z1={X1, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z2={X2, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z3={X3, Y3, Y4, Y5, Y6, Y7, Y8}, Z4={X4, Y4, Y5, Y6, Y7, Y8}, Z5={X5, Y5, Y6, Y7, Y8}, Z6={X6, Y6, Y7, Y8}, Z7={X 7, Y7, Y8}, Z8={X8, Y8}, wherein the signals X1, X2, X3, X4, X5, X6, X7, X8 are signals in the second signal group X, and the signals Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 are signals in the first signal group Y, then as long as there is a corresponding signal group in the corresponding signal groups Z1 to Z8 that is a high level signal, the output detection signal OUT indicates that the first signal group Y and the second signal group X achieve information matching.

[0063] Similarly, for the case where both the first switch M1_i and the second switch M2_j are PMOS transistors, if the corresponding signal group Z w There are 8 of them, and they are Z1={X1, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z2={X2, Y2, Y3, Y4, Y5, Y6, Y7, Y8}, Z3={X3, Y3, Y4, Y5, Y6, Y7, Y8}, Z4={X4, Y4, Y5, Y6, Y7, Y8}, Z5={X5, Y5, Y6, Y7, Y8}, Z6={X6, Y6, Y7, Y8}, Z7={X 7, Y7, Y8}, Z8={X8, Y8}, wherein the signals X1, X2, X3, X4, X5, X6, X7, X8 are signals in the second signal group X, and the signals Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8 are signals in the first signal group Y, then as long as there is a corresponding signal group in the corresponding signal groups Z1 to Z8 that is a low level signal, the output detection signal OUT indicates that the first signal group Y and the second signal group X achieve information matching.

[0064] In another optional embodiment, the detection circuit further includes: a reset power supply terminal V2; a third transistor M3, a first channel terminal connected to the reset power supply terminal V2, a second channel terminal connected to the end Q of the sub-circuit, and a control terminal receiving a switch control signal PRE_CHG of the detection circuit. Specifically, after the detection circuit is turned on by the switch control signal PRE_CHG, the third transistor M3 is in a closed state, and at this time, the end Q of the sub-circuit is connected to the reset power supply terminal V2.

[0065] It should be noted that the second switch M2_j, the first switch M1_i and the third transistor M3 between the set power supply terminal V1 and the reset power supply terminal V2 are not ideal resistance-free elements. Therefore, after the third transistor M3 is turned on, if there is no conduction between the sub-circuit terminal Q and the set power supply terminal V1, the potential V Q1 = The voltage of the reset power supply terminal V2 minus the voltage drop on the third transistor M3; if the sub-circuit terminal Q is connected to the set power supply terminal V1, the potential V Q2 The voltage between the set power supply terminal V1 and the reset power supply terminal V2 is obtained by dividing the voltage through the second switch M2_j, the first switch M1_i and the third transistor M3. Therefore, by properly configuring the set power supply terminal V1, the reset power supply terminal V2 and the second switch M2_j, the first switch M1_i and the third transistor M3, V Q1 ≠V Q2 , that is, the signal output by the sub-circuit end Q can be used as the detection signal OUT, and the detection signal OUT represents whether the information between the first signal group Y and the second signal group X matches through the level state.

[0066] Further, the set power supply terminal V1 is a low-level power supply terminal, and the reset power supply terminal V2 is a high-level power supply terminal; the third transistor M3 is a PMOS tube, the first channel terminal is the PMOS tube source, the second channel terminal is the PMOS tube drain, and the control terminal is the PMOS tube gate; the first switch M1_i is an NMOS tube, the input terminal of the first switch M1_i is the NMOS tube source and the output terminal is the NMOS tube drain, and the end of the first switch M1_i receiving the first signal group signal is the NMOS tube gate; the second switch M2_j is an NMOS tube, the end of the second switch M2_j connected to the set power supply terminal V1 is the NMOS tube source, the end connected to the first switch M1_i is the NMOS tube drain, and the end receiving the second signal group X signal is the NMOS tube gate. Specifically, the set power supply terminal V1 can be grounded, and the reset power supply terminal V2 is connected to the power supply device, so that the NMOS tube serves as a pull-down tube of the sub-circuit end Q, and the PMOS tube serves as a pull-up tube of the sub-circuit end Q.

[0067] In another optional embodiment, the detection circuit is as follows Figure 1The circuit shown also includes: an inverter D, whose input end is connected to the terminal Q of the sub-circuit; a P-type MOS tube M4, whose source is connected to the high-level power supply terminal V2, whose drain is connected to the input end of the inverter D, and whose gate is connected to the output end of the inverter D; and, whose output end is used as the detection signal output end of the detection circuit to output the detection signal OUT. Therefore, if the terminal Q of the sub-circuit outputs a high-level signal, the high-level signal is converted into a low-level signal after the inverter D, and the low-level signal controls the drain and source of the PMOS tube to be turned on so that the drain of the PMOS tube outputs a high-level signal to the input end of the inverter D; if the terminal Q of the sub-circuit outputs a low-level signal, the low-level signal is converted into a high-level signal after the inverter D, and the high-level signal controls the drain and source of the PMOS tube to be turned off so that the input end of the inverter D maintains a low level. It can be seen that the combination of the inverter D and the PMOS tube plays the role of latching the signal at the terminal Q of the sub-circuit. It should be noted that in the embodiment of the present invention, the detection signal OUT output by the detection circuit through the inverter D and the signal at the end Q of the sub-circuit are in opposite level states.

[0068] In another optional embodiment, the detection circuit is as follows Figure 2 The figure also includes: an inverter D, whose input end is connected to the terminal Q of the sub-circuit; an NMOS tube, whose source is connected to the low-level power supply terminal V1, whose drain is connected to the input end of the inverter D, and whose gate is connected to the output end of the inverter D; and, whose output end of the inverter D serves as the detection signal output end of the detection circuit. Therefore, if the terminal Q of the sub-circuit outputs a high-level signal, the high-level signal is converted into a low-level signal after the inverter D, and then the low-level signal controls the drain and source of the NMOS tube to be disconnected so that the input end of the inverter D maintains a high level; if the terminal Q of the sub-circuit outputs a low-level signal, the low-level signal is converted into a high-level signal after the inverter D, and the high-level signal controls the drain and source of the NMOS tube to be turned on so that the drain of the NMOS tube outputs a low-level signal to the input end of the inverter D. It can be seen that the combination of the inverter D and the NMOS tube plays the role of latching the signal at the terminal Q of the sub-circuit. It should be noted that in the embodiment of the present invention, the detection signal OUT output by the detection circuit through the inverter D and the signal at the end Q of the sub-circuit are in opposite level states.

[0069] With respect to the information matching detection circuit provided in the first embodiment, the second embodiment of the present invention further provides an electronic device, which includes a controlled device and the detection circuit described in the first embodiment, and the detection signal output ends of the controlled device and the detection circuit are connected to be controlled by the detection signal. Thus, the electronic device achieves the technical effect of occupying less circuit area by using the detection circuit provided in the first embodiment.

[0070] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0071] According to the embodiments of the present invention, as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. An information matching detection circuit, characterized in that: include: There are a plurality of first switches, and the plurality of first switches are connected in series to form a sub-circuit; There is at least one second switch, and each second switch is connected in series between the set power supply terminal and an input terminal of the first switch; Wherein, each of the first switches is controlled by a signal in the first signal group, and each of the second switches is controlled by a signal in the second signal group, so that when the information of the first signal group and the second signal group matches, the end of the sub-circuit is connected to the set power supply terminal by closing the first switch and the second switch to output the detection signal; Wherein, the plurality of first switches on the subcircuit are controlled correspondingly by the signals of the first signal group in the order of appearance times from small to large in the corresponding signal group, and the signal with the largest appearance times controls the first switch connected in series at the end of the subcircuit; The second switch connected to the input terminal of the target switch is controlled by a signal belonging to the second signal group in the current corresponding signal group, and the target switch is the first switch controlled by the signal with the least number of occurrences in the current corresponding signal group; The corresponding signal group is a signal group formed by signals in the first signal group and the second signal group according to a cross-group correspondence relationship of the signals.

2. The detection circuit according to claim 1, characterized in that: The number of the first switches is equal to the number of signals in the first signal group, and the input end of each of the first switches is serially connected to a second switch.

3. The detection circuit according to claim 1, characterized in that: The number of the first switches is equal to the number of signals in the first signal group, and the number of the second switches is equal to the number of the corresponding signal groups.

4. The detection circuit according to claim 1, characterized in that: The first switch and the second switch are transistors of the same type.

5. The detection circuit according to claim 1, characterized in that: Also includes: Reset the power supply terminal; The third transistor has a first channel end connected to the reset power supply end, a second channel end connected to the end of the sub-circuit, and a control end receiving a switch control signal of the detection circuit.

6. The detection circuit according to claim 5, characterized in that: The reset power supply terminal is a high-level power supply terminal, and the set power supply terminal is a low-level power supply terminal; The third transistor is a PMOS tube, the first channel end is a source of the PMOS tube, the second channel end is a drain of the PMOS tube, and the control end is a gate of the PMOS tube; The first switch is an NMOS tube, the input end of the first switch is the source of the NMOS tube and the output end is the drain of the NMOS tube, and the end of the first switch receiving the signal of the first signal group is the gate of the NMOS tube; The second switch is an NMOS tube, one end of the second switch connected to the set power supply end is the NMOS tube source, one end connected to the first switch is the NMOS tube drain, and one end receiving the second signal group signal is the NMOS tube gate.

7. The detection circuit according to claim 6, characterized in that: Also includes: an inverter having an input terminal connected to a terminal of the sub-circuit; A PMOS tube, a source connected to the high-level power supply terminal, a drain connected to the input terminal of the inverter, and a gate connected to the output terminal of the inverter; Furthermore, the output end of the inverter serves as the detection signal output end of the detection circuit.

8. The detection circuit according to claim 6, characterized in that: Also includes: an inverter having an input terminal connected to a terminal of the sub-circuit; An NMOS tube, a source connected to the low-level power supply terminal, a drain connected to the input terminal of the inverter, and a gate connected to the output terminal of the inverter; Furthermore, the output end of the inverter serves as the detection signal output end of the detection circuit.

9. An electronic device, characterized in that: The invention comprises a controlled device and the detection circuit according to any one of claims 1 to 8, wherein the controlled device and the detection signal output terminal of the detection circuit are connected to be controlled by the detection signal.

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