Single crystal silicon local SOI substrate, optoelectronic device and preparation method

Abstract

The present invention provides a single crystal silicon local SOI substrate, optoelectronic device and preparation method, the preparation method comprising: 1) etching a local SOI regional groove on a silicon substrate; 2) depositing a dielectric layer on the local SOI regional groove and the surface of the silicon substrate, and polishing to form a flat surface, the flat surface stays on the surface of the dielectric layer, and etching a seed groove in the dielectric layer; 3) depositing an amorphous silicon layer on the seed groove and the surface of the dielectric layer, polishing to form a flat surface, and recrystallizing the amorphous silicon layer through a thermal annealing solid phase epitaxial process to form a single crystal silicon layer, so as to form the single crystal silicon local SOI substrate; 4) preparing electrical devices on the silicon substrate and the single crystal silicon layer above it, and preparing optical devices on the single crystal silicon layer on the dielectric layer. The method of the present invention can form a local SOI on a bulk silicon substrate, thereby realizing the monolithic integration of optical chips and electrical chips.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor materials and devices, and in particular relates to a single crystal silicon local SOI substrate, a photoelectric device and a preparation method thereof. Background Art

[0002] Optoelectronic integration technology is one of the key technologies for the development of the future information industry. It is a key technical solution for achieving chip miniaturization, overcoming signal delays and breaking through the bottleneck of Moore's Law. At present, the solution for optoelectronic integration is to make electrical chips and optical chips on different chips, and then realize optoelectronic interconnection through wire bonding, flip-chip bonding, 2.5D / 3D and other technologies. Using standard CMOS process to realize monolithic integration of electrical chips and optical chips on the same substrate can effectively improve chip integration and chip rate, while reducing process costs. It is one of the important development directions of optoelectronic integrated chips. However, as the dominant manufacturing platform for microelectronic chips (Intel, Apple, Nvidia CPU / GPU, full computer memory, flash memory, etc.), the bulk silicon CMOS process lacks a semiconductor material with suitable optical properties to realize large-scale active and passive photonic functions. So far, all efforts to integrate optical chips into CMOS have been limited to silicon on insulator (SOI) material manufacturers. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a single-crystal silicon local SOI substrate, an optoelectronic device and a preparation method, which are used to solve the problem in the prior art that it is difficult to improve the performance of optical chips prepared based on polycrystalline silicon SOI materials.

[0004] To achieve the above-mentioned purpose and other related purposes, the present invention provides a method for preparing a single-crystal silicon local SOI substrate, the preparation method comprising the following steps: 1) providing a silicon substrate, etching a local SOI regional groove on the silicon substrate; 2) depositing a dielectric layer in the local SOI regional groove and the surface of the silicon substrate, and performing a chemical mechanical polishing process to form a flat surface, the flat surface stays on the surface of the dielectric layer, and a seed groove is etched in the dielectric layer, the seed groove exposes the surface of the silicon substrate; 3) depositing an amorphous silicon layer on the seed groove and the surface of the dielectric layer, using a chemical mechanical polishing process to form a flat surface, and recrystallizing the amorphous silicon layer through a thermal annealing solid phase epitaxial process to form a single-crystal silicon layer covering the surface of the silicon substrate and the dielectric layer, so as to form the single-crystal silicon local SOI substrate.

[0005] Optionally, the depth of the local SOI region groove is between 1 micron and 10 microns.

[0006] Optionally, in step 2), a dielectric layer is deposited in the local SOI region groove and on the surface of the silicon substrate using a chemical vapor deposition process, wherein the thickness of the dielectric layer is greater than the depth of the local SOI region groove, and the material of the dielectric layer includes one of silicon dioxide, silicon oxynitride and silicon nitride.

[0007] Optionally, in step 3), a magnetron sputtering method or a chemical vapor deposition method is used to deposit an amorphous silicon layer on the seed groove and the surface of the dielectric layer, and the thickness of the amorphous silicon layer is between 50 nanometers and 5000 nanometers.

[0008] Optionally, in step 3), the annealing temperature of the thermal annealing solid phase epitaxy process is between 500 and 1200° C., and the annealing time is between 0.5 minutes and 120 minutes.

[0009] The present invention also provides a method for preparing an optoelectronic device based on a single crystal silicon local SOI substrate, the preparation method comprising the steps of: 1) preparing a single crystal silicon local SOI substrate using a preparation method for a single crystal silicon local SOI substrate; 2) preparing electrical devices on the silicon substrate and the single crystal silicon layer above it, and preparing optical devices on the single crystal silicon layer on the dielectric layer.

[0010] Optionally, the electrical device includes one or more of a semiconductor transistor, a diode, a resistor and a capacitor, and the optical device includes one or more of an optical waveguide, an active device and a passive device.

[0011] The present invention also provides a single crystal silicon local SOI substrate, comprising: a silicon substrate having a local SOI area groove; a dielectric layer filled in the local SOI area groove and covering the surface of the silicon substrate, the dielectric layer having a seed groove, the seed groove exposing the silicon substrate; a single crystal silicon layer filled in the seed groove and covering the surface of the dielectric layer, the single crystal silicon layer contacting the silicon substrate at the bottom of the seed groove.

[0012] Optionally, the depth of the local SOI region groove is between 1 micron and 10 microns.

[0013] Optionally, the material of the dielectric layer includes one of silicon dioxide, silicon oxynitride and silicon nitride.

[0014] Optionally, the thickness of the amorphous silicon layer is between 50 nanometers and 5000 nanometers.

[0015] The present invention also provides an optoelectronic device based on a single crystal silicon local SOI substrate, comprising: a single crystal silicon local SOI substrate; an electrical device prepared on the silicon substrate and the single crystal silicon layer above it; and an optical device prepared on the single crystal silicon layer on the dielectric layer.

[0016] Optionally, the electrical device includes one or more of a semiconductor transistor, a diode, a resistor and a capacitor, and the optical device includes one or more of an optical waveguide, an active device and a passive device.

[0017] As described above, the crystalline silicon localized SOI substrate, optoelectronic device and preparation method of the present invention have the following beneficial effects:

[0018] First, compared with the solution of integrating optoelectronic devices on SOI substrate, the present invention can realize the integration of optoelectronic devices on bulk silicon and local SOI, that is, electrical devices can be integrated on bulk silicon and optical devices can be integrated on local SOI, with better electrical performance and lower cost.

[0019] Second, compared with the existing polycrystalline silicon local SOI solution on bulk silicon, the present invention can realize single crystal silicon local SOI through a special solid phase epitaxial process, which can effectively improve the performance of optical devices.

[0020] Third, part of the dielectric layer on the bulk silicon substrate is retained, that is, a thinner dielectric layer is also inserted into the bulk silicon substrate, and a seed groove is formed to facilitate solid phase epitaxy. Retaining a thinner dielectric layer can enable the electrical device to obtain a certain degree of SOI effect, such as reducing the latch-up effect of CMOS. At the same time, the single crystal silicon layer in the seed groove is in contact with the bulk silicon, which can suppress the floating body effect of SOI to a certain extent, thereby greatly improving the overall performance of the electrical device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic flow chart of the steps of a method for preparing an optoelectronic device based on a single-crystal silicon local SOI substrate according to an embodiment of the present invention.

[0022] Figure 2 to Figure 9 Shown is a schematic structural diagram of each step of a method for preparing an optoelectronic device based on a single-crystal silicon localized SOI substrate according to an embodiment of the present invention.

[0023] Component number description

[0024] 101 Silicon substrate

[0025] 102 Local SOI Area Slot

[0026] 103 Dielectric layer

[0027] 104 Amorphous silicon layer

[0028] 105 single crystal silicon layer

[0029] 106 Electrical Devices

[0030] 107 Optical Devices

[0031] 201 Seed slot

[0032] S11~S14 Step 1)~Step 4) DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0035] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0036] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0038] Research has found that optical chips can be prepared by depositing polycrystalline silicon materials on silicon dioxide (SiO2) to form a local SOI substrate. However, there is still a large gap in performance between optical chips prepared based on polycrystalline silicon SOI materials and those prepared based on single crystal silicon SOI materials.

[0039] like Figure 1 and Figure 2 to Figure 9As shown, this embodiment provides a single crystal silicon local SOI substrate and a method for preparing an optoelectronic device based on the single crystal silicon local SOI substrate, the preparation method comprising the steps of:

[0040] like Figure 1 and Figure 2-3 As shown, firstly, step 1) S11 is performed to provide a silicon substrate 101 and to etch a local SOI region groove 102 on the silicon substrate 101 .

[0041] For example, a local SOI regional groove 102 can be defined in the silicon substrate 101 (such as a single crystal silicon wafer, etc.) by a photolithography process, and then the local SOI regional groove 102 can be etched on the silicon substrate 101 by an etching process. The depth of the local SOI regional groove 102 can be between 1 micron and 10 microns. The above depth range can ensure that the subsequent dielectric layer 103 has sufficient isolation effect while avoiding the increase in etching cost due to excessive depth of the regional groove. In this embodiment, the opening depth is 2.2 microns. The width of the local SOI regional groove 102 can be determined according to the area required by the subsequent device, such as 10 microns to 100 microns, etc. Of course, the depth and width of the local SOI regional groove 102 can be selected according to actual needs, and are not limited to the examples listed here.

[0042] Furthermore, after etching the local SOI region groove 102, the silicon substrate 101 may be oxidized and cleaned to make the sharp corner of the silicon substrate 101 at the top of the local SOI region groove 102 become rounded to improve the device's pressure resistance and breakdown resistance.

[0043] like Figure 1 and Figures 4 to 6 As shown, step 2) S12 is then performed to deposit a dielectric layer 103 on the local SOI region groove 102 and the surface of the silicon substrate 101, and a chemical mechanical polishing process is performed to form a flat surface, the flat surface stays on the surface of the dielectric layer 103, and a seed groove 201 is etched in the dielectric layer 103, and the seed groove 201 exposes the surface of the silicon substrate 101.

[0044] For example, a chemical vapor deposition process can be used to deposit a dielectric layer 103 on the surface of the local SOI region groove 102 and the silicon substrate 101. The thickness of the dielectric layer 103 is greater than the depth of the local SOI region groove 102. The material of the dielectric layer 103 includes one of silicon dioxide, silicon oxynitride and silicon nitride. In this embodiment, the thickness of the dielectric layer 103 is 2.3 microns to 2.8 microns, which is slightly greater than the depth of the local SOI region groove 102, to ensure that the dielectric layer 103 can fill the local SOI region groove 102, which is beneficial to the subsequent polishing process and shortens the time required for the polishing process. After the chemical mechanical polishing, the thickness of the remaining dielectric layer 103 located on the surface of the silicon substrate 101 is between 0.1 microns and 0.3 microns. Then, a photolithography process and an etching process are used to etch a seed groove 201 in the dielectric layer, and the seed groove 201 exposes the surface of the silicon substrate 101. Figure 6 As shown, the number and size of the seed slots 221 can be determined according to actual needs.

[0045] like Figure 4-5 As shown, since the deposition of the dielectric layer 103 has a groove filling function, the thickness of the dielectric layer 103 located on the silicon substrate 101 will be greater than the thickness of the dielectric layer 103 located above the local SOI region groove 102. In this embodiment, the dielectric layer 103 with a larger thickness above the silicon substrate 101 can be removed by a first-step photolithography and etching process to reduce the surface height difference of the dielectric layer 103, and then a chemical mechanical polishing process is used to form a flat surface, which can greatly improve the surface flatness and improve efficiency.

[0046] like Figure 1 and Figure 7-Figure 8 As shown, then step 3) S13 is performed to deposit an amorphous silicon layer 104 on the surface of the seed groove 201 and the dielectric layer 103, a chemical mechanical polishing process is used to form a flat surface, and the amorphous silicon layer 104 is recrystallized by a thermal annealing solid phase epitaxial process to form a single crystal silicon layer 105 covering the surface of the silicon substrate 101 and the dielectric layer 103, so as to form the single crystal silicon local SOI substrate, as shown in FIG. Figure 8 shown.

[0047] For example, a magnetron sputtering method or a chemical vapor deposition method can be used to deposit the amorphous silicon layer 104 on the surface of the seed groove 201 and the dielectric layer 103, and the thickness of the amorphous silicon layer 104 is between 50 nanometers and 5000 nanometers. In this embodiment, the amorphous silicon layer 104 is deposited on the surface of the seed groove 201 and the dielectric layer 103 by magnetron sputtering method, and the thickness of the amorphous silicon layer 104 is 220 nanometers.

[0048] The annealing temperature of the thermal annealing solid phase epitaxy process is between 500 and 1200° C., and the annealing time is between 0.5 minutes and 120 minutes. During the annealing process, the amorphous silicon layer 104 on the silicon substrate 101 contacts the silicon substrate 101 in the seed groove 201, and vertical solid phase epitaxy occurs to form single crystal silicon. Then, based on the single crystal silicon, horizontal solid phase epitaxy occurs toward the amorphous silicon above the dielectric layer 103, thereby forming a single crystal silicon layer 105 on the dielectric layer 103. In this embodiment, the annealing temperature of the solid phase epitaxy is 700° C., and the annealing time is 5 minutes.

[0049] like Figure 1 and Fig. 9 As shown, step 4) S14 is finally performed to prepare electrical devices 106 on the silicon substrate 101 and the single crystal silicon layer 105 thereon, and optical devices 107 are prepared on the single crystal silicon layer 105 on the dielectric layer 103 .

[0050] For example, the electrical device 106 may be a semiconductor transistor, a diode, a resistor and a capacitor, such as an N-type metal semiconductor field effect transistor, a P-type metal semiconductor field effect transistor, a CMOS device, etc., and the optical device 107 may be an optical waveguide, an active device and a passive device, etc.

[0051] like Figure 8 As shown, this embodiment also provides a single crystal silicon local SOI substrate, including: a silicon substrate 101, on which a local SOI regional groove 102 is provided; a dielectric layer 103, which is filled in the local SOI regional groove 102; and a single crystal silicon layer 105, which covers the surface of the silicon substrate 101 and the dielectric layer 103. For example, the depth of the local SOI regional groove 102 is between 1 micron and 10 microns. The material of the dielectric layer 103 includes one of silicon dioxide, silicon oxynitride and silicon nitride. The thickness of the amorphous silicon layer 104 is between 50 nanometers and 5000 nanometers.

[0052] like Fig. 9 As shown, this embodiment also provides an optoelectronic device based on a single crystal silicon local SOI substrate, the optoelectronic device comprising: the single crystal silicon local SOI substrate as described above; an electrical device 106, prepared on the silicon substrate 101 and the single crystal silicon layer 105 thereon; and an optical device 107, prepared on the single crystal silicon layer 105 on the dielectric layer 103.

[0053] For example, the electrical device 106 may be a semiconductor transistor, a diode, a resistor and a capacitor, such as an N-type metal semiconductor field effect transistor, a P-type metal semiconductor field effect transistor, a CMOS device, etc., and the optical device 107 may be an optical waveguide, an active device and a passive device, etc.

[0054] Compared with the scheme of integrating optoelectronic devices on SOI substrate, the present invention can realize the integration of optoelectronic devices on bulk silicon and local SOI, that is, electrical devices 106 can be integrated on bulk silicon, and optical devices 107 can be integrated on local SOI, which has better electrical performance and lower cost. Compared with the existing polycrystalline silicon local SOI scheme on bulk silicon, the present invention can realize single crystal silicon local SOI, which can effectively improve the performance of optical device 107.

[0055] In addition, part of the dielectric layer on the bulk silicon substrate 101 is retained, that is, a thinner dielectric layer 103 is also inserted into the bulk silicon substrate 101, and a seed groove 201 is formed to facilitate solid phase epitaxy. Retaining a thinner dielectric layer can enable the electrical device to obtain a certain degree of SOI effect, such as reducing the latch-up effect of CMOS, etc. At the same time, the single crystal silicon layer 105 in the seed groove 201 is in contact with the bulk silicon, which can suppress the floating body effect of SOI to a certain extent, thereby greatly improving the overall performance of the electrical device.

[0056] As described above, the crystalline silicon localized SOI substrate, optoelectronic device and preparation method of the present invention have the following beneficial effects:

[0057] First, compared with the solution of integrating optoelectronic devices on SOI substrate, the present invention can realize the integration of optoelectronic devices on bulk silicon and local SOI, that is, electrical devices can be integrated on bulk silicon and optical devices can be integrated on local SOI, with better electrical performance and lower cost.

[0058] Second, compared with the existing polycrystalline silicon local SOI solution on bulk silicon, the present invention can realize single crystal silicon local SOI, which can effectively improve the performance of optical devices.

[0059] Third, part of the dielectric layer on the bulk silicon substrate is retained, that is, a thinner dielectric layer is also inserted into the bulk silicon substrate, and a seed groove is formed to facilitate solid phase epitaxy. Retaining a thinner dielectric layer can enable the electrical device to obtain a certain degree of SOI effect, such as reducing the latch-up effect of CMOS. At the same time, the single crystal silicon layer in the seed groove is in contact with the bulk silicon, which can suppress the floating body effect of SOI to a certain extent, thereby greatly improving the overall performance of the electrical device.

[0060] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0061] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a single crystal silicon local SOI substrate, characterized in that: The preparation method comprises the steps of: 1) providing a silicon substrate, etching a local SOI region groove on the silicon substrate, performing oxidation and cleaning steps on the silicon substrate, so that the sharp corner of the silicon substrate at the top of the local SOI region groove becomes a rounded corner, and the depth of the local SOI region groove is between 1 micron and 10 microns; 2) depositing a dielectric layer in the local SOI region groove and on the surface of the silicon substrate, removing the dielectric layer with a larger thickness on the silicon substrate by a first photolithography and etching process to reduce the height difference on the surface of the dielectric layer, and then performing a chemical mechanical polishing process to form a flat surface, wherein the flat surface stays on the surface of the dielectric layer, and after chemical mechanical polishing, the thickness of the remaining dielectric layer on the surface of the silicon substrate is between 0.1 microns and 0.3 microns, and a seed groove is etched in the dielectric layer, and the seed groove exposes the surface of the silicon substrate; 3) depositing an amorphous silicon layer on the surface of the seed groove and the dielectric layer, using a chemical mechanical polishing process to form a flat surface, and recrystallizing the amorphous silicon layer through a thermal annealing solid phase epitaxial process to form a single crystal silicon layer covering the surface of the silicon substrate and the dielectric layer, so as to form the single crystal silicon local SOI substrate.

2. The method for preparing a single crystal silicon localized SOI substrate according to claim 1, characterized in that: Step 2) depositing a dielectric layer on the local SOI region groove and the surface of the silicon substrate using a chemical vapor deposition process, wherein the thickness of the dielectric layer is greater than the depth of the local SOI region groove, and the material of the dielectric layer includes one of silicon dioxide, silicon oxynitride and silicon nitride.

3. The method for preparing a single crystal silicon localized SOI substrate according to claim 1, characterized in that: Step 3) depositing an amorphous silicon layer on the seed groove and the surface of the dielectric layer by a magnetron sputtering method or a chemical vapor deposition method, wherein the thickness of the amorphous silicon layer is between 50 nanometers and 5000 nanometers.

4. The method for preparing a single crystal silicon localized SOI substrate according to claim 1, characterized in that: Step 3) The annealing temperature of the thermal annealing solid phase epitaxy process is between 500 and 1200° C., and the annealing time is between 0.5 minutes and 120 minutes.

5. A method for preparing an optoelectronic device based on a single crystal silicon localized SOI substrate, characterized in that: The preparation method comprises the steps of: 1) preparing a single crystal silicon local area SOI substrate by using the method for preparing a single crystal silicon local area SOI substrate according to any one of claims 1 to 4; 2) preparing electrical devices on the silicon substrate and the single crystal silicon layer thereon, and preparing optical devices on the single crystal silicon layer on the dielectric layer.

6. The method for preparing an optoelectronic device based on a single crystal silicon localized SOI substrate according to claim 5, characterized in that: The electrical device includes one or more of a semiconductor transistor, a diode, a resistor and a capacitor, and the optical device includes one or more of an optical waveguide, an active device and a passive device.

7. A single crystal silicon local SOI substrate, characterized in that: include: A silicon substrate having a local SOI region groove, wherein the top sharp corner of the silicon substrate at the top of the local SOI region groove is changed into a rounded corner, and the depth of the local SOI region groove is between 1 micron and 10 microns; A dielectric layer is filled in the local SOI region groove and covers the surface of the silicon substrate, the thickness of the remaining dielectric layer on the surface of the silicon substrate is between 0.1 micrometer and 0.3 micrometer, and the dielectric layer has a seed groove, and the seed groove exposes the silicon substrate; A single crystal silicon layer fills the seed groove and covers the surface of the dielectric layer, and the single crystal silicon layer is in contact with the silicon substrate at the bottom of the seed groove.

8. The single crystal silicon local SOI substrate according to claim 7, characterized in that: The material of the dielectric layer includes one of silicon dioxide, silicon oxynitride and silicon nitride.

9. An optoelectronic device based on a single crystal silicon localized SOI substrate, characterized in that: include: The single crystal silicon local SOI substrate according to any one of claims 7 to 8; An electrical device is prepared on the silicon substrate and the single crystal silicon layer thereon; The optical device is prepared on the single crystal silicon layer on the dielectric layer.

10. The optoelectronic device based on a single crystal silicon localized SOI substrate according to claim 9, characterized in that: The electrical device includes one or more of a semiconductor transistor, a diode, a resistor and a capacitor, and the optical device includes one or more of an optical waveguide, an active device and a passive device.

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