Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, comprising: providing a substrate, the substrate having a plurality of initial fins separated from each other, and grooves between adjacent initial fins; performing an isolation ion implantation process, wherein the direction of the isolation ion implantation is perpendicular to the bottom surface of the groove, forming a first implantation region on the sidewall surface of the initial fin, and forming a second implantation region on the bottom surface of the groove; performing a first annealing process, so that the first implantation region forms a first isolation layer, the initial fin forms a fin, the fin includes a second region and a first region located on the second region; and forming a second isolation layer in the second implantation region. By performing isolation ion implantation on the initial fin, a first implantation region and a second implantation region are formed on the sidewall of the initial fin and the bottom of the groove, and subsequently performing a first annealing process, the bottom size of the first region of the fin is reduced, and the depth of the groove is deepened, thereby improving the electrical performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development of semiconductor technology, the control capability of the traditional planar MOS transistor on the channel current has become weaker, resulting in serious leakage current. Fin Field Effect Transistor (FinFET) is an emerging multi-gate device.

[0003] The FinFET includes: a fin located on a substrate; a gate across the fin; a source and a drain located in the fin on both sides of the gate, with the source and the gate, and the drain and the gate separated from each other. Compared with CMOS transistors, the FinFET is a similar three-dimensional structure located on a substrate, with a smaller feature size and better able to meet the requirements of high integration. Moreover, the gate of the FinFET is opposite to the upper surface of the fin, and the gate is also opposite to the two opposite sidewall surfaces of the fin. When working, the upper surface of the fin in contact with the gate and the two opposite sidewall surfaces can form a channel region, which improves the mobility of carriers.

[0004] However, the performance of the fin field effect transistor formed by the prior art needs to be improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate having a plurality of mutually discrete initial fins, and grooves between adjacent initial fins; performing isolation ion implantation, the direction of the isolation ion implantation being perpendicular to the bottom surface of the groove, forming a first implantation region on the sidewall surface of the initial fin, and forming a second implantation region on the bottom surface of the groove; performing a first annealing treatment, so that the first implantation region forms a first isolation layer, the initial fin forms a fin, the fin includes a second region and a first region located on the second region; and forming a second isolation layer in the second implantation region.

[0007] Optionally, the material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0008] Optionally, an angle between the sidewall surface of the first region and the bottom surface of the fin is 89.5° to 90°.

[0009] Optionally, the distance between adjacent fins is 22 nm to 26 nm; the width of the fin is 8 to 10 nm; and the height of the fin is 1100 angstroms to 1300 angstroms.

[0010] Optionally, the initial fin and the substrate are formed using a multiple patterning process.

[0011] Optionally, the method of forming the initial fin and the substrate using a multiple patterning process includes: providing an initial substrate, forming a mask layer on the top surface of the initial substrate; forming a sacrificial layer on the mask layer; etching the sacrificial layer until the mask layer is exposed to form a plurality of discrete patterned structures; forming a first sidewall material layer on the surface of the patterned structure and the top surface of the mask layer; removing the first sidewall material layer and the patterned structure in a horizontal direction to form a first sidewall layer; forming a second sidewall material layer on the surface of the first sidewall layer and the top surface of the mask layer; removing the second sidewall material layer and the first sidewall layer in a horizontal direction to form a second sidewall layer; etching the mask layer and the initial substrate using the second sidewall layer as a mask to form the initial fin and the substrate.

[0012] Optionally, the first spacer material layer and the second spacer material layer are formed by an atomic deposition process.

[0013] Optionally, the isolation ion implantation process is performed at a temperature of -100°C to 0°C.

[0014] Optionally, the spacer ions include oxygen ions.

[0015] Optionally, the parameters of the isolation ion implantation process include: implantation energy of 0KeV to 20KeV, implantation dose of 1E16atoms / cm 2 ~1E17atoms / cm 2 .

[0016] Optionally, after the isolation ion implantation process, the method further includes: forming an initial isolation layer in the trench.

[0017] Optionally, the first annealing treatment is performed before forming the initial isolation layer.

[0018] Optionally, the initial isolation layer is formed by a fluid chemical vapor deposition process; the fluid chemical vapor deposition process comprises: forming a precursor layer in the groove by a spin coating process; and performing a second annealing process to solidify the precursor layer to form the initial isolation layer.

[0019] Optionally, the initial isolation layer is formed by a fluid chemical vapor deposition process; the fluid chemical vapor deposition process includes: forming a precursor layer in the groove using a spin coating process; performing the first annealing treatment to solidify the precursor layer to form the initial isolation layer, and forming the first isolation layer in the first injection area, and forming the second isolation layer in the second injection area.

[0020] Optionally, before forming the initial isolation layer, the method further includes: forming an interface layer on the surface of the groove.

[0021] Optionally, the process for forming the interface layer adopts an in-situ water vapor process.

[0022] Optionally, the material of the interface layer includes silicon oxide.

[0023] Optionally, after forming the initial isolation layer, the method further includes: planarizing the initial isolation layer until the top surface of the fin is exposed; and removing a portion of the initial isolation layer in the groove until the first region is completely exposed to form an isolation layer.

[0024] Correspondingly, the present invention also provides a semiconductor structure formed by any of the above methods, comprising: a substrate having a plurality of mutually discrete fins on the substrate, the fins comprising a first region and a second region located on the first region, and grooves between adjacent fins; a first isolation layer located on the side walls of the fins; and a second isolation layer located on the bottom surface of the groove.

[0025] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0026] In the technical solution of the present invention, the initial fin is subjected to isolation ion implantation treatment, and the direction of the isolation ion implantation is perpendicular to the bottom surface of the groove, so that the isolation ions are implanted into the outwardly inclined portion of the initial fin side wall to form a first implantation region, and then a first annealing treatment is performed to react the isolation ions with the initial fin side wall to generate a first isolation layer, and the initial fin forms a fin, thereby reducing the bottom size of the first region of the fin, increasing the spacing between adjacent first regions, reducing the occurrence of leakage problems, and thereby improving the electrical performance of the semiconductor structure finally formed.

[0027] In addition, after the isolation ion implantation treatment, part of the isolation ions will also be implanted into the bottom of the groove to form a second implantation area. After the first annealing treatment, this part of the isolation ions will react with the substrate to generate a second isolation layer. The second isolation layer will deepen the isolation depth, reduce the parasitic capacitance between the subsequently formed device structure and the substrate, and improve the electrical performance of the semiconductor structure finally formed.

[0028] Furthermore, in the technical solution of the present invention, the initial fin is formed by a multiple patterning process, which can greatly improve the density of the semiconductor integrated circuit without changing the current photolithography technology.

[0029] Furthermore, in the technical solution of the present invention, the temperature of the isolation ion implantation treatment is -100°C to 0°C. Within this temperature range, the mobility of the isolation ions is reduced, thereby reducing the damage caused by the isolation ions to the side wall surface of the initial fin. In addition, the isolation ions that diffuse at a low speed are easier to control, and the range of the isolation ions diffusing to the side wall of the second zone of the initial fin can be controlled more accurately. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figures 1 to 5 It is a schematic diagram of the structure of a semiconductor structure;

[0031] Figures 6 to 11 It is a schematic diagram of the structure of each step of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0032] Figures 12 to 18 A schematic structural diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention. DETAILED DESCRIPTION

[0033] As described in the background art, the performance of the fin field effect transistor formed in the prior art needs to be improved. Figures 1 to 5 To explain, Figures 1 to 5 It is a structural schematic diagram of the formation process of a semiconductor structure.

[0034] Please refer to Figure 1 A substrate 100 is provided, on which a plurality of mutually discrete fins 101 are provided. The fins include a second region B and a first region A located on the second region B. A groove 102 is provided between adjacent fins 101 .

[0035] Please refer to Figure 2 An interface layer 103 is formed on the surface of the fin 101 and the bottom surface of the trench 102 .

[0036] Please refer to Figure 3 A precursor layer 104 is formed on the surface of the interface layer 103 , and the precursor layer 104 covers the fin 101 .

[0037] Please refer to Figure 4 , performing annealing treatment so that the precursor layer 104 reacts with the interface layer 103 to form an initial isolation layer 105.

[0038] Please refer to Figure 5, planarizing the initial isolation layer 105 until the top surface of the fin 101 is exposed; removing a portion of the initial isolation layer 105 and the interface layer 103 in the groove 102 until the first area A is completely exposed, to form an isolation layer 106.

[0039] In the above embodiment, the process of forming the fin 101 will affect the verticality of the side wall of the fin 101 due to problems in the manufacturing process. Specifically, the side wall of the first area A and the side wall of the second area B are outwardly expanded and inclined, resulting in a larger bottom size of the first area A, and then the distance between adjacent first areas A will become smaller, which is prone to leakage problems and affects the performance of the formed semiconductor structure.

[0040] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the initial fin is subjected to vertical isolation ion implantation treatment so that the isolation ions diffuse to the outwardly expanded inclined portion of the side wall of the initial fin, and then a first annealing treatment is performed so that the isolation ions react with the outwardly expanded inclined portion of the side wall of the fin to generate a first isolation layer. The initial fin forms a fin, and the bottom size of the first region of the fin is reduced after formation, thereby improving the electrical performance of the semiconductor structure finally formed.

[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figures 6 to 11 , is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0043] Please refer to Figure 6 A substrate 200 is provided, on which a plurality of initial fins 201 separated from each other are provided, and grooves 202 are provided between adjacent initial fins 201 .

[0044] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0045] In this embodiment, the material of the initial fin 201 is silicon; in other embodiments, the material of the initial fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0046] In this embodiment, the method of forming the initial fin 201 and the substrate 200 using a multiple patterning process includes: providing an initial substrate (not shown), forming a mask layer (not shown) on the top surface of the initial substrate; forming a sacrificial layer (not shown) on the mask layer; etching the sacrificial layer until the mask layer is exposed to form a plurality of discrete patterned structures; forming a first sidewall material layer (not shown) on the surface of the patterned structure and the top surface of the mask layer; removing the first sidewall material layer and the patterned structure in a horizontal direction to form a first sidewall layer; forming a second sidewall material layer (not shown) on the surface of the first sidewall layer and the top surface of the mask layer; removing the second sidewall material layer and the first sidewall layer in a horizontal direction to form a second sidewall layer; etching the mask layer and the initial substrate using the second sidewall layer as a mask to form the initial fin 201 and the substrate 200.

[0047] In this embodiment, the first spacer material layer and the second spacer material layer are formed by an atomic layer deposition process. The first spacer material layer and the second spacer material layer formed by the atomic layer deposition process have good uniformity, step coverage and thickness control capability, which effectively improves the accuracy of the initial fin pattern after etching.

[0048] In this embodiment, the initial fin 201 is formed by the multiple patterning process, which can greatly improve the density of the semiconductor integrated circuit without changing the current photolithography technology.

[0049] Due to the limitation of the manufacturing process, the verticality of the sidewalls of the initial fin 201 formed after etching needs to be improved, which is specifically manifested in that the sidewalls of the initial fin 201 are outwardly expanded and inclined.

[0050] Please refer to Figure 7 , an isolation ion implantation process is performed, wherein the direction of the isolation ion implantation is perpendicular to the bottom surface of the trench 202 , a first implantation region 203 is formed on the sidewall surface of the initial fin 201 , and a second implantation region 204 is formed on the bottom surface of the trench 202 .

[0051] In this embodiment, the isolation ions are oxygen ions.

[0052] In this embodiment, the purpose of injecting the isolation ions in a direction perpendicular to the bottom surface of the groove 202 is to ensure that the isolation ions can enter the outwardly inclined part of the side wall of the initial fin 201 by vertically injecting the isolation ions, and will not be injected into the vertical part of the side wall of the initial fin 201, thereby ensuring the verticality of the side wall of the fin formed after the first annealing treatment.

[0053] In this embodiment, the isolation ion implantation process is performed at a temperature of -100°C to 0°C.

[0054] In this temperature range, the mobility of the isolation ions is reduced, thereby reducing the damage caused by the isolation ions to the sidewall surface of the initial fin 201 .

[0055] In addition, to improve the verticality of the sidewall of the initial fin 201, it is only necessary to form the first implantation region 203 in the outwardly expanded inclined portion of the initial fin 201. If the isolation ions diffuse deeper into the sidewall of the initial fin 201, the width of the final fin will be narrowed, thereby affecting the electrical performance of the formed semiconductor structure. Therefore, in a low temperature environment, the diffusion speed of the isolation ions is low, which makes it easier to control and can more accurately control the range of the isolation ions diffused to the sidewall of the initial fin 201.

[0056] In this embodiment, the parameters of the isolation ion implantation process include: implantation energy of 0KeV to 20KeV, implantation dose of 1E16atoms / cm 2 ~1E17atoms / cm 2 .

[0057] In this embodiment, the range of diffusion of the isolation ions to the side walls of the initial fin 201 can be comprehensively controlled by injection energy, injection dose and injection time to ensure that the isolation ions are more accurately diffused to the outward expansion part of the side walls of the initial fin 201, thereby improving the verticality of the side walls of the finally formed fins.

[0058] In the present embodiment, after the initial fin 201 is formed by adopting the multiple patterning process, the second sidewall layer (not marked) and the mask layer (not marked) serving as a mask will remain on the top surface of the initial fin 201. Therefore, when the isolation ion implantation process is performed, the isolation ions will not be implanted into the top surface of the initial fin 201 due to the blocking of the second sidewall layer and the mask layer. Therefore, after the subsequent first annealing process, the height of the initial fin 201 will not be affected.

[0059] In this embodiment, after the isolation ion implantation process, a first annealing process is performed to form the first implantation region 203 into a first isolation layer, the initial fin 201 into a fin, the fin including a second region and a first region located on the second region; and the second implantation region 204 into a second isolation layer. For the specific formation process, please refer to Figures 8 to 11 .

[0060] Please refer to Figure 8 After the isolation ion implantation process, an interface layer 205 is formed on the surface of the trench 202 .

[0061] In this embodiment, since the second spacer layer and the mask layer remain on the top surface of the initial fin 201 , the interface layer 205 is specifically formed on the exposed surfaces of the second spacer layer, the mask layer, the initial fin 201 and the trench 202 .

[0062] In this embodiment, the process of forming the interface layer 205 adopts an in-situ water vapor process. The interface layer 205 formed by the in-situ water vapor process can effectively reduce stress and reduce defects such as stacking faults. In addition, the interface layer 205 formed by this process has good graphic retention. The interface layer 205 formed at the top and bottom corners of the initial fin 201 is smooth and has a good isolation effect.

[0063] In this embodiment, the material of the interface layer 205 is silicon oxide.

[0064] In this embodiment, the thickness of the interface layer 205 is 30 angstroms to 40 angstroms.

[0065] In this embodiment, an initial isolation layer is subsequently formed in the groove 202, and the initial isolation layer is formed by a fluid chemical vapor deposition process. For the process of forming the initial isolation layer by a fluid chemical vapor deposition process, please refer to Figures 9 and 10 .

[0066] Please refer to Fig. 9 , a precursor layer 207 is formed in the groove by a spin coating process.

[0067] In this embodiment, the precursor layer 207 is specifically formed on the surface of the interface layer 205 until the groove 202 is completely filled.

[0068] Please refer to Fig.10 , perform the first annealing treatment to solidify the precursor layer 207 to form the initial isolation layer 206; form the first isolation layer 208 in the first injection region 203, and form the fin 201 into a fin 211, wherein the fin 211 includes a second region B and a first region A located on the second region B; and form the second isolation layer 209 in the second injection region 204.

[0069] In this embodiment, the parameters of the first annealing treatment include: an annealing temperature of 620° C. to 650° C., and an annealing time of 40 min to 50 min.

[0070] In this embodiment, the precursor layer 207 can be solidified through the first annealing treatment to form the initial isolation layer 206, thereby improving the isolation quality; at the same time, the first injection area 203 and the second injection area 204 can also be formed into the first isolation layer 208 and the second isolation layer 209 under the first annealing treatment, thereby simplifying the process steps in the manufacturing process and improving production efficiency.

[0071] The first isolation layer 208 formed by the first injection area 203 can transform the outward expansion part of the side wall of the initial fin 201 into an isolation structure, so that the initial fin 201 forms a fin 211, effectively improving the verticality of the side wall of the initial fin 201, thereby reducing the bottom size of the first area A, increasing the distance between adjacent first areas A, reducing the occurrence of leakage problems, and improving the electrical performance of the semiconductor structure finally formed.

[0072] The second injection region 204 is formed on the bottom surface of the groove 202, and the second isolation layer 209 is formed after the first annealing treatment. The second isolation layer 209 deepens the isolation depth, reduces the parasitic capacitance between the subsequently formed device structure and the substrate 200, and improves the electrical performance of the semiconductor structure finally formed.

[0073] Please refer to Fig.11 After forming the initial isolation layer 206 , the initial isolation layer 206 is planarized until the top surface of the fin 211 is exposed; a portion of the initial isolation layer 206 in the groove 202 is removed until the first area A is completely exposed, thereby forming an isolation layer 210 .

[0074] The process used to planarize the initial isolation layer 206 includes a chemical mechanical polishing process and an etching process. In the present embodiment, the process used to planarize the initial isolation layer 206 is a chemical mechanical polishing process.

[0075] In this embodiment, when removing part of the initial isolation layer 206 in the groove 202, part of the interface layer 205 and part of the first isolation layer 208 located on the side wall of the first region A are also removed. The removal process used is a wet etching process. In other embodiments, the process used to remove part of the initial isolation layer in the groove may also be a dry etching process.

[0076] In this embodiment, the angle between the side wall surface of the first region A of the fin 211 and the bottom surface of the fin 211 is 89.5° to 90°.

[0077] The distance between adjacent fins 211 is 22 nm to 26 nm; the width of the fin 211 is 8 nm to 10 nm; and the height of the fin 211 is 1100 angstroms to 1300 angstroms.

[0078] Accordingly, the present invention also provides a semiconductor structure formed by the above method, please continue to refer to Fig.10 , including: a substrate 200, the substrate 200 having a plurality of mutually discrete fins 211, the fins 211 including a second region B and a first region located on the second region B, and grooves between adjacent fins 211; a first isolation layer 208 located on the sidewalls of the fins 211; and a second isolation layer 209 located on the bottom surface of the groove.

[0079] Figures 12 to 18 A schematic structural diagram of each step of a method for forming a semiconductor structure in another embodiment of the present invention.

[0080] Please refer to Fig.12 A substrate 300 is provided, on which a plurality of initial fins 301 separated from each other are provided, and grooves 302 are provided between adjacent fins 301 .

[0081] Please refer to Fig.13 , an isolation ion implantation process is performed, wherein the direction of the isolation ion implantation is perpendicular to the bottom surface of the trench 302 , a first implantation region 303 is formed on the sidewall surface of the fin 301 , and a second implantation region 304 is formed on the bottom surface of the trench 302 .

[0082] The substrate 300 , the initial fin 301 , the trench 302 , and the isolation ion implantation process are as described in the embodiment Figure 6 and Figure 7 And related instructions have been described, which will not be repeated here.

[0083] Please refer to Fig.14 , a first annealing treatment is performed to form a first isolation layer 308 in the first injection region 303, and the initial fin 301 forms a fin 311, wherein the fin 311 includes a second region B and a first region A located on the second region B; and the second injection region 304 forms a second isolation layer 309.

[0084] The first isolation layer 308 formed by the first injection region 303 can transform the outward expansion portion of the side wall of the initial fin 301 into an isolation structure, forming the fin 311, effectively improving the verticality of the side wall of the initial fin 301, reducing the bottom size of the first region A, and increasing the spacing between adjacent first regions A, thereby reducing the occurrence of leakage problems and improving the electrical performance of the semiconductor structure finally formed.

[0085] In this embodiment, the parameters of the first annealing treatment include: an annealing temperature of 1000° C. to 1100° C., and an annealing time of 25 min to 35 min.

[0086] Please refer to Fig.15 After the first isolation layer 308 and the second isolation layer 309 are formed, an interface layer 305 is formed on the surface of the groove 302 .

[0087] The interface layer 305 is formed as in Example Figure 8 And related instructions have been described, which will not be repeated here.

[0088] In this embodiment, an initial isolation layer is subsequently formed in the groove 302, and the process of forming the initial isolation layer is a fluid chemical vapor deposition process. For the process of forming the initial isolation layer using the fluid chemical vapor deposition process, please refer to Fig.16 Fig.18 .

[0089] Please refer to Fig.16 , a precursor layer 307 is formed in the groove 302 by a spin coating process.

[0090] In this embodiment, the precursor layer 307 is specifically formed on the surface of the interface layer 305 until the groove 302 is completely filled.

[0091] Please refer to Fig.17 , a second annealing treatment is performed to solidify the precursor layer 307 to form the initial isolation layer 306 .

[0092] In this embodiment, the parameters of the second annealing treatment include: an annealing temperature of 620° C. to 650° C., and an annealing time of 40 min to 50 min.

[0093] Please refer to Fig.18 After forming the initial isolation layer 306 , the initial isolation layer 306 is planarized until the top surface of the fin 311 is exposed; a portion of the initial isolation layer 306 in the groove 302 is removed until the first area A is completely exposed, thereby forming an isolation layer 310 .

[0094] The isolation layer 305 is formed as in the embodiment Fig.11 And related instructions have been described, which will not be repeated here.

[0095] Accordingly, in this embodiment, a method is also provided. Fig.17 The semiconductor structure shown.

[0096] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a plurality of initial fins separated from each other, grooves are provided between adjacent initial fins, and sidewalls of the initial fins are outwardly expanded and inclined; Performing an isolation ion implantation process, wherein the direction of the isolation ion implantation is perpendicular to the bottom surface of the trench, forming a first implantation region on the sidewall surface of the initial fin, and forming a second implantation region on the bottom surface of the trench; A first annealing treatment is performed to form a first isolation layer in the first implanted region, and the initial fin portion is formed into a fin portion, wherein the fin portion includes a second region and a first region located on the second region; and the second implanted region is formed into a second isolation layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The material of the substrate includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

3. The method for forming a semiconductor structure according to claim 1, wherein: An angle between a sidewall surface of the first region and a bottom surface of the fin portion is 89.5° to 90°.

4. The method for forming a semiconductor structure according to claim 1, wherein: The distance between adjacent fins is 22nm-26nm; the width of the fin is 8-10nm; and the height of the fin is 1100 angstroms-1300 angstroms.

5. The method for forming a semiconductor structure according to claim 1, wherein: The initial fin and the substrate are formed by a multiple patterning process.

6. The method for forming a semiconductor structure according to claim 5, wherein: The method of forming the initial fin and the substrate using a multiple patterning process includes: providing an initial substrate, forming a mask layer on the top surface of the initial substrate; forming a sacrificial layer on the mask layer; etching the sacrificial layer until the mask layer is exposed to form a plurality of discrete patterned structures; forming a first sidewall material layer on the surface of the patterned structure and the top surface of the mask layer; removing the first sidewall material layer and the patterned structure in a horizontal direction to form a first sidewall layer; forming a second sidewall material layer on the surface of the first sidewall layer and the top surface of the mask layer; removing the second sidewall material layer and the first sidewall layer in a horizontal direction to form a second sidewall layer; etching the mask layer and the initial substrate using the second sidewall layer as a mask to form the initial fin and the substrate.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first spacer material layer and the second spacer material layer are formed by an atomic deposition process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The isolation ion implantation process is performed at a temperature of -100°C to 0°C.

9. The method for forming a semiconductor structure according to claim 1, wherein: The spacer ions include oxygen ions.

10. The method for forming a semiconductor structure according to claim 1, wherein: The parameters of the isolation ion implantation process include: implantation energy of 0KeV to 20KeV, implantation dose of 1E16atoms / cm 2 ~1E17atoms / cm 2 .

11. The method for forming a semiconductor structure according to claim 1, wherein: After the isolation ion implantation process, the method further includes: forming an initial isolation layer in the trench.

12. The method for forming a semiconductor structure according to claim 11, wherein: The first annealing process is performed before forming the initial isolation layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The initial isolation layer is formed by a fluid chemical vapor deposition process; the method of the fluid chemical vapor deposition process includes: forming a precursor layer in the groove by a spin coating process; and performing a second annealing process to solidify the precursor layer to form the initial isolation layer.

14. The method for forming a semiconductor structure according to claim 11, wherein: The formation process of the initial isolation layer is a fluid chemical vapor deposition process; the method of the fluid chemical vapor deposition process includes: using a spin coating process to form a precursor layer in the groove; performing the first annealing treatment to solidify the precursor layer to form the initial isolation layer, and to form the first isolation layer in the first injection area, and the second isolation layer in the second injection area.

15. The method for forming a semiconductor structure according to claim 11, wherein: Before forming the initial isolation layer, the method further includes: forming an interface layer on the surface of the groove.

16. The method for forming a semiconductor structure according to claim 15, wherein: The process for forming the interface layer adopts an in-situ water vapor process.

17. The method for forming a semiconductor structure according to claim 15, wherein: The material of the interface layer includes silicon oxide.

18. The method for forming a semiconductor structure according to claim 11, wherein: After forming the initial isolation layer, the method further includes: planarizing the initial isolation layer until the top surface of the fin is exposed; and removing a portion of the initial isolation layer in the groove until the first region is completely exposed to form an isolation layer.

19. A semiconductor structure formed by the method according to any one of claims 1 to 18, characterized in that: include: A substrate having a plurality of mutually separated fins on the substrate, wherein the fins include a first region and a second region located on the first region, and grooves are provided between adjacent fins; a first isolation layer located on a sidewall of the fin; A second isolation layer is located on the bottom surface of the trench.

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