Semiconductor structure and method for forming the same

Abstract

The invention relates to a semiconductor structure and a method for forming the same, which can obtain a gate with a better profile and improve the yield of the memory finally produced. The method for forming the semiconductor structure includes the following steps: providing a substrate, the upper surface of which is sequentially stacked with a gate oxide layer, a polysilicon layer and a first mask layer; patterning the first mask layer to form a groove penetrating the first mask layer, and the groove exposes the polysilicon layer; forming a metal layer filled in the groove, and the upper surface of the metal layer is flush with the upper surface of the first mask layer; forming an insulating cap on the upper surface of the metal layer, and the projection of the insulating cap on the upper surface of the substrate coincides with the projection of the groove on the upper surface of the substrate; removing the patterned first mask layer, and sequentially removing the exposed polysilicon layer and the gate oxide layer; partially removing the exposed substrate, so that the exposed upper surface of the substrate forms a height difference with the lower surface of the gate oxide layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor structures, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] As the characteristic size of semiconductor integrated circuit devices continues to shrink, the requirements for the process technology of memories, such as DRAM (dynamic random access memory), are becoming increasingly higher, and the design of MOS transistors in the peripheral circuits of the memory is also very important. In the prior art, the sidewalls of the gate of the MOS tube are easily damaged during the etching process, and the gate profile is prone to necking, which greatly affects the contact resistance and conduction rate of the gate and the subsequent ion implantation process, reduces the performance of the peripheral circuit of the memory formed in the end, and affects the yield of the memory produced in the end. Summary of the invention

[0003] The object of the present invention is to provide a semiconductor structure and a method for forming the same, which can obtain a gate with a better profile and improve the yield of the memory finally produced.

[0004] In order to solve the above technical problems, a method for forming a semiconductor structure is provided below, comprising the following steps: providing a substrate, wherein a gate oxide layer, a polysilicon layer and a first mask layer are sequentially stacked on the upper surface of the substrate; patterning the first mask layer to form a groove penetrating the first mask layer, and the groove exposes the polysilicon layer; forming a metal layer filled in the groove, and the upper surface of the metal layer is flush with the upper surface of the first mask layer; forming an insulating top cover on the upper surface of the metal layer, and the projection of the insulating top cover on the upper surface of the substrate coincides with the projection of the groove on the upper surface of the substrate; removing the patterned first mask layer, and sequentially removing the exposed polysilicon layer and the gate oxide layer; partially removing the exposed substrate so that a height difference is formed between the exposed upper surface of the substrate and the lower surface of the gate oxide layer.

[0005] Optionally, before forming the metal layer filling the groove, the method further includes the following steps: forming a first insulating sidewall on the sidewall surface of the groove.

[0006] Optionally, forming a first insulating sidewall on the sidewall surface of the groove includes the following steps: forming an insulating layer, the insulating layer covering the sidewall surface and the bottom of the groove, and the upper surface of the patterned first mask layer; removing the insulating layer located at the bottom of the groove and the upper surface of the patterned first mask layer.

[0007] Optionally, the forming of the insulating layer includes: forming the insulating layer by atomic layer deposition; the removing of the insulating layer at the bottom of the groove and the upper surface of the patterned first mask layer includes: removing the insulating layer at the bottom of the groove and the upper surface of the patterned first mask layer by directional etching.

[0008] Optionally, the forming of the metal layer filling the groove includes: forming a metal deposition layer, the metal deposition layer filling the groove and covering the patterned first mask layer; and planarizing the metal deposition layer to form the metal layer.

[0009] Optionally, when forming an insulating top cover on the upper surface of the metal layer, the following steps are included: forming an insulating top cover layer on the upper surface of the patterned first mask layer and the metal layer; etching the insulating top cover layer to expose the patterned first mask layer, and retaining the insulating top cover layer above the metal layer to form an insulating top cover.

[0010] Optionally, when removing the patterned first mask layer and removing the exposed polysilicon layer and gate oxide layer in sequence, the following steps are included: removing the patterned first mask layer by directional etching to expose the polysilicon layer; removing the exposed polysilicon layer by directional etching to expose the gate oxide layer; and removing the exposed gate oxide layer by directional etching.

[0011] Optionally, after removing the exposed polysilicon layer by directional etching, the method further includes the following steps: converting the sidewall of the etched polysilicon layer into a second insulating sidewall.

[0012] Optionally, the second insulating sidewall is a silicon nitride sidewall, and when the sidewall of the etched polysilicon layer is converted into the second insulating sidewall, the following steps are included: using nitrogen to react with the sidewall of the etched polysilicon layer to convert the sidewall of the polysilicon layer into a silicon nitride sidewall.

[0013] Optionally, the exposed substrate is partially removed to form a height difference between the exposed upper surface of the substrate and the lower surface of the gate oxide layer, comprising the following steps: bombarding the exposed upper surface of the substrate downwardly in a direction perpendicular to the substrate surface by plasma to make the height of the exposed upper surface of the substrate lower than the height of the lower surface of the gate oxide layer.

[0014] Optionally, the height difference is 3-5 nm.

[0015] In order to solve the above technical problems, a semiconductor structure is also provided below, including: a substrate; a gate oxide layer formed on the upper surface of the substrate; a polysilicon layer formed on the upper surface of the gate oxide layer; a first mask layer formed on the upper surface of the polysilicon layer; a groove formed on the upper surface of the first mask layer; a metal layer formed in the groove and a first insulating sidewall formed on the sidewall surface of the metal layer; and an insulating top cover formed on the upper surface of the metal layer.

[0016] Optionally, the groove exposes an upper surface of the polysilicon layer, and an upper surface of the metal layer is flush with an upper surface of the first mask layer.

[0017] Optionally, the first insulating sidewall includes a silicon nitride sidewall, and the first mask layer includes an amorphous carbon layer.

[0018] The semiconductor structure and the method for forming the same of the present invention form a metal layer of a desired shape by first forming a patterned first mask layer, and then forming an insulating cap on the metal layer. It is not necessary to obtain a metal layer of a specific shape by etching, so the metal layer profile will not be affected by etching. Furthermore, a second insulating sidewall is formed on the sidewall of the polysilicon layer, and it is not necessary to use pickling to remove the oxide formed on the sidewall of the polysilicon layer during the etching process, so the sidewall of the polysilicon layer will not be affected. The semiconductor structure obtained in this way has a better profile, and will not have necking or inverted taper, thereby improving the yield of the memory finally produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figures 1 to 12 It is a schematic diagram of a semiconductor structure corresponding to each step of a method for forming a semiconductor structure in a specific implementation manner of the present invention.

[0020] Fig.13 The figure is a schematic flow chart of the steps of a method for forming a semiconductor structure in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0021] Research has found that in the prior art, when manufacturing the gate of a transistor in a memory structure, the profile of the gate is prone to necking or inverted taper, which will seriously limit the yield of the memory finally produced.

[0022] The reason for these phenomena is that in the process of forming the gate, the gate is transferred through a multi-layer mask, and the pattern is transferred from the mask to the final metal layer and polysilicon layer, and the metal layer and polysilicon layer are shaped into the desired shape. When etching polysilicon, the etching gas used usually has a strong chemical property, such as SF6, NF3, Cl2, etc., which will affect the profile of the polysilicon layer and the metal layer. Specifically, these gases will damage the metal layer, causing the profile of the metal layer to shrink, and these gases will cause the side wall surface of the polysilicon layer to form native oxide (native oxide), which will be removed by the pickling process, which will also cause the profile of the polysilicon layer to shrink severely, and even cause the polysilicon layer to be inverted. Taper, affect the subsequent ion implantation process, cause the final device failure, and limit the yield of the memory produced in the end.

[0023] A semiconductor structure and a method for forming the same proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0024] See also Figures 1 to 13 ,in Figures 1 to 12 is a schematic diagram of a semiconductor structure corresponding to each step of a method for forming a semiconductor structure in a specific embodiment of the present invention, Fig.13 The figure is a schematic flow chart of the steps of a method for forming a semiconductor structure in a specific embodiment of the present invention.

[0025] In this specific embodiment, a method for forming a semiconductor structure is provided, comprising the following steps: S1301 provides a substrate 101, wherein a gate oxide layer 102, a polysilicon layer 103 and a first mask layer 104 are sequentially stacked on the upper surface of the substrate 101, and the gate oxide layer 102, the polysilicon layer 103 and the ... Figure 1 S1302 patterns the first mask layer 104 to form a groove 113 penetrating the first mask layer 104, and the groove 113 exposes the polysilicon layer 103, which can be referred to herein Figure 2 and Figure 4 S1303 forms a metal layer 107 filled in the groove 113, and the upper surface of the metal layer 107 is flush with the upper surface of the first mask layer 104, which can be referred to here Figure 6 S1304 forms an insulating cap 115 on the upper surface of the metal layer 107, wherein the projection of the insulating cap 115 on the upper surface of the substrate 101 coincides with the projection of the groove 113 on the upper surface of the substrate 101, and can be referred to herein Fig. 9; S1305 removes the patterned first mask layer 104, and sequentially removes the exposed polysilicon layer 103 and the gate oxide layer 102; S1306 partially removes the exposed substrate 101, so that the exposed upper surface of the substrate 101 forms a height difference with the lower surface of the gate oxide layer 102, which can be referred to here Fig.12 .

[0026] In this specific embodiment, the method for forming the semiconductor structure first forms a groove 113 of a desired shape, and then forms a metal layer 107 in the groove 113, so that the metal layer 107 of the desired shape can be directly obtained without etching the metal layer 107 in the subsequent production process to obtain the metal layer 107 of the desired shape. In this way, the metal layer 107 will not be damaged by etching and will not shrink.

[0027] When forming the groove 113, it is first necessary to pattern the first mask layer 104. When patterning the first mask layer 104, it is necessary to spin-coat the first photoresist layer 105 on the upper surface of the first mask layer, and then form a hollow area on the first photoresist layer 105, and the hollow area corresponds to the area in the first mask layer 104 where the groove 113 needs to be formed. Afterwards, the first mask layer 104 is patterned by etching means such as dry etching.

[0028] In this specific embodiment, during the process of forming the groove 113, all etchings used are directional etchings, and the etching directions are perpendicular to the surface of the substrate 101, so as to ensure that the sidewall surface of the groove 113 is vertical, perpendicular to the surface of the substrate 101. In this way, the sidewall surface of the insulating cap 115 subsequently formed based on the groove 113 is also vertical.

[0029] In a specific embodiment, before forming the metal layer filled in the groove, the following step is further included: forming a first insulating sidewall 106 on the sidewall surface of the groove 113. Figure 3 , 4 In this way, before removing the first mask layer 104 and removing the exposed polysilicon layer 103 and gate oxide layer 102 in sequence, an insulating sidewall is formed on the sidewall of the metal layer 107, which can block the etching gas used in processing the first mask layer 104, the polysilicon layer 103 and the gate oxide layer 102 from etching the sidewall of the metal layer 107, and prevent the etching gas used to etch the first mask layer 104, the polysilicon layer 103 and the gate oxide layer 102 from affecting the outer contour of the metal layer 107.

[0030] In a specific embodiment, forming the first insulating sidewall 106 on the sidewall surface of the groove 113 includes the following steps: forming an insulating layer 116, the insulating layer 116 covering the sidewall surface and the bottom of the groove 113 and the upper surface of the patterned first mask layer 104, see Figure 3 ; Remove the insulating layer located at the bottom of the groove 113 and the upper surface of the patterned first mask layer 104, see here Figure 4 In this way, a first insulating sidewall 106 is formed on the sidewall surface of the groove 113, and since the insulating layer at the bottom of the groove 113 is removed, the lower surface of the metal layer 107 formed in the groove 113 is in direct contact with the polysilicon layer 103, which is convenient for subsequent circuit formation.

[0031] In this specific embodiment, directional etching is used except for the insulating layer at the bottom of the groove 113 and the upper surface of the patterned first mask layer 104. In a specific embodiment, the directional etching adopts a dry etching method, using SF6, NF3, Cl2 and other gases, which are subjected to high pressure treatment to form plasma, and the plasma is used to bombard the insulating layer to perform direction etching on the insulating layer.

[0032] The directional etching is required here because, when the directional etching is used, it is possible to avoid removing the insulating layer on the side wall of the groove 113 , thereby ensuring that the insulating layer on the side wall of the groove 113 protects the metal layer 107 .

[0033] In a specific implementation, the insulating layer 116 is formed by atomic layer deposition. In a specific implementation, physical vapor deposition or chemical vapor deposition or other methods may be selected as needed to deposit the insulating layer.

[0034] In a specific embodiment, during the formation of the metal layer 107, a metal deposition layer 114 is first formed, the metal deposition layer 114 fills the groove 113 and covers the patterned first mask layer 104, and then the metal deposition layer 114 is planarized to form the metal layer 107. In this specific embodiment, the metal layer 107 above the upper surface of the first mask layer 104 needs to be removed. In a specific embodiment, a chemical mechanical polishing process is used to polish the upper surface of the metal layer 107 until the upper surface of the first mask layer 104 is exposed, and the upper surface of the metal layer 107 is flush with the upper surface of the first mask layer 104. Please refer to Figure 6 .

[0035] In a specific embodiment, when forming an insulating top cap 115 on the upper surface of the metal layer 107, the following steps are included: forming an insulating top cap layer 108 on the upper surfaces of the patterned first mask layer 104 and the metal layer 107; etching the insulating top cap layer 108 to expose the patterned first mask layer 104, and retaining the insulating top cap layer 108 above the metal layer 107 to form an insulating top cap 115, and the projection of the insulating top cap 115 on the surface of the substrate 101 coincides with the projection of the groove 113 on the surface of the substrate 101.

[0036] In this specific embodiment, when the insulating cap layer 108 is etched to expose the patterned first mask layer 104, the following steps are included: forming a second mask layer on the upper surface of the insulating cap layer 108, and forming a second photoresist layer 117 on the upper surface of the second mask layer. Figure 7 In this specific embodiment, a pattern to be etched is formed on the second photoresist layer 117 by photolithography, and the pattern is transferred to the upper surface of the second mask layer. On the upper surface of the second mask layer, etching is started from top to bottom in a direction perpendicular to the surface of the substrate 101 until the patterned first mask layer 104 is exposed.

[0037] In this specific embodiment, a hollow area is engraved on the surface of the second photoresist layer 117 to expose the area to be etched of the second mask layer. The projection of the area to be etched on the surface of the substrate 101 is connected to the edge of the groove 113. When etching the insulating cap layer 108, directional etching is adopted. In this way, after etching the insulating cap layer 108 above the metal layer 107 filled in the groove 113, the side wall surface of the formed insulating cap 115 is flush with the side wall surface of the groove 113, ensuring that the part of the semiconductor structure protruding from the surface of the substrate 101 has a smooth side wall that is perpendicular to the upper surface of the substrate 101.

[0038] In this specific embodiment, since the first insulating sidewall 106 is formed on the sidewall surface of the groove 113 before the metal is filled in the groove 113 , the sidewall of the insulating cap 115 is flush with the surface of the insulating sidewall.

[0039] In a specific embodiment, the first mask layer 104 includes a first amorphous carbon layer 104, the second mask layer includes a second amorphous carbon layer 109 and a silicon oxynitride layer 110, the silicon oxynitride layer 110 is formed on the upper surface of the second amorphous carbon layer 109, and the second amorphous carbon layer 109 is formed on the upper surface of the insulating cap layer 108.

[0040] In a specific embodiment, when the second mask layer is etched to expose the upper surface of the first mask layer 104, the pattern of the second photoresist layer 117 is first transferred to the surface of the silicon oxynitride layer 110 to expose the upper surface of the second amorphous carbon layer 109. Thereafter, the pattern transferred to the surface of the silicon oxynitride layer 110 is transferred to the second amorphous carbon layer 109, and the second amorphous carbon layer 109 is etched downward to a preset depth.

[0041] After the above operations are completed, the remaining second photoresist layer 117, the remaining silicon oxynitride layer 110, and the second amorphous carbon layer 109 above the preset depth can be removed. Figure 8 .

[0042] In a specific embodiment, the remaining second amorphous carbon layer 109 is first removed, as can be seen in Fig. 9 After removing the second amorphous carbon layer 109, the first amorphous carbon layer 104 and the exposed polysilicon layer 103 are removed. Fig.10 .

[0043] In this specific embodiment, etching or ashing is used to remove the first amorphous carbon layer 104 and the second amorphous carbon layer 109. For example, the exposed patterned first amorphous carbon layer 104 can be removed by a plasma dry etching process to expose the polysilicon layer 103. In a specific embodiment, the exposed polysilicon layer 103 can be removed by a stripping process.

[0044] In a specific implementation, the insulating cap layer 108, the first insulating sidewall 106 and the second insulating sidewall 111 are all made of silicon nitride. In fact, the second insulating sidewall 111 can also be silicon oxynitride.

[0045] In a specific embodiment, when removing the patterned first mask layer 104, and removing the exposed polysilicon layer 103 and the gate oxide layer 102 in sequence, the following steps are included: removing the patterned first mask layer 104 by directional etching to expose the polysilicon layer 103; removing the exposed polysilicon layer 103 by directional etching to expose the gate oxide layer 102; removing the exposed gate oxide layer 102 by directional etching.

[0046] In this specific embodiment, since the portions of the polysilicon layer 103 that are not exposed are all covered by the insulating top cover 115, and the edges of the insulating top cover 115 are flush with the sides of the groove 113, after the polysilicon layer 103 is processed, the projection of the remaining portion on the substrate 101 also coincides with the projection of the groove 113 on the substrate 101.

[0047] In a specific embodiment, after removing the exposed polysilicon layer 103, the following step is further included: converting the sidewall of the etched polysilicon layer 103 into a second insulating sidewall 111, which can be referred to herein. Fig.11 The second insulating sidewall 111 may be made of silicon nitride or silicon oxynitride.

[0048] By converting the sidewall of the etched polysilicon layer 103 into the second insulating sidewall 111, it is not necessary to remove the oxide formed on the sidewall of the polysilicon layer 103 during the etching of the polysilicon layer 103 by pickling, thus avoiding the sidewall damage of the polysilicon layer 103 caused by the pickling process, causing the necking or inverted taper of the polysilicon layer 103. This also avoids affecting the ion implantation effect due to the profile problem of the semiconductor structure.

[0049] In a specific embodiment, the second insulating sidewall 111 is a silicon nitride sidewall. When the sidewall of the etched polysilicon layer 103 is converted into the second insulating sidewall 111, the following steps are included: using nitrogen to react with the sidewall of the etched polysilicon layer 103 to convert the sidewall of the polysilicon layer into a silicon nitride sidewall.

[0050] In this specific embodiment, nitrogen reacts with oxide generated on the sidewalls of the polysilicon layer 103 to generate silicon nitride, thereby forming silicon nitride sidewalls.

[0051] In a specific embodiment, the thickness of the second insulating sidewall 111 formed on the side of the polysilicon layer 103 is 2 to 3 nm. This can be determined by controlling the amount of nitrogen and the reaction time. In a specific embodiment, the thickness of the first insulating sidewall 106 is also 2 to 3 nm. In fact, the thickness of the first insulating sidewall 106 and the second insulating sidewall 111 can be determined as needed.

[0052] In a specific embodiment, when the exposed substrate 101 is partially removed so that a height difference is formed between the exposed upper surface of the substrate 101 and the lower surface of the gate oxide layer 102, the following steps are included: the exposed upper surface of the substrate 101 is bombarded downwardly by plasma in a direction perpendicular to the surface of the substrate 101 so that the height of the exposed upper surface of the substrate 101 is lower than the height of the lower surface of the gate oxide layer 102. Fig.12 .

[0053] In a specific implementation, the substrate 101 is bombarded to be recessed 3-5 nm downward in a direction perpendicular to the surface of the substrate 101, that is, the height difference is 3-5 nm. In practice, the size of the height difference can be determined according to needs.

[0054] In this specific embodiment, the metal layer 107 is filled into the groove 113 to form a metal layer 107 with specific properties, which can avoid using SF6 or CF4 gas to etch the metal layer 107, so that the metal layer 107 presents a specific shape. This helps to prevent the F radicals in the SF6 or CF4 gas from affecting the insulating cap 115 formed on the upper surface of the metal layer 107, causing the insulating cap 115 to be too low, and also avoids the problem of necking of the metal layer 107 when the polysilicon layer 103 is subsequently etched using SF6 or CF4 gas.

[0055] Moreover, the semiconductor structure forming method in this specific embodiment forms a second insulating sidewall 111 on the sidewall of the polysilicon layer 103, and converts the second insulating sidewall of the oxide conversion layer formed on the sidewall surface of the polysilicon layer 103 during the etching process, instead of using processes such as pickling to remove the oxide on the sidewall of the polysilicon layer 103, which can effectively avoid damage to the sidewall of the polysilicon layer 103 during the pickling process, and prevent the polysilicon layer 103 from necking or even inverted taper. In this specific embodiment, the portion protruding from the substrate surface is finally formed, and its contour is smooth. It is a vertical sidewall perpendicular to the substrate surface formed based on the sidewall of the groove, which will not affect the ion injection path during the subsequent ion injection, improves the success rate of ion injection, and avoids device failure. When the semiconductor structure is used to form the gate of a memory circuit, the semiconductor structure forming method also simplifies the process flow of preparing the gate.

[0056] In this specific embodiment, a semiconductor structure is also provided, including: a substrate 101; a gate oxide layer 102 formed on the upper surface of the substrate 101; a polysilicon layer 103 formed on the upper surface of the gate oxide layer 102; a first mask layer 104 formed on the upper surface of the polysilicon layer 103; a groove 113 formed on the upper surface of the first mask layer 104; a metal layer 107 formed in the groove 113 and a first insulating sidewall 106 formed on the sidewall surface of the metal layer 107; and an insulating top cover 115 formed on the upper surface of the metal layer 107.

[0057] In this specific embodiment, the semiconductor structure forms a metal layer 107 of a specific shape in a groove 113 of a specific shape. Thus, when the semiconductor structure is applied to the preparation of a gate of a memory circuit, as long as the contour of the groove 113 is controlled to be consistent with the outer contour of the metal layer required for the gate when forming the groove 113, a metal layer 107 of a desired shape can be obtained without the user having to etch the metal layer 107 to make the metal layer 107 present the desired shape, thereby avoiding the influence on the side wall of the metal layer 107 during the etching process and avoiding the necking of the outer contour of the metal layer 107 under the etching action.

[0058] In a specific implementation, the groove 113 exposes the upper surface of the polysilicon layer 103 , so that the lower surface of the metal layer 107 formed in the groove 113 can directly contact the polysilicon layer 103 , facilitating subsequent circuit formation.

[0059] In this specific embodiment, the upper surface of the metal layer 107 is flush with the upper surface of the first mask layer 104. In this way, the metal layer 107 can be defined by defining the thickness of the first mask layer 104, as long as the metal layer 107 is flattened to the same height as the first mask layer 104 when forming the metal layer 107.

[0060] In this specific implementation, the first insulating sidewall 106 includes a silicon nitride sidewall, and the first mask layer 104 includes an amorphous carbon layer. In fact, the specific material of the first mask layer 104 can also be selected according to needs.

[0061] In a specific embodiment, the substrate 101 is a semiconductor substrate, and germanium and silicon are commonly used as raw materials for the semiconductor substrate. In fact, the preparation material of the semiconductor substrate can be selected according to needs, such as gallium arsenide, gallium phosphide, cadmium sulfide, zinc sulfide, etc.

[0062] In a specific implementation, the gate oxide layer 102 is made of silicon dioxide, or other high-K dielectric materials, such as titanium dioxide.

[0063] In a specific implementation, the metal layer 107 includes a tungsten layer. In practice, the metal layer 107 may be made of a specific composition such as a titanium nitride layer.

[0064] In a specific implementation, the insulating cap 115 is a silicon nitride cap.

[0065] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for forming a semiconductor structure, characterized in that: The following steps are involved: Providing a substrate, wherein a gate oxide layer, a polysilicon layer and a first mask layer are sequentially stacked on the upper surface of the substrate; Patterning the first mask layer to form a groove penetrating the first mask layer, wherein the groove exposes the polysilicon layer; forming a first insulating sidewall on a sidewall surface of the groove; forming a metal layer filled in the groove, wherein the upper surface of the metal layer is flush with the upper surface of the first mask layer; forming an insulating cap on the upper surface of the metal layer, wherein a projection of the insulating cap on the upper surface of the substrate coincides with a projection of the groove on the upper surface of the substrate; removing the patterned first mask layer by directional etching to expose the polysilicon layer; The exposed polysilicon layer is removed by directional etching to expose the gate oxide layer; nitrogen is used to react with the sidewalls of the etched polysilicon layer to convert the sidewalls of the polysilicon layer into silicon nitride sidewalls; removing the exposed gate oxide layer by directional etching; The exposed substrate is partially removed so that the height of the upper surface of the substrate at both sides of the gate oxide layer is lower than the height of the lower surface of the gate oxide layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: Forming a first insulating sidewall on the sidewall surface of the groove comprises the following steps: forming an insulating layer, wherein the insulating layer covers the sidewall surface and the bottom of the groove and the upper surface of the patterned first mask layer; The insulating layer located at the bottom of the groove and the upper surface of the patterned first mask layer is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: The forming of the insulating layer comprises: forming the insulating layer by atomic layer deposition; The removing of the insulating layer at the bottom of the groove and the upper surface of the patterned first mask layer comprises: removing the insulating layer at the bottom of the groove and the upper surface of the patterned first mask layer by directional etching.

4. The method for forming a semiconductor structure according to claim 1, wherein: The forming of the metal layer filled in the groove comprises: forming a metal deposition layer, wherein the metal deposition layer fills the groove and covers the patterned first mask layer; The metal deposition layer is planarized to form a metal layer.

5. The method for forming a semiconductor structure according to claim 1, wherein: When an insulating cap is formed on the upper surface of the metal layer, the steps include: forming an insulating cap layer on the upper surfaces of the patterned first mask layer and the metal layer; The insulating cap layer is etched to expose the patterned first mask layer, and the insulating cap layer above the metal layer is retained to form an insulating cap.

6. The method for forming a semiconductor structure according to claim 1, wherein: Partially removing the exposed substrate, comprising the following steps: The exposed upper surface of the substrate is bombarded downward by plasma in a direction perpendicular to the surface of the substrate.

7. The method for forming a semiconductor structure according to claim 1, wherein: The height difference is 3-5 nm.

8. A semiconductor structure, characterized in that: include: substrate; A gate oxide layer is formed on the upper surface of the substrate, wherein the height of the upper surface of the substrate on both sides of the gate oxide layer is lower than the height of the lower surface of the gate oxide layer; A polysilicon layer formed on the upper surface of the gate oxide layer, wherein the sidewalls of the polysilicon layer are formed with silicon nitride sidewalls; a first mask layer formed on the upper surface of the polysilicon layer; A groove formed on the surface of the first mask layer; A metal layer is formed in the groove and a first insulating side wall is formed on the side wall surface of the metal layer; and an insulating top cover is formed on the surface of the metal layer.

9. The semiconductor structure according to claim 8, characterized in that: The groove exposes the upper surface of the polysilicon layer, and the upper surface of the metal layer is flush with the upper surface of the first mask layer.

10. The semiconductor structure according to claim 8, characterized in that The first insulating sidewall includes a silicon nitride sidewall, and the first mask layer includes an amorphous carbon layer.

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