A ground base station system

Abstract

A ground base station system includes: a crystal oscillator module, a temperature compensation module, a control module, a frequency selection amplification module, a signal shaping module, a quantum module, a long stability module, a short stability module, an isolation amplifier, a DDS frequency division module, a phase detector, a GPS receiver, a loop filter module and a GPS antenna. The ground base station system provided by the present application has high precision.

Description

Technical Field

[0001] The invention belongs to the technical field of Beidou navigation satellites, and in particular relates to a ground base station system. Background Art

[0002] At present, Beidou satellites have become one of the main means of transmitting time and frequency for navigation in my country. Due to the continuous deepening of research on multi-mode navigation systems, my country's Beidou navigation satellite network has gradually improved, and the combination of multiple global navigation satellite systems has become a hot area in the future. The pseudo-random noise codes emitted by GLONASS satellites are the same, and the frequencies emitted by different satellites are different, which is used to distinguish different satellites, that is, frequency division multiple access. Atomic clocks (atomic time and frequency standards) are the basic conditions for human scientific and technological activities. The improvement of the accuracy and precision of time and frequency measurements will fundamentally change the face of a series of major natural sciences and applied technologies. In basic scientific research, such as the verification of general relativity, the measurement of light speed anisotropy, the measurement of gravitational gradients, and the measurement of atomic physical constants changing over time, all require precise timing standards.

[0003] The construction of space laboratories and space stations is an important part of my country's manned space program. From the perspective of payload volume weight and the orbit of the space station, high-precision space cold atomic clocks are suitable as a payload of the space station. As the core technology and key content of precise positioning technology, the research on high-precision atomic clocks is even more important. Based on the research on space cold atomic clocks on the International Space Station, in addition to the European Space Agency's ACES (Atomic Clock Ensemble in Space) project planned to be launched in 2013, the United States once had projects such as PARCS (Primary Atomic Reference Clock in Space) and RACE (Rubidium Atomic Clock Experiment). However, due to changes in the US space strategy, these projects are currently suspended, but there is still a small amount of funding to continue to support them. my country is also carrying out space cold atomic clock projects. The implementation of these projects will open up new directions for the research of time and frequency standards, and the timing accuracy of mankind will be further improved. High-precision atomic clocks and time and frequency transmission technologies will better serve the future third-generation positioning and navigation systems. In addition, the new generation of optical clocks may achieve a stability of 10-17 to 10-18. For atomic clocks of such precision, the influence of factors such as tides that affect the change of gravitational potential on the stability of the atomic clock has become non-negligible. It will be very necessary to use the atomic clock in the microgravity environment of space to more accurately measure the gravitational frequency shift of the atomic clock. Summary of the invention

[0004] In view of the above problems, the present invention provides a ground base station system that overcomes the above problems or at least partially solves the above problems.

[0005] To solve the above technical problems, the present invention provides a ground base station system, comprising: a crystal oscillator module, a temperature compensation module, a control module, a frequency selection amplification module, a signal shaping module, a quantum module, a long stable module, a short stable module, an isolation amplifier, a DDS frequency division module, a phase detector, a GPS receiver, a loop filter module and a GPS antenna, wherein the crystal oscillator module is respectively connected to the temperature compensation module, the control module and the frequency selection amplification module, the temperature compensation module is connected to the control module, the control module is connected to the quantum module, the frequency selection amplification module is connected to the signal shaping module, the signal shaping module is connected to the isolation amplifier, the long stable module and the short stable module are respectively connected to the quantum module and the isolation amplifier, the DDS frequency division module is respectively connected to the isolation amplifier and the phase detector, the phase detector is respectively connected to the GPS receiver and the loop filter module, the GPS receiver is connected to the GPS antenna, and the loop filter module is connected to the crystal oscillator module.

[0006] Preferably, the crystal oscillator module includes: a crystal oscillator, a thermistor R3, a varactor D1, a varactor D2 and a varactor D3, wherein the oscillator is connected to the thermistor R3, and the crystal oscillator is respectively connected to the resistor R1, the cathode of the varactor D1, the cathode of the varactor D2 and the cathode of the varactor D3.

[0007] Preferably, the temperature compensation module includes: resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, thermistor Rm, thermistor Rn, voltage follower A1, voltage follower A2 and voltage follower A3, wherein the first end of the resistor R4 is connected to the Ucc signal end and the second end is connected to the positive input end of the voltage follower A1, the first end of the resistor R5 is connected to the Ucc signal end and the second end is connected to the positive input end of the voltage follower A2, the first end of the thermistor Rm is connected to the positive input end of the voltage follower A1 and the second end is grounded, the first end of the thermistor Rn is connected to the positive input end of the voltage follower A2 and the second end is grounded, the first end of the resistor R6 is connected to the voltage follower A1 is connected to the output end and the second end is connected to the negative input end of the voltage follower A3, the negative input end of the voltage follower A1 is connected to its own output end, the first end of the resistor R7 is connected to the negative input end of the voltage follower A3 and the second end is grounded, the first end of the resistor R8 is connected to the output end of the voltage follower A2 and the second end is connected to the positive input end of the voltage follower A3, the negative input end of the voltage follower A2 is connected to its own output end, the output end of the voltage follower A3 is connected to the Uout signal end, the first end of the resistor R9 is connected to the positive input end of the voltage follower A3 and the second end is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the Uout signal end.

[0008] Preferably, the temperature compensation module further includes: a voltage follower A4, a positive input terminal of the voltage follower A4 is grounded and a negative input terminal is connected to the second end of the resistor R11, and an output terminal of the voltage follower A4 is connected to the second end of the resistor R9.

[0009] Preferably, the ground base station system also includes: a time correction module, a voltage-controlled correction module and a servo module, wherein the crystal oscillator module is respectively connected to the time correction module and the voltage-controlled correction module, the voltage-controlled correction module is connected to the servo module, the servo module is respectively connected to the time correction module and the quantum module, and the time correction module is connected to the GPS receiver.

[0010] Preferably, the ground base station system also includes: a timer and a delay array module, wherein the timer is connected to the crystal oscillator module and the servo module, and the delay array module is respectively connected to the timer, the DDS frequency division module and the servo module.

[0011] Preferably, the delay array module comprises: a first counter, a second counter and a NOT gate array, wherein the first counter and the second counter are connected to the servo module and the NOT gate array respectively.

[0012] Preferably, the ground base station system also includes: a temperature control module and a phase accumulation module, wherein the crystal oscillator module is respectively connected to the DDS frequency division module and the temperature control module, and the phase accumulation module is respectively connected to the DDS frequency division module, the GPS receiver and the servo module.

[0013] Preferably, the phase accumulation module includes: an isolation amplification unit, a DDS processing module, a low-pass filtering module, a travel time counter, a latch and a single-chip microcomputer, wherein the isolation amplification unit is respectively connected to the DDS processing module and the travel time counter, the single-chip microcomputer is respectively connected to the latch and the DDS processing module, the DDS processing module is connected to the low-pass filtering module, and the travel time counter is connected to the latch.

[0014] Preferably, the temperature control module comprises: a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor Rw, a thermistor Ra, a thermistor Rb, a voltage follower A, a voltage source and a heating coil loop, wherein the first end of the resistor R12 is grounded and the second end is connected to the first end of the resistor R15, the first end of the resistor R13 is grounded and the second end is connected to the first end of the resistor R14, the second end of the resistor R14 is connected to the positive input end of the voltage follower A, the second end of the resistor R15 is connected to the negative input end of the voltage follower A, and the resistor The first end of R16 is connected to the positive input end of the voltage follower A and the second end is grounded, the first end of the resistor Rw is connected to the negative input end of the voltage follower A and the second end is connected to the output end of the voltage follower A, the output end of the voltage follower A is connected to the first end of the heating coil loop, the second end of the heating coil loop is connected to the first end of the voltage source, the first end of the thermistor Ra is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R15, the first end of the thermistor Rb is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R14.

[0015] One or more technical solutions in the embodiments of the present invention have at least the following technical effects or advantages: The ground base station system provided by the present application has high accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a schematic diagram of a Beidou satellite system provided by an embodiment of the present invention;

[0018] Figure 2 is a schematic diagram of a satellite-borne clock system provided by an embodiment of the present invention;

[0019] Figure 3 is a schematic diagram of a double-bubble physical system provided by an embodiment of the present invention;

[0020] Figure 4 is a schematic diagram of a temperature control module system provided by an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of another embodiment of a satellite-borne clock system provided by an embodiment of the present invention;

[0022] Figure 6 This is a working schematic diagram of a status indication module in a satellite-borne clock system provided by an embodiment of the present invention;

[0023] Figure 7 is a signal timing diagram of a satellite-borne clock system provided by an embodiment of the present invention;

[0024] Figure 8 is a schematic diagram of a ground base station system provided by an embodiment of the present invention;

[0025] Fig. 9 is a schematic diagram of a crystal oscillator module provided by an embodiment of the present invention;

[0026] Fig.10 is a schematic diagram of a temperature compensation module provided by an embodiment of the present invention;

[0027] Fig.11 is a schematic diagram of another embodiment of a ground base station system provided by an embodiment of the present invention;

[0028] Fig.12 is a timing diagram of a ground base station system provided by an embodiment of the present invention;

[0029] Fig.13 is a schematic diagram of another embodiment of a ground base station system provided by an embodiment of the present invention;

[0030] Fig.14is a schematic diagram of a delay array module provided by an embodiment of the present invention;

[0031] Fig.15 is a timing diagram of a delay array module provided by an embodiment of the present invention;

[0032] Fig.16 is a measurement schematic diagram of a delay array module provided by an embodiment of the present invention;

[0033] Fig.17 is a schematic diagram of a NOT gate array provided by an embodiment of the present invention;

[0034] Fig.18 is a schematic diagram of another embodiment of a ground base station system provided by an embodiment of the present invention;

[0035] Fig.19 is a schematic diagram of a phase accumulation module provided by an embodiment of the present invention;

[0036] Fig. 20 is a timing diagram of a phase accumulation module provided by an embodiment of the present invention;

[0037] Fig.21 It is a schematic diagram of a temperature control module provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0038] The present invention will be described in detail below in conjunction with specific implementations and examples, and the advantages and various effects of the present invention will be more clearly presented. It should be understood by those skilled in the art that these specific implementations and examples are used to illustrate the present invention, rather than to limit the present invention.

[0039] Throughout the specification, unless otherwise specifically stated, the terms used herein should be understood as meanings commonly used in the art. Therefore, unless otherwise defined, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art to which the present invention belongs. In the event of a conflict, the present specification takes precedence.

[0040] Unless otherwise specified, various raw materials, reagents, instruments and equipment used in the present invention can be purchased from the market or prepared by existing methods.

[0041] like Figure 1 In an embodiment of the present application, the present application provides a BeiDou satellite system, including:

[0042] The onboard clock system 100 is used to provide a precise time function;

[0043] The ground base station system 200 is used to provide a time calibration function for the ground terminal;

[0044] The ground-to-space timing system 300 is used for communication between the satellite-borne clock system 100 and the ground base station system 200; the ground-to-space timing system 300 is communicatively connected with the satellite-borne clock system 100 and the ground-to-space timing system 300 respectively.

[0045] In the embodiment of the present application, specifically, the satellite clock system 100 runs in space, and there is a microgravity environment in space. The satellite clock system 100 is hardly disturbed by the outside world in the microgravity environment, so that it can provide accurate time function. The ground base station system 200 is arranged on the ground, and can provide time calibration function for the ground terminal. The ground-space timing system 300 is arranged between the two (for example, arranged on the orbit of the satellite around the earth), and communicates with the satellite clock system 100 and the ground base station system 200 respectively. The ground base station system 200 sends a time calibration command to the satellite clock system 100 through the ground-space timing system 300, and the satellite clock system 100 provides the accurate time to the ground base station system 200 through the ground-space timing system 300, so that the ground base station system 200 can be time-calibrated, and then provide accurate time calibration service for the ground terminal.

[0046] like Figure 2 In an embodiment of the present application, the satellite-borne clock system 100 includes: a high-stable crystal oscillator 101, a microwave radio frequency source 102, an integrated servo module 103, a first synchronous phase detection module 104, a second synchronous phase detection module 105, a central processing unit 106 and a double-bubble physical system 107, wherein the high-stable crystal oscillator 101 is respectively connected to the microwave radio frequency source 102 and the integrated servo module 103, the microwave radio frequency source 102 is respectively connected to the integrated servo module 103 and the double-bubble physical system 107, the integrated servo module 103 is respectively connected to the first synchronous phase detection module 104 and the second synchronous phase detection module 105, the first synchronous phase detection module 104 is respectively connected to the central processing unit 106 and the double-bubble physical system 107, and the second synchronous phase detection module 105 is respectively connected to the central processing unit 106 and the double-bubble physical system 107.

[0047] like Figure 3In the embodiment of the present application, the double-bubble physical system 107 includes: a magnetic shield 11, a constant temperature layer 12, a microwave cavity 13, an electric field 14, a metal shielding layer 15, a first integrated filter resonance bubble 16, a second integrated filter resonance bubble 17, a first coupling ring 18, a second coupling ring 19, a first photocell 111, a second photocell 112, a spectrum lamp 113 and a thermostat 114, wherein the constant temperature layer 12 is arranged inside the magnetic shield 11, the microwave cavity 13 is arranged inside the constant temperature layer 12, the electric field 14 is arranged along the surface of the microwave cavity 13, the metal shielding layer 15 is arranged inside the microwave cavity 13, and its internal The magnetic shield 11 is divided into a first cavity and a second cavity isolated from each other, the first integrated filter resonance bubble 16, the first coupling ring 18 and the first photocell 111 are arranged in the first cavity, the second integrated filter resonance bubble 17, the second coupling ring 19 and the second photocell 112 are arranged in the second cavity, the thermostat 114 is arranged above the magnetic shield 11, and the spectrum lamp 113 is arranged inside, the first battery is respectively connected to the first synchronous phase-detection module 104 and the second synchronous phase-detection module 105, and the second battery is respectively connected to the first synchronous phase-detection module 104 and the second synchronous phase-detection module 105.

[0048] In the embodiment of the present application, the modulation signal generated by the integrated servo module 103 and the signals of the first synchronous phase detection module 104 and the second synchronous phase detection module 105 are three coherent signals, that is, the frequencies and phases are the same.

[0049] Specifically, the working mode of the onboard clock system 100 in the first 3-5 years is as follows:

[0050] (1) The satellite-borne clock system 100 first starts the first synchronous phase detection module 104 and the second synchronous phase detection module 105 respectively, and completes the operation according to the conventional servo principle. Figure 3 The frequency sweep of the atomic absorption spectrum in the entire double-bubble physical system 107 is performed, and the corresponding voltage values ​​V1 and V2 at the corresponding frequencies f1 and f2 are obtained simultaneously, which are recorded as V11 and V12 for the first synchronous phase-locking module 104 and as V21 and V22 for the second synchronous phase-locking module 105, and are stored in the central processing unit 106 at the same time.

[0051] (2) Then, when the onboard clock system 100 enters the closed-loop operation, the first synchronous phase detection module 104 is used as the traditional synchronous phase detection main module, and the second synchronous phase detection module 105 is used for auxiliary judgment. According to the traditional scheme, ΔV1=V11-V12 will be used as the judgment basis for whether the entire double-bubble physical system 107 is closed-loop locked. This basis has been stored and judged by the central processor 106, that is, if the second synchronous phase detection module 105 is not enabled, the double-bubble physical system 107 will work with the first synchronous phase detection module 104 at a certain moment, and the obtained synchronous phase detection error signal ΔW1 will be transmitted to the central processor 106, and the central processor 106 will perform the following operation: ΔW1-ΔV1, if the difference is a negative number, the central processor 106 will output the corresponding quantum deviation correction signal to act on the high-stability crystal oscillator 101, so that its output frequency value increases; similarly, if the difference is a positive number, the central processor 106 will output the corresponding quantum deviation correction signal to act on the high-stability crystal oscillator 101, so that its output frequency value decreases. Finally, ΔW1-ΔV1=0 dynamically.

[0052] Compared with the traditional technology, the present application introduces the second synchronous phase detection module 105 as an auxiliary module. Since the quantum frequency detection signals entering the first synchronous phase detection module 104 and the second synchronous phase detection module 105 are both from Figure 3 The first photocell 111 in the first integrated filter resonance bubble 16 on the left side of the double-bubble physical system 107. Here, the two quantum frequency discrimination signals obtained are expected to reflect consistent information. Therefore, for the resonant cavity in the form of TE111, the intensity of the longitudinal component of the microwave magnetic field is the strongest on both sides of the coupling ring, so the strongest atomic resonance transition signal is on both sides of the cavity under working conditions. Therefore, the first photocell 111 and the second photocell 112 are symmetrically installed on both sides of the central axis (i.e., the metal shielding layer 15), so that the signals they obtain are the strongest and can consistently reflect the quantum frequency situation of the double-bubble physical system 107.

[0053] According to the method in the above step (2), the central processor 106 will respectively determine the values ​​of (ΔW1-ΔV1) and (ΔW2-ΔV2). If both are positive or negative at the same time, it means that the onboard clock system 100 needs to be corrected due to part of the double-bubble physical system 107. Then the central processor 106 will use the first synchronous phase-locking module 104 to complete the entire closed-loop locking in the manner of the above step (2).

[0054] If the central processing unit 106 respectively determines that the values ​​of (ΔW1-ΔV1) and (ΔW2-ΔV2) are (positive, negative) or (negative, positive), it means that the star-borne clock system 100 may have different correction requirements due to interference from peripheral circuits. At this time, the central processing unit 106 will not perform a correction operation, that is, the frequency of the high-stability crystal oscillator 101 will not be changed.

[0055] If the central processor 106 determines that the values ​​of (ΔW1-ΔV1) and (ΔW2-ΔV2) are (0, positive or negative) respectively, then since the first synchronous phase-locking module 104 is the main synchronous phase-locking module, the central processor 106 believes that it is locked at this time and will not perform the correction operation, that is, the frequency of the high-stability crystal oscillator 101 will not be changed.

[0056] If the central processor 106 determines that the values ​​of (ΔW1-ΔV1) and (ΔW2-ΔV2) are (positive or negative, 0) respectively, then since the first synchronous phase-locking module 104 is the main synchronous phase-locking module, the central processor 106 believes that it is not locked at this time and will perform a correction operation, that is, changing the frequency of the high-stability crystal oscillator 101.

[0057] In the above four situations, the central processor 106 performs corresponding operations respectively until ΔW1-ΔV1=0, at which time the closed-loop locking of the entire onboard clock system 100 can be achieved.

[0058] The above-mentioned first synchronous phase detection module 104 and the second synchronous phase detection module 105 are used in the simultaneous working mode in order to further improve the short-term stability of the satellite-borne clock system 100 and avoid interference caused by external interference or internal operation.

[0059] Specifically, after 3-5 years, the onboard clock system 100 operates as follows:

[0060] At this time, the alkali metal in the first integrated filter resonance bubble 16 has been consumed, and the double-bubble physical system 107 switches the second integrated filter resonance bubble 17 on the right to enter the working mode. The modulation signal generated by the integrated servo module 103 and the signal of the first synchronous phase-detection module 104 are two coherent signals, that is, the frequency and phase are the same, but the second synchronous phase-detection module 105 signal is no longer generated, because at this time, after 3-5 years, the system has entered a very stable working state, and there is no need to consider the short stability of the satellite-borne clock system 100, but more consideration is given to the life of the satellite-borne clock system 100. Therefore, the second synchronous phase-detection module 105, which is used as an auxiliary judgment, is turned off at this time.

[0061] According to the traditional scheme, ΔV1=V11-V12 will be used as the basis for judging whether the entire double-bubble physical system 107 is closed-loop locked. This basis has been stored and judged by the central processor 106. The onboard clock system 100 will work with the first synchronous phase-locking module 104 at a certain moment, and the obtained synchronous phase-locking error signal ΔW1 will be transmitted to the central processor 106. The central processor 106 will perform the following operation: ΔW1-ΔV1. If the difference is a negative number, the central processor 106 will output a corresponding quantum correction signal to act on the high-stability crystal oscillator 101 to increase its output frequency value; similarly, if it is a positive number, the central processor 106 will output a corresponding quantum correction signal to act on the high-stability crystal oscillator 101 to reduce its output frequency value, and finally dynamically make ΔW1-ΔV1=0.

[0062] like Figure 2 In an embodiment of the present application, the satellite-borne clock system 100 further includes: a temperature control module 108 , and the temperature control module 108 is connected to the double-bubble physical system 107 .

[0063] like Figure 4 In the embodiment of the present application, the temperature control module 108 includes: a digital potentiometer Ro, a first resistor R1, a second resistor R2, a first thermistor Rk, a second thermistor Rz, a temperature control chip and a processor, wherein the first fixed end of the digital potentiometer Ro is grounded and the second fixed end is respectively connected to the first end of the first resistor R1 and the first end of the temperature control chip, the sliding end of the digital potentiometer Ro is connected to the processor, the second end of the first resistor R1 is connected to the Ucc signal end, the first end of the second resistor R2 is connected to the Ucc signal end and the second end is connected to the second end of the temperature control chip, the first end of the first thermistor Rk is grounded and the second end is connected to the second end of the temperature control chip, the second thermistor Rz is connected to the processor, and the first thermistor Rk, the second thermistor Rz and the temperature control chip are all arranged on the control / temperature measurement body.

[0064] In the embodiment of the present application, the digital potentiometer Ro, the first resistor R1, the second resistor R2 and the first thermistor Rk together form a Wheatstone bridge, the first resistor R1 and the second resistor R2 are mutually symmetrical resistors, and the selection of the two should meet the same manufacturer and the same batch, and the two symmetrical resistors should be as consistent as possible, especially the temperature coefficient, and the resistance of the first resistor R1, the second resistor R2 should be close to the digital potentiometer Ro and the first thermistor Rk. The processor can assign a value to the digital potentiometer Ro through a command word, and the specific resistance of the digital potentiometer Ro reflects the preset working temperature t of the control / temperature measuring body (such as the double-bubble physical system 107). The first thermistor Rk is attached to the inner surface of the control / temperature measuring body to measure the actual working temperature t' of the control / temperature measuring body. When the resistance of the digital potentiometer Ro is not equal to the resistance of the first thermistor Rk, an electromotive force gradient UAB will be formed at A and B at both ends of the Wheatstone bridge. UAB can be positive or negative. When the resistance of the digital potentiometer Ro is equal to the resistance of the first thermistor Rk, UAB=0. The temperature control chip is attached to the inner surface of the control / temperature measuring body to heat the control / temperature measuring body. The heating mechanism is determined by the UAB value. When UAB is positive or negative, the temperature control chip implements heating or cooling until UAB = 0. At this time, the actual working temperature of the control / temperature measuring body is already at the working point of the digital potentiometer Ro value set by the processor. At this time, the resistance of the first thermistor Rk is equal to the resistance of the digital potentiometer Ro. The second thermistor Rz is attached to the inner surface of the control / temperature measuring body to measure the actual working temperature t' of the control / temperature measuring body and feed back the measurement information to the processor. The processor indirectly sets the working temperature t1 of the control / temperature measuring body by setting the resistance of the digital potentiometer Ro in the control / temperature measuring body. Under the action of the Wheatstone bridge, once the resistance of the digital potentiometer Ro is not equal to the resistance of the first thermistor Rk, the constant temperature chip will work until the working temperature of the control / temperature measuring body is constant at the preset temperature point. At this time, the resistance of the second thermistor Rz should be close to the resistance of the digital potentiometer Ro and the resistance of the first thermistor Rk, and the measurement information will be transmitted to the processor. The final effect of this implementation is to keep the overall temperature of the entire control / temperature measuring body appropriate.

[0065] like Figure 5 In an embodiment of the present application, the satellite-borne clock system 100 also includes: a status indication module 109, and the status indication module 109 is respectively connected to the central processor 106 and the double-bubble physical system 107, and the central processor 106 is also connected to the microwave radio frequency source 102.

[0066] like Figure 6The working diagram of the status indication module 109 is shown in FIG. 1 . Specifically, the status indication module 109 is an indicator light. Each of the VCXO component, the electronic circuit component and the physical system component is provided with a status indication module 109, that is, a normal indicator light and a fault indicator light are provided. When the component is working normally, the normal indicator light is on, and when the component is faulty, the fault indicator light is on. The status indication module 109 provided for the whole machine is a working indicator light. When the whole machine is working, the working indicator light is on. Specifically, the VCXO component includes a high-stability crystal oscillator 101, the electronic circuit component includes a microwave radio frequency source 102, an integrated servo module 103, a first synchronous phase-detection module 104 and a second synchronous phase-detection module 105, and the physical system component includes a magnetic shield 11, a constant temperature layer 12, a microwave cavity 13, an electric field 14, a metal shielding layer 15, a first integrated filter resonance bubble 16, a second integrated filter resonance bubble 17, a first coupling ring 18, a second coupling ring 19, a first photocell 111, a second photocell 112, a spectrum lamp 113 and a thermostat 114.

[0067] Specifically, a timer is preset in the internal program of the central processor 106, and a corresponding square wave level is output to each component every second to detect the working status of each component. When the detected component is working normally, the central processor 106 controls the status indication module 109 to emit a first color of light; when the detected component is not working properly, the central processor 106 controls the status indication module 109 to emit a second color of light. The working principle of the status indication module 109 is described below with a specific embodiment.

[0068] The central processor 106 includes a travel time counter, which can be used to predict the output frequency of the high-stable crystal oscillator 101. Before power-on, the internal memory of the central processor 106 records the specific model of the high-stable crystal oscillator 101 and the corresponding voltage-controlled slope value data. When powered on or when a fault occurs, according to the traditional atomic clock technology solution, the central processor 106 makes the high-stable crystal oscillator 101 work in an open-loop state. At this time, the central processor 106 changes the voltage-controlled voltage value output to the high-stable crystal oscillator 101 in a large range, and measures the corresponding frequency value of the high-stable crystal oscillator 101 through the internal travel time counter, thereby obtaining the corresponding high-stable crystal oscillator 101 voltage-controlled slope data, and compares it with the voltage-controlled slope parameters of the corresponding model of the high-stable crystal oscillator 101 stored internally. If there is a difference, the "fault" light of the central processor 106 enabling status indication module 109 is lit to remind the user to replace the high-stable crystal oscillator 101, otherwise the "normal" indicator light will be lit.

[0069] Based on the traditional atomic clock technology solution, the locking signal used by the atomic clock to determine whether the closed-loop is locked is led back to the central processor 106 for monitoring. Then, the locking signal that may appear during the closed-loop locking process of the entire onboard clock system 100 is as follows: Figure 7 shown.

[0070] like Figure 7 , the sampling sequence is generated by the central processor 106, and the other four curves are all locking signals, which are collected by the central processor 106. Specifically, the basis for judging the failure of the spectrum lamp 113 in the double-bubble physical system 107 is: when the spectrum lamp 113 is working, the atoms and the trace impurity elements in the bulb and on the bulb wall have chemical and physical effects, which can gradually reduce the number of atoms in the bulb. After long-term work, the atoms are exhausted. Once this happens, it means that the bulb has reached the end of its life and needs to be replaced to continue working. The life of the bulb of a general atomic clock is about 10,000-30,000 hours. Due to the loss of elements, Figure 3 The locking signal amplitude will decrease significantly; when there is a special fault, the spectrum lamp does not work (does not light up), the locking signal will decrease sharply, and the central processor will enable the "fault" light in the status indication module to light up. At this time, the user needs to replace the spectrum lamp according to the prompt, otherwise the "normal" light will light up.

[0071] Specifically, the basis for judging the failure of the integrated filter resonance bubble in the double-bubble physical system 107 is: according to the traditional atomic clock technology, the inert gas filled in the integrated filter resonance bubble collides to produce frequency shift to change the atomic ground state 0-0 transition center frequency, so that it is suitable for the peripheral electronic circuit. This requires very accurate pressure numbers of the inert gas filled, and in fact, the pressure numbers often become the key to the accuracy of the atomic clock. Under normal circumstances, the pressure numbers cannot be very accurate. In traditional technology, magnetic fields are used to compensate, but magnetic fields can only increase the frequency value of the integrated filter resonance bubble system, and cannot reduce its frequency value. In this way, the integrated filter resonance bubble of the atomic clock works in a constant temperature environment of 600C-700C for a long time. When the pumping light passes through, the internal atoms continuously undergo physical effects such as resonance and collision. After such long-term operation, it is possible to change the frequency of the integrated filter resonance bubble, thereby making it impossible for the atomic clock to achieve normal closed-loop locking. In this patent, the integrated filter resonance bubble is placed together with the above-mentioned photodetector, magnetic field, magnetic screen, etc. in the microwave cavity as a replaceable module, so the failure of closed-loop locking here should include the possible failure of the integrated filter resonance bubble frequency change, microwave cavity frequency change, and even the magnetic field causing the atom not to split. When the failure occurs, it can be seen as follows Figure 7 The CPU will then light up the "Fault" light in the enable status indicator module, otherwise it will light up the "Normal" light. When the "Fault" light is on, the user first needs to power on the double-bubble physical system again. If the phenomenon persists, the user needs to replace the integrated filter resonance bubble.

[0072] like Figure 8In the embodiment of the present application, the ground base station system 200 includes: a crystal oscillator module 201, a temperature compensation module 202, a control module 203, a frequency selection amplification module 204, a signal shaping module 205, a quantum module 206, a long stability module 207, a short stability module 208, an isolation amplifier 209, a DDS frequency division module 210, a phase detector 211, a GPS receiver 212, a loop filter module 213 and a GPS antenna 214, wherein the crystal oscillator module 201 is respectively connected to the temperature compensation module 202, the control module 203 and the frequency selection amplification module 204, the temperature compensation module 202 is connected to the control module 203, and the control module 2 03 is connected to the quantum module 206, the frequency selection amplification module 204 is connected to the signal shaping module 205, the signal shaping module 205 is connected to the isolation amplifier 209, the long-stable module 207 and the short-stable module 208 are respectively connected to the quantum module 206 and the isolation amplifier 209, the DDS frequency division module 210 is respectively connected to the isolation amplifier 209 and the phase detector 211, the phase detector 211 is respectively connected to the GPS receiver 212 and the loop filter module 213, the GPS receiver 212 is connected to the GPS antenna 214, and the loop filter module 213 is connected to the crystal oscillator module 201.

[0073] In the embodiment of the present application, the crystal oscillator module 201 generates an oscillation signal, and the oscillation signal passes through the frequency selection amplifier module 204 and the signal shaping module 205 to obtain a 10MHz frequency signal, which is output to the quantum module 206, the DDS frequency division module 210 and external use through the isolation amplifier 209. The GPS receiver 212 receives the frequency signal from the GPS antenna 214 to obtain a 10KHz frequency signal, which is divided by 1 / 1000 of the DDS frequency division module 210 together with the 10MHz frequency signal generated in the crystal oscillator module 201 to obtain a 10KHz frequency signal, which is phase-detected with the 10KHz frequency signal generated by the GPS receiver 212. The phase detector 211 compares the phase difference between the input signal received by the GPS receiver 212 and the output signal of the crystal oscillator module 201, thereby generating a GPS correction signal, and can adjust the frequency of the crystal oscillator module 201 so that the frequency and phase of the crystal oscillator module 201 maintain a certain relationship with the input signal received by the GPS receiver 212. When the frequency of the output signal of the crystal oscillator module 201 (ie, the crystal oscillator) and the input signal received by the GPS receiver 212 are equal, their instantaneous phase difference is a constant; otherwise, if their instantaneous phase difference is a constant, the input signal and the output signal have the same frequency.

[0074] In the embodiment of the present application, after the 10MHz of the crystal oscillator module 201 is sent to the quantum module 206, it needs to be multiplied, integrated and microwave mixed to obtain the atomic clock atomic ground state 0-0 transition frequency and act on the atom. After the frequency discrimination of the quantum module 206, a quantum entanglement signal is obtained to determine whether the microwave frequency at this moment is aligned with the atomic ground state 0-0 transition frequency, and the control module 203 controls the voltage-controlled voltage to act on the crystal oscillator module 201 to produce quantum correction. Another temperature compensation module 202 is mainly for the peripheral components of the crystal oscillator module 201. The peripheral temperature change is sensed by the bridge thermistor. When the working environment temperature of the components changes, the error voltage-controlled voltage generated by the bridge is used to compensate for the frequency influence on the crystal oscillator module 201 caused by the temperature. The specific working principle of the temperature compensation module 202 is described in detail in the subsequent steps.

[0075] like Fig. 9 In the embodiment of the present application, the crystal oscillator module 201 includes: a crystal oscillator, a thermistor R3, a varactor D1, a varactor D2 and a varactor D3, wherein the oscillator is connected to the thermistor R3, and the crystal oscillator is respectively connected to the resistor R1, the cathode of the varactor D1, the cathode of the varactor D2 and the cathode of the varactor D3.

[0076] In the embodiment of the present application, the crystal oscillator module 201 is composed of a thermistor R3, varactor diodes D1, D2, D3 and a crystal oscillator. When the temperature is controlled to be constant, the resistance of the thermistor R3 and the equivalent series capacitance of the crystal oscillator change accordingly, thereby offsetting or reducing the temperature drift of the oscillation frequency. The signal generated by the GPS receiver 212 and the signal generated by the crystal oscillator module 201 pass through the phase detector 211 to obtain the GPS correction signal, that is, the voltage-controlled voltage 1 acts on the varactor diode D1 connected in series with the crystal oscillator, and the nonlinear frequency drift of the crystal oscillator is compensated by the change of the series capacitance of the crystal oscillator.

[0077] like Fig.10: is a circuit diagram of the temperature compensation module 202, the temperature compensation module 202 includes: a resistor R4, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a thermistor Rm, a thermistor Rn, a voltage follower A1, a voltage follower A2 and a voltage follower A3, wherein a first end of the resistor R4 is connected to a Ucc signal end and a second end is connected to a positive input end of the voltage follower A1, a first end of the resistor R5 is connected to the Ucc signal end and a second end is connected to the positive input end of the voltage follower A2, a first end of the thermistor Rm is connected to the positive input end of the voltage follower A1 and a second end is grounded, a first end of the thermistor Rn is connected to the positive input end of the voltage follower A2 and a second end is grounded, and a first end of the resistor R6 is connected to The output end of the voltage follower A1 and the second end are connected to the negative input end of the voltage follower A3, the negative input end of the voltage follower A1 is connected to its own output end, the first end of the resistor R7 is connected to the negative input end of the voltage follower A3 and the second end is grounded, the first end of the resistor R8 is connected to the output end of the voltage follower A2 and the second end is connected to the positive input end of the voltage follower A3, the negative input end of the voltage follower A2 is connected to its own output end, the output end of the voltage follower A3 is connected to the Uout signal end, the first end of the resistor R9 is connected to the positive input end of the voltage follower A3 and the second end is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the Uout signal end.

[0078] Specifically, the bridge pressure difference signal in the temperature compensation module 202 reflects the working environment temperature information of the peripheral components of the crystal oscillator module 201. When the bridge pressure difference signal is transmitted to the control module 203, the control module 203 processes the voltage-controlled voltage 2 to act on the variable capacitance diode D2 connected in series with the crystal oscillator, and the nonlinear frequency drift of the crystal oscillator is compensated by the change of the series capacitance of the crystal oscillator. The quantum correction signal from the quantum module 206 is processed to obtain the voltage-controlled voltage 3 to act on the variable capacitance diode D3 connected in series with the crystal oscillator, and the output 10MHz signal frequency of the crystal oscillator is corrected by the change of the series capacitance of the crystal oscillator.

[0079] like Fig.10 Furthermore, the temperature compensation module 202 also includes: a voltage follower A4, wherein the positive input terminal of the voltage follower A4 is grounded and the negative input terminal is connected to the second end of the resistor R11, and the output terminal of the voltage follower A4 is connected to the second end of the resistor R9.

[0080] Specifically, the bridge temperature measurement circuit in the temperature compensation module 202 is mainly composed of two resistors R4 and R5 with the same resistance value, a thermistor Rm with a preset temperature value, and a thermistor Rn. When the working environment temperature of the semiconductor component is constant, that is, the measured value of the thermistor Rn is equal to the thermistor sensor Rm with a preset temperature value, the output voltage difference between the A and B ends of the resistance bridge will be 0, and the entire temperature compensation output end Uout will output 0. When the working environment temperature of the semiconductor component changes, a certain voltage difference is formed between the A and B ends of the bridge, which is transmitted to the voltage follower A3 through the transmission of the voltage followers A1 and A2 for differential amplification. Considering that the amplified voltage difference can be effectively collected, a voltage follower A4 is added to the output end of the voltage follower A3 to play a role in gain linear adjustment. The obtained temperature compensation voltage difference Uout is sent to the control module 203 for processing, and the voltage-controlled voltage 2 is obtained to act on the variable capacitance diode D2 connected in series with the crystal oscillator. Through the change of the series capacitance of the crystal oscillator, the nonlinear frequency drift of the crystal oscillator is compensated.

[0081] In the embodiment of the present application, the reference frequency signal of the DDS frequency division module 210 can use the frequency signal generated by the crystal oscillator module itself. The phase detector 211 uses the 74HCT9046AIC of Philips that includes the current-type phase detector 211. Its circuit design makes it difficult for the input and output characteristics of the phase detector 211 to have a dead zone, and a high-precision PLL can be formed. The GPS receiver 212 uses the high-precision, low-power Jupiter12 series TU35-D410-021GPS module of NAVMAN, which has an integrated LNA and supports active and passive antennas. The module provides a 10KHz frequency output synchronized with the 1PPS signal, and the time accuracy is better than 100ns.

[0082] like Fig.11 The ground base station system 200 also includes: a time correction module 215, a voltage-controlled correction module 216 and a servo module 217, wherein the crystal oscillator module 201 is respectively connected to the time correction module 215 and the voltage-controlled correction module 216, the voltage-controlled correction module 216 is connected to the servo module 217, the servo module 217 is respectively connected to the time correction module 215 and the quantum module 206, and the time correction module 215 is connected to the GPS receiver 212.

[0083] Specifically, the GPS receiver 212 receives the signal sent by the GPS satellite, obtains the second pulse signal after conversion and sends it to the time correction module 215, counts the frequency signal output by the crystal oscillator module 201 within one cycle of the second pulse and obtains the corresponding correction value and sends it to the servo module 217, and outputs the corresponding DC correction voltage through the voltage control correction module 216 to act on the crystal oscillator module 201. The corresponding timing is as follows Fig.12 As shown (the crystal oscillator module 201 is also known as the VCXO in the figure).

[0084] like Fig.12 When the GPS second pulse gate signal (width is T) is at a high level, after t1 time, the rising edge of the first pulse of the frequency signal of the crystal oscillator module 201 makes the counter enable end effective, and the crystal oscillator module 201 starts counting the frequency signal. When the GPS second pulse gate reaches a low level after T seconds, the crystal oscillator module 201 does not stop counting. After t2 time, the counter is turned off when the rising edge of the frequency signal of the crystal oscillator module 201 that comes later arrives. Here, the time width of the enable signal (actual gate signal) is exactly equal to the number of complete cycles (N) of the frequency signal of the crystal oscillator module 201. According to the above-mentioned related parameters: T, t1, t2, N, according to the traditional GPS time difference comparison technology, the servo module 217 can obtain the corresponding correction value of the frequency signal of the crystal oscillator module 201, and output the corresponding DC correction voltage through the voltage-controlled correction module 216 to act on the crystal oscillator module 201.

[0085] like Fig.13 In an embodiment of the present application, the ground base station system 200 also includes: a timer 218 and a delay array module 219, wherein the timer 218 is connected to the crystal oscillator module 201 and the servo module 217, and the delay array module 219 is respectively connected to the timer 218, the DDS frequency division module 210 and the servo module 217.

[0086] like Fig.13 In the embodiment of the present application, it is also necessary to improve the short-term frequency stability of the atomic clock, and the signal obtained by the crystal oscillator module 201 after the DDS frequency division module 210, the local reference source, and the GPS second pulse are all sent to the delay array module 219. Here, the local reference source usually selects a high-stability H clock source, and its output signal frequency is usually 10MHz. The frequency of the crystal oscillator module 201 selected in the present application is also 10MHz, and a 1MHz frequency signal is obtained after the DDS frequency division module 210 divides the frequency.

[0087] like Fig.14In the embodiment of the present application, the delay array module 219 includes: a first counter 2191, a second counter 2192, and a NOT gate array 2193, wherein the first counter 2191 and the second counter 2192 are connected to the servo module 217 and the NOT gate array 2193, respectively. The timing corresponding to the delay array module 219 is as follows Fig.15 As shown (the crystal oscillator module 201 is also known as the VCXO in the figure).

[0088] like Fig.15 When the preset GPS second pulse gate signal (width is T=1 second) arrives at a high level, the rising edge of the first pulse of the frequency division signal of the crystal oscillator module 201 makes the enable terminals of the first counter 2191 and the second counter 2192 valid, and counts the frequency division signal of the crystal oscillator module 201 and the local reference signal respectively. When the preset GPS second pulse gate signal arrives at a high level again after T seconds, the first counter 2191 and the second counter 2192 do not stop counting at this time, and wait until the rising edge of the frequency division signal of the crystal oscillator module 201 that arrives later arrives, and the two counters are closed at the same time. Here, the time width of the enable signal (actual gate signal) is exactly equal to the number of complete cycles of the frequency division signal of the crystal oscillator module 201.

[0089] Furthermore, assuming that the frequency of the frequency division signal of the crystal oscillator module 201 is Fx, and the frequency of the local reference source signal is fo, within the gate time T, the first counter 2191 and the second counter 2192 count the frequency division signal of the crystal oscillator module 201 and the local reference source signal respectively as N1 and N2, then:

[0090]

[0091] From equation (1), it can be seen that the frequency fx of the frequency division signal of the crystal oscillator module 201 is related to the local reference source frequency fo and the count values ​​N1 and N2 of the two counters. It should be noted that Fig.15 Since the frequency division signal of the crystal oscillator module 201 and the local reference signal have different frequencies, their phases cannot overlap and be equal at points A and B. Fig.15 Zooming in on A and B in the figure gives Fig.16 Schematic diagram of the measurement of the crystal oscillator module 201 (ie, VCXO in the figure).

[0092] like Fig.16, when the gate signal trigger edge pulse of the GPS second pulse arrives, wait for the next rising edge of the local reference signal, at this moment enable the corresponding counter to perform "start counting" and "end counting" operations at point A and point B. From ,15, it can be seen that there is a time difference △t1, △t2 between enabling the counter at time points A and B and the arrival of the next edge pulse of the local reference signal. The specific difference depends on the phase difference between the local reference signal and the local reference signal at time A or time B, and its size is not a constant fixed phase difference relationship, which will lead to different errors in each sampling. For those high-stability, high-frequency clock frequency sources, it is necessary to further improve the measurement method to determine the △t1, △t2 values ​​to improve the measurement accuracy. At this time, the present application adopts the following solution: according to Fig.14 The frequency division signal of the crystal oscillator module 201 and the local reference signal are also sent to the NOT gate array 2193. The NOT gate array 2193 is provided with N levels (N is an even number) of NOT gates and an AND gate. It should be noted that these NOT gates and AND gates are simulated by the internal FPGA chip. Fig.16 When the A moment in the figure arrives, the frequency division signal of the crystal oscillator module 201 will pass through 2 NOT gates, 4 NOT gates, 6 NOT gates...N NOT gates of the NOT gate array 2193, and then pass through an AND gate with the local reference source signal. Fig.17 As shown (the crystal oscillator module 201 is also known as the VCXO in the figure).

[0093] refer to Fig.16 and Fig.17 It can be known that: Fig.16 When time A or B arrives, Fig.17 The AND gate in the state 1 detection module will be recognized as "1" only after the "AND" operation when the local reference signal reaches a high level: for example Fig.16 When the A moment in the figure arrives, since the frequency division signal of the crystal oscillator module 201 is at a high level (i.e., "1" state), after 6 (N=6) Fig.17 After the delay of the logical "NOT" gate in the local reference source signal, the high level of the local reference source signal comes, making the corresponding "AND" gate operation "1", while the previous "AND" gate operations in N = 2 and N = 4 are all "0". Fig.17 The state "1" detection module in the corresponding "AND" gate operation is 1, and the N value can be obtained. Fig.16 The size of △t in . Similarly, the size of △t2 can also be obtained.

[0094] With the above-obtained △t1 and △t2, combined with formula (1), according to the prior art, the frequency correction value of the frequency division signal of the crystal oscillator module 201 can be accurately measured and obtained, and Fig.11The voltage control correction module 216 in the circuit outputs a corresponding DC voltage to act on the crystal oscillation module 201 .

[0095] like Fig.18 In an embodiment of the present application, the ground base station system 200 also includes: a temperature control module 220 and a phase accumulation module 221, wherein the crystal oscillator module 201 is respectively connected to the DDS frequency division module 210 and the temperature control module 220, and the phase accumulation module 221 is respectively connected to the DDS frequency division module 210, the GPS receiver 212 and the servo module 217.

[0096] according to Fig.18 The GPS receiver 212 obtains the signal sent by the GPS satellite and converts it to obtain the second pulse signal f0, which is sent to the phase accumulation module 221. The 1KHz synchronization reference signal f1 generated based on the GPS second pulse signal is also sent to the phase accumulation module 221. At the same time, the output signal of the crystal oscillator module 201 is obtained by the DDS frequency division module 210 to obtain f2 and sent to the phase accumulation module 221. Here, the present application sets the frequency division ratio of the DDS frequency division module 210 (see the specific frequency division circuit for details). Figure 2 ), the ultimate goal is to make the divided signal frequency consistent with the synchronization reference signal f1 frequency, that is, f2 = 1KHz.

[0097] The present application hopes that in theory f1=f2, so that the detection of the same frequency but different phases can be realized to improve the detection accuracy of the present application. However, in practice, it is impossible to make the two completely identical, for example, f1=1.0012KHz, f2=1.0023KHz. To solve this problem, the present application sets a phase accumulation module 221 Figure 2 The DDS frequency division circuit shown is used to make the values ​​of f1 and f2 as close as possible:

[0098] like Fig.19 In the embodiment of the present application, the phase accumulation module 221 includes: an isolation amplification unit 2211, a DDS processing module 2212, a low-pass filtering module 2213, a travel time counter 2214, a latch 2215 and a single-chip microcomputer 2216, wherein the isolation amplification unit 2211 is respectively connected to the DDS processing module 2212 and the travel time counter 2214, the single-chip microcomputer 2216 is respectively connected to the latch 2215 and the DDS processing module 2212, the DDS processing module 2212 is connected to the low-pass filtering module 2213, and the travel time counter 2214 is connected to the latch 2215.

[0099] In the embodiment of the present application, the measured frequency signal fx (f1 or f2) is sent to the travel time counter 2214 and the DDS processing module 2212 respectively after passing through the isolation amplifier unit 2211, wherein the signal is sent to the travel time counter 2214 for coarse frequency measurement, and the single chip microcomputer 2216 reads the value sampled by the latch 2215 on the travel time counter 2214 and records the frequency value at this time, so as to obtain the coarse frequency value F of the measured signal. The measured signal passing through the isolation amplifier unit 2211 on the other side is sent to the external clock input end of the DDS processing module 2212 as the reference clock when the DDS processing module 2212 is working. At the same time, the external communication port of the DDS processing module 2212 is connected to the single chip microcomputer 2216, and the single chip microcomputer 2216 obtains the frequency division value for communication with the DDS processing module 2212 according to the existing DDS processing technology calculation formula (the model of the DDS processing module 2212 used here is AD9852, which has a 48-bit frequency control word register): Among them, F is the rough frequency value of the measured signal obtained by counting the time counter 2214 and calculating the single-chip microcomputer 2216. f is 1KHz, and the specific frequency division value obtained is written into the buffer area of ​​the DDS processing module 2212 through the serial communication timing. After DDS processing, a 1KHz frequency signal is obtained, and the obtained frequency signal is sent to the low-pass filter module 2213 to obtain the final 1KHz frequency signal output. Fig.19 After circuit processing, theoretically f1=f2=1KHz.

[0100] like Fig. 20 is a timing diagram of the phase accumulation module 221. Specifically, when the GPS second pulse gate signal f0 (width is T=1 second) is at a high level, after t1 time, the rising edge of the first pulse of the frequency division signal f2 (1KHz) of the crystal oscillator module 201 makes the phase accumulation effective, and the phase difference accumulation calculation between the reference signal f1 and the frequency division signal of the crystal oscillator module 201 begins. When the GPS second pulse gate high level comes again after T seconds, after t2 time, when the rising edge of the frequency signal of the crystal oscillator module 201 that comes later arrives, the phase difference accumulation calculation process between the reference signal f1 and the frequency division signal of the crystal oscillator module 201 continues, and Fig.18 The servo module 217 in the circuit has been recording the specific value Δφ of the phase difference between the reference signal f1 and the frequency division signal f2 of the crystal oscillator module 201. Only at this moment, the information of Δφ is determined by the servo module 217. Here, the time width of the enable signal (actual gate signal) is exactly equal to the number of complete cycles (N) of the frequency signal of the crystal oscillator module 201.

[0101] Fig. 20The frequency of the GPS second pulse f0 in the figure is 1Hz, that is, T = 1 second. From the above principle, it can be seen that the phase difference Δφ between f1 and f2 is only performed once at every T = 1 second interval. After M times of sampling at T = 1 second, when Δφ = 0, the servo module 217 uses the phase difference data obtained in the M*T time to obtain the corresponding frequency difference Δf of the f1 and f2 signals according to the traditional "phase difference-frequency difference" conversion theory. The servo module 217 will Fig.18 The “voltage control slope” relationship of the crystal oscillator module 201 in the embodiment converts Δf into ΔV (DC bias correction voltage value) to enable the voltage control correction module 216 to work on the crystal oscillator module 201 .

[0102] like Fig.21 : is a circuit diagram of the temperature control module 220, the temperature control module 220 includes: a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor Rw, a thermistor Ra, a thermistor Rb, a voltage follower A, a voltage source and a heating coil loop, wherein the first end of the resistor R12 is grounded and the second end is connected to the first end of the resistor R15, the first end of the resistor R13 is grounded and the second end is connected to the first end of the resistor R14, the second end of the resistor R14 is connected to the positive input end of the voltage follower A, and the second end of the resistor R15 is connected to the negative input end of the voltage follower A. end, the first end of the resistor R16 is connected to the positive input end of the voltage follower A and the second end is grounded, the first end of the resistor Rw is connected to the negative input end of the voltage follower A and the second end is connected to the output end of the voltage follower A, the output end of the voltage follower A is connected to the first end of the heating coil loop, the second end of the heating coil loop is connected to the first end of the voltage source, the first end of the thermistor Ra is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R15, the first end of the thermistor Rb is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R14.

[0103] Specifically, the temperature control module 220 can set the temperature value T of the crystal oscillator module 201 under the control of the control module 203. Specifically, the control module 203 can set the working environment temperature corresponding to the crystal oscillator module 201 and obtain the actual working environment temperature information. Resistor R12, resistor R13 and sensitive resistor Rb are resistors with the same temperature coefficient, and their resistance values ​​should be selected to be equivalent to the thermistor Ra. Here, the value of resistor Rb reflects the actual working environment temperature T. The thermistor Ra is attached to the surface of the temperature control module 120 to sense the actual working environment temperature T. Therefore, when the working environment temperature T does not change, Fig.21The bridge in the circuit is in balance, and the temperature compensation voltage value transmitted to the heating coil loop is 0. Once the working environment temperature T changes, the resistance value of the thermistor Ra will decrease (temperature rises) or increase (temperature drops), and then there will be a voltage difference between the two ends of the bridge, which is converted into a temperature compensation voltage after differential amplification by the operational amplifier A and transmitted to the voltage source, and output to the traditional heating wire coil loop at the same time. The amplification gain of the entire circuit is adjusted by the negative feedback resistor Rw of the operational amplifier A. The resistor Rw is a digital potentiometer. The above circuit compensation factor change function is achieved by adjusting the resistance value of the resistor Rw.

[0104] In the embodiment of the present application, the ground-to-space timing system 300 is a prior art and is not elaborated in detail in the present application. In short, the ground-to-space timing system 300 is used for communication between the satellite-borne clock system 100 and the ground base station system 200. For example, the ground-to-space timing system 300 can be a communication satellite or a satellite base station, etc.

[0105] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The above is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. The various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features applied for herein.

[0106] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A ground base station system, characterized in that: include: A crystal oscillator module, a temperature compensation module, a control module, a frequency-selective amplification module, a signal shaping module, a quantum module, a long-stable module, a short-stable module, an isolation amplifier, a DDS frequency-dividing module, a phase detector, a GPS receiver, a loop filter module and a GPS antenna, wherein the crystal oscillator module is respectively connected to the temperature compensation module, the control module and the frequency-selective amplification module, the temperature compensation module is connected to the control module, the control module is connected to the quantum module, the frequency-selective amplification module is connected to the signal shaping module parts, the signal shaping module is connected to the isolation amplifier, the long-stable module and the short-stable module are respectively connected to the quantum module and the isolation amplifier, the DDS frequency-dividing module is respectively connected to the isolation amplifier and the phase detector, the phase detector is respectively connected to the GPS receiver and the loop filter module, the GPS receiver is connected to the GPS antenna, and the loop filter module is connected to the crystal oscillator module; The crystal oscillator module includes: a crystal oscillator, a thermistor R3, a varactor diode D1, a varactor diode D2 and a varactor diode D3, wherein the crystal oscillator is connected to the thermistor R3, the cathode of the varactor diode D1, the cathode of the varactor diode D2 and the cathode of the varactor diode D3 respectively; The temperature compensation module includes: resistor R4, resistor R5, resistor R6, resistor R7, resistor R8, resistor R9, resistor R10, resistor R11, thermistor Rm, thermistor Rn, voltage follower A1, voltage follower A2 and voltage follower A3, wherein the first end of the resistor R4 is connected to the Ucc signal end and the second end is connected to the positive input end of the voltage follower A1, the first end of the resistor R5 is connected to the Ucc signal end and the second end is connected to the positive input end of the voltage follower A2, the first end of the thermistor Rm is connected to the positive input end of the voltage follower A1 and the second end is grounded, the first end of the thermistor Rn is connected to the positive input end of the voltage follower A2 and the second end is grounded, the first end of the resistor R6 is connected to the voltage follower A1 The first end of the resistor R7 is connected to the negative input end of the voltage follower A3 and the second end is connected to the output end of the voltage follower A3, the negative input end of the voltage follower A1 is connected to its own output end, the first end of the resistor R7 is connected to the negative input end of the voltage follower A3 and the second end is grounded, the first end of the resistor R8 is connected to the output end of the voltage follower A2 and the second end is connected to the positive input end of the voltage follower A3, the negative input end of the voltage follower A2 is connected to its own output end, the output end of the voltage follower A3 is connected to the Uout signal end, the first end of the resistor R9 is connected to the positive input end of the voltage follower A3 and the second end is connected to the first end of the resistor R11, the second end of the resistor R11 is connected to the first end of the resistor R10, and the second end of the resistor R10 is connected to the Uout signal end; The temperature compensation module further includes: a voltage follower A4, a positive input terminal of the voltage follower A4 is grounded and a negative input terminal is connected to the second end of the resistor R11, and an output terminal of the voltage follower A4 is connected to the second end of the resistor R9.

2. The ground base station system according to claim 1, characterized in that: The ground base station system also includes: a time correction module, a voltage-controlled correction module and a servo module, wherein the crystal oscillator module is respectively connected to the time correction module and the voltage-controlled correction module, the voltage-controlled correction module is connected to the servo module, the servo module is respectively connected to the time correction module and the quantum module, and the time correction module is connected to the GPS receiver.

3. The ground base station system according to claim 2, characterized in that: The ground base station system also includes: a timer and a delay array module, wherein the timer is connected to the crystal oscillator module and the servo module, and the delay array module is respectively connected to the timer, the DDS frequency division module and the servo module.

4. The ground base station system according to claim 3, characterized in that: The delay array module includes: a first counter, a second counter and a NOT gate array, wherein the first counter and the second counter are connected to the servo module and the NOT gate array respectively.

5. The ground base station system according to claim 2, characterized in that: The ground base station system also includes: a temperature control module and a phase accumulation module, wherein the crystal oscillator module is respectively connected to the DDS frequency division module and the temperature control module, and the phase accumulation module is respectively connected to the DDS frequency division module, the GPS receiver and the servo module.

6. The ground base station system according to claim 5, characterized in that: The phase accumulation module includes: an isolation amplifier unit, a DDS processing module, a low-pass filtering module, a travel time counter, a latch and a single-chip microcomputer, wherein the isolation amplifier unit is respectively connected to the DDS processing module and the travel time counter, the single-chip microcomputer is respectively connected to the latch and the DDS processing module, the DDS processing module is connected to the low-pass filtering module, and the travel time counter is connected to the latch.

7. The ground base station system according to claim 6, characterized in that: The temperature control module includes: a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor Rw, a thermistor Ra, a thermistor Rb, a voltage follower A, a voltage source and a heating coil loop, wherein the first end of the resistor R12 is grounded and the second end is connected to the first end of the resistor R15, the first end of the resistor R13 is grounded and the second end is connected to the first end of the resistor R14, the second end of the resistor R14 is connected to the positive input end of the voltage follower A, the second end of the resistor R15 is connected to the negative input end of the voltage follower A, and the resistor R1 6 is connected to the positive input terminal of the voltage follower A and the second end is grounded, the first end of the resistor Rw is connected to the negative input terminal of the voltage follower A and the second end is connected to the output terminal of the voltage follower A, the output terminal of the voltage follower A is connected to the first end of the heating coil loop, the second end of the heating coil loop is connected to the first end of the voltage source, the first end of the thermistor Ra is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R15, the first end of the thermistor Rb is connected to the second end of the voltage source and the second end is connected to the first end of the resistor R14.

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