On-chip transformer and manufacturing process thereof

Abstract

An on-chip transformer includes a primary coil and a secondary coil, each of which includes multiple metal layers; all metal layers are stacked in the height direction of the primary coil and the secondary coil; each metal layer includes a plurality of independent metal rings with the same structure; the metal rings are configured as a spiral structure diffused from the inside to the outside; the top metal layer in the primary coil is provided with N input terminals; the top metal layer in the secondary coil has (N+1) output terminals, where N is an integer; the signal enters through the input terminal and then outputs from the output terminal. The present invention also proposes a manufacturing process for preparing the above-mentioned on-chip transformer. The present invention has a large coupling area and a small occupied area, and is also suitable for half-bridge or full-bridge DC-DC converters, and can achieve output of any proportion by adjusting the voltage by boosting, bucking or equalizing, balancing the resistance and reducing the parasitic effects in the coil.

Description

Technical Field

[0001] The present invention belongs to the technical field of Buck-type DCDC converters, and in particular relates to an on-chip transformer with three-terminal output and a manufacturing process thereof. The on-chip transformer is mainly used in a bridge-type isolated DC-DC converter. Background Art

[0002] With the development of electronic products, the demand for portable mobile devices is growing, and the competition among manufacturers is becoming increasingly fierce, which has prompted the reduction of the size and weight of electronic systems. In these electronic devices, the power supply part has become the main factor affecting the size and weight of electronic equipment due to the presence of magnetic components such as inductors and transformers. The advent of on-chip transformers has greatly reduced the area and weight of transformers, and therefore has been widely used. The half-bridge isolated DC-DC converter and the full-bridge isolated DC-DC converter are widely used in a variety of power supply systems because they have the advantages of bidirectional excitation transformers, few switches, large output power, a wide output power range, low cost and high reliability.

[0003] In the existing technology, GaN materials are considered to meet the development requirements of new power devices and have quickly become a research hotspot because of their excellent properties such as large bandgap, high saturated electron mobility, small dielectric constant, good thermal conductivity, high temperature resistance and corrosion resistance.

[0004] Existing on-chip transformers generally use a cross-coupling structure between metals on the same layer, that is, the primary coil and the secondary coil are arranged in the same layer at intervals, such as the on-chip transformer balun in China's public patent CN107293393A and an on-chip transformer in CN104103636A. This type of on-chip transformer has a small coupling area and a large occupied area, and is not suitable for half-bridge or full-bridge DC-DC converters at the same time. In addition, this type of structure is an asymmetric tapped transformer, and due to the different lengths of the secondary coils, it is impossible to accurately achieve a 1:1 conversion of the coil turns ratio.

[0005] China's public patent CN108269677A on-chip transformer proposes an octagonal structure on-chip transformer, in which each metal layer is composed of multiple concentric octagonal circles of different diameters and closed, which are overlapped and circulated through connectors set in different circles; this structure not only leads to a large number of connectors, affecting signal transmission, but also makes it impossible to transmit signals continuously and unimpeded at one time. Moreover, the on-chip transformer of this structure is not completely overlapped in the direction perpendicular to the X-axis, and the coupling area cannot be maximized; at the same time, the structural lengths in the primary coil and the secondary coil are different, and the coil turns ratio cannot be converted to 1:1.

[0006] Therefore, how to design an on-chip transformer and combine it with GaN-based technology to obtain a DC-DC converter suitable for half-bridge or full-bridge, achieve output of any proportion by adjusting the voltage by boosting, bucking or equalizing, balance the resistance and reduce the parasitic effects in the coil, and accurately achieve a transformer with a coil turns ratio of 1:1 output, is the key to improving the performance, conversion efficiency and operating frequency of the power management system, and obtaining power devices with good performance, miniaturization and low consumption. Summary of the invention

[0007] The present invention provides an on-chip transformer and a manufacturing process thereof, which is particularly suitable for a half-bridge or full-bridge DC-DC converter, and solves the technical problems in the prior art of poor coupling efficiency and high parasitic effect leading to poor inductance storage capacity.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] An on-chip transformer comprises a primary coil and a secondary coil disposed on the same side of a substrate layer, wherein the primary coil and the secondary coil both comprise multiple metal layers;

[0010] All the metal layers are stacked and arranged along the height direction of the primary coil and the secondary coil;

[0011] Each of the metal layers comprises a plurality of independent metal rings with the same structure;

[0012] The metal ring is configured as a spiral structure that spreads from the inside to the outside;

[0013] The uppermost metal layer in the primary coil is provided with N input terminals;

[0014] The uppermost metal layer in the secondary coil has (N+1) output terminals, where N is an integer;

[0015] The signal enters through the input end and then is output from the output end.

[0016] Furthermore, all the metal rings in all the metal layers and the metal rings adjacent to and corresponding to them above and below are stacked without misalignment along the height direction of the primary coil and the secondary coil;

[0017] All of the metal rings are annular spiral structures that are diffused from the inside to the outside.

[0018] Furthermore, the number of the metal layers in the primary coil and the secondary coil is the same;

[0019] Preferably, the number of the metal layers in the primary coil and the secondary coil is 2;

[0020] All the metal rings in the same metal layer are arranged in the same row.

[0021] Furthermore, all the metal rings in the uppermost metal layer of the primary coil and the secondary coil are connected to each other via a connecting bridge;

[0022] All the metal rings in the metal layers of the same layer except the top metal layer in the primary coil and the secondary coil are disconnected from each other.

[0023] Furthermore, the number of turns of all the metal coils in the primary coil and the secondary coil is the same;

[0024] The width of each of the metal rings is the same;

[0025] The gap width in each of the metal rings is the same;

[0026] The thicknesses of the metal rings in different layers in the primary coil and the secondary coil are different.

[0027] Further, N is 2;

[0028] The input ends are both arranged in the uppermost metal layer of the primary coil, and are respectively arranged in the outer rings of the two outermost metal rings in the uppermost metal layer of the primary coil.

[0029] Furthermore, all the output terminals are arranged in the topmost metal layer of the secondary coil;

[0030] The two output ends are respectively arranged on the outer rings of the two outermost metal rings in the uppermost metal layer of the secondary coil;

[0031] The other output terminals are arranged on the connecting bridges in the metal ring.

[0032] Furthermore, it is characterized in that the primary coil is arranged close to one side of the substrate layer;

[0033] between the primary coil and the substrate layer, and

[0034] Between all adjacent metal layers in the primary coil and the secondary coil,

[0035] They are all provided with dielectric layers of different structures formed by Si3N4 for isolation.

[0036] Furthermore, the thickness of the dielectric layer disposed between the primary coil and the substrate layer is greater than the thickness of the dielectric layer disposed between adjacent metal layers;

[0037] The thickness of the dielectric layer disposed between the primary coil and the substrate layer is 100-300 um; preferably, the thickness of the dielectric layer disposed between the primary coil and the substrate layer is 100 um.

[0038] Furthermore, the thickness of all the dielectric layers disposed between adjacent metal layers is the same, which is 60-200 nm;

[0039] Preferably, the dielectric layer disposed between adjacent metal layers has a thickness of 60 nm.

[0040] A manufacturing process for preparing an on-chip transformer as described in any one of the above items, comprising the steps of:

[0041] Coating a dielectric layer on the GaN-based substrate layer;

[0042] Then, the primary coil and the secondary coil formed by multiple metal layers are sequentially grown on the dielectric layer, and each of the metal layers is grown on a different layer of the dielectric layer;

[0043] The signal enters from N input terminals arranged on the primary coil and is then output through (N+1) output terminals arranged in the secondary coil, wherein N is an integer.

[0044] Furthermore, all the metal rings in all the metal layers and the metal rings adjacent to and corresponding to them above and below are stacked without misalignment along the height direction of the primary coil and the secondary coil; and

[0045] All the metal rings are annular spiral structures that are diffused from the inside to the outside.

[0046] Further, N is 2, and all the dielectric layers are Si3N4 dielectric layers;

[0047] The number of the metal layers in the primary coil and the secondary coil is the same, which is 2.

[0048] An on-chip transformer and its manufacturing process designed by the present invention have a large coupling area and a small occupied area, and are suitable for half-bridge or full-bridge DC-DC converters. Output of any proportion can be achieved by adjusting the voltage by boosting, bucking or equalizing the voltage, balancing the resistance and reducing the parasitic effect in the coil.

[0049] The lengths of the primary and secondary coils of this structure are the same, and the conversion of the coil turns ratio of 1:1 is accurately achieved. The coupling efficiency is high and the parasitic effect in the coil is small, so that a transformer with a wide frequency range and good parasitic effect can be obtained, and the inductance storage capacity can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a top view of an on-chip transformer according to an embodiment of the present invention;

[0051] Figure 2 is a cross-sectional view of an on-chip transformer along the Y axis according to an embodiment of the present invention;

[0052] Figure 3 is a top view of a metal layer 1 in the production of a primary coil according to an embodiment of the present invention;

[0053] Figure 4 is a top view of the second metal layer in the primary coil of one embodiment of the present invention;

[0054] Figure 5 is an equivalent circuit diagram of an on-chip transformer according to an embodiment of the present invention;

[0055] Figure 6 is a simulation diagram of the inductance values ​​of different ports changing with frequency according to an embodiment of the present invention;

[0056] Figure 7 It is a simulation diagram showing the variation of coupling coefficient and quality factor with frequency according to an embodiment of the present invention.

[0057] In the figure:

[0058] 10, substrate layer 20, dielectric layer 1 30, primary coil

[0059] 31. Metal layer 1 32. Metal layer 2 40. Secondary coil

[0060] 41. Metal layer 3 42. Metal layer 4 50. Dielectric layer 2

[0061] 60, dielectric layer three 70, dielectric layer four 80, connecting bridge DETAILED DESCRIPTION

[0062] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0063] This embodiment provides an on-chip transformer, such as Figure 1As shown, the primary coil 30 and the secondary coil 40 are placed on the same side of the substrate layer 10, and the primary coil 30 is arranged close to the side of the substrate layer 10. Between the primary coil 30 and the substrate layer 10, and between all adjacent metal layers in the primary coil 30 and the secondary coil 40, there are dielectric layers of different structures formed by Si3N4 for isolation. Among them, the primary coil 30 and the secondary coil 40 both include multiple metal layers, and all metal layers are stacked along the height direction of the primary coil 30 and the secondary coil 40, and each metal layer includes a number of independent metal rings with the same structure; all metal rings are configured as a spiral structure diffused from the inside to the outside; and the uppermost metal layer in the primary coil 30 is equipped with N input terminals; the uppermost metal layer in the secondary coil 40 has (N+1) output terminals, wherein N is an integer; the one with more output terminals than input terminals is used as the ground wire of the bridge isolation converter; the signal enters through the input terminal and then outputs from the output terminal.

[0064] Specifically, for Figure 1 The cross-sectional view along the Y axis of the on-chip transformer is shown in FIG. Figure 2 As shown, all metal rings in all metal layers and the metal rings adjacent to and corresponding to them above and below are stacked without misalignment along the height direction of the primary coil 30 and the secondary coil 40; and the metal rings are annular spiral structures that are diffused from the inside to the outside. That is, the primary coil 30 and the secondary coil 40 are both metal rings of annular spiral structures that correspond to each other and overlap and stack, and are connected side by side. The overlapping metal rings can increase the coupling area of ​​the primary coil 30 and the secondary coil 40, and the overall occupied area is small, and the transfer efficiency of the magnetic flux can be increased vertically to each metal layer structure.

[0065] Furthermore, the number of metal layers in the primary coil 30 and the secondary coil 40 is the same, both of which are 2; that is, the primary coil 30 includes a metal layer 1 31 and a metal layer 2 32, and the secondary coil 40 includes a metal layer 3 41 and a metal layer 4 42, each metal layer includes the same number of metal rings, and all metal rings in the same metal layer are arranged in the same row. All metal rings are continuous spiral structures that spread outward in a ring shape, and arc-shaped metal wires are used to connect at the connection of each spiral annular metal ring. The connection of the metal wire of the arc structure is a connection angle of an obtuse angle of 120-160° as a turning point, and preferably, the obtuse angle is 150°. Compared with the metal coil of the existing polygonal structure with multiple connection bridges, the arc-shaped structure connection method not only has a gentle bending arc and a slow connection change amplitude, which is beneficial to the balance of resistance, but also can make the parasitic resistance as consistent as possible at the straight line and the inflection point, that is, reduce the parasitic effect of the transformer metal coil; especially when a 150° obtuse-angle metal wire is used to connect the spiral turns at the inflection point in the metal coil, it can further ensure that the metal coil is uniform and annularly diffused outward.

[0066] Furthermore, all metal circles in the top metal layer 2 32 in the primary coil 30 and the top metal layer 4 42 in the secondary coil 40 are connected to each other through the connecting bridge 80; and except for the top metal layer, all metal circles in the other metal layers in the primary coil 30 and the secondary coil 40, that is, the bottom metal layer 1 31 and the bottom metal layer 3 41, are disconnected from each other. And the metal circles on the same side of the primary coil 30 are connected up and down through vias.

[0067] The number of turns of all metal rings in the primary coil 30 and the secondary coil 40 is the same; the width of each metal ring is the same, and the width of the gap in each metal ring is the same. In this embodiment, the inner diameter of all metal rings is 100 μm, the wire width of the metal ring is 20 μm, the width of the gap in each metal wire is 10 μm, and the number of turns of each metal ring is 3.

[0068] The thickness of the primary coil 30 is the same as that of the secondary coil 40, and the thickness of the metal rings of different layers in the primary coil 30 and the secondary coil 40 is different, that is, the thickness of the metal layer 1 31 in the primary coil 30 is less than the thickness of the metal layer 2 32, but the same as the thickness of the metal layer 3 41 in the secondary coil 40; the thickness of the metal layer 3 41 in the secondary coil 40 is less than the thickness of the metal layer 4 42; wherein, the thickness of the metal layer 1 31 and the metal layer 3 41 is the same, and the thickness of the metal layer 2 32 and the metal layer 4 42 is the same, that is, the thickness of all the metal rings in the metal layer 1 31 and the metal layer 3 41 is the same, and the thickness of all the metal rings in the metal layer 2 32 and the metal layer 4 42 is the same. This structure makes the vertical distance between the primary coil 30 and the secondary coil 40 of the transformer overlap, so that the magnetic flux generated by the primary coil 30 can be effectively directly transferred to the secondary coil 40, and at the same time, compared with other types of on-chip transformers, it will save more area and have higher output efficiency.

[0069] In this embodiment, N is preferably 2, that is, there are 2 input terminals and 3 output terminals, wherein the 2 input terminals are A terminal and B terminal, both of which are arranged in the top metal layer 2 32 of the primary coil 30, and are arranged on the leads of the outer rings of the two outermost metal rings in the top metal layer 2 32 of the primary coil 30. The 3 output terminals are C terminal, D terminal and E terminal, all of which are arranged in the top metal layer 4 42 of the secondary coil 40, wherein the two output terminals C terminal and E terminal are arranged on the outer rings of the two outermost metal rings in the top metal layer 4 42 of the secondary coil 40, and are arranged in alignment with the A terminal and the B terminal respectively; the D terminal is arranged on the connecting bridge 80 between the two metal rings, which is arranged as the ground wire of the bridge-type isolation transformer.

[0070] Furthermore, a dielectric layer 20 is provided between the primary coil 30 and the substrate layer 10, that is, the isolation layer between the metal layer 31 and the substrate layer 10 is the dielectric layer 20; at the same time, a dielectric layer 2 50, a dielectric layer 3 60 and a dielectric layer 4 70 are provided as isolation layers between the metal layer 1 31 and the metal layer 2 32, between the metal layer 2 32 and the metal layer 3 41, and between the metal layer 3 and the metal layer 4 42, wherein all the dielectric layers are isolation layers made of Si3N4 material, which isolate the primary coil 30 and the substrate layer 10, the primary coil 30 and the secondary coil 40. The function of the isolation is to allow only AC signals to pass between the primary coil 30 and the secondary coil 40, but no DC signals to pass, thereby realizing the function of a transformer, so that both signals and power can be transmitted between the primary coil 30 and the secondary coil 40, thereby realizing the transmission from electrical signals to magnetic signals and then to electrical signals. That is, the on-chip transformer of this structure can be simultaneously applied to half-bridge or full-bridge DC-DC converters, and can be adjusted by boosting, bucking or isobaric voltage to achieve output of any proportion, balance resistance and reduce parasitic effects in the coil.

[0071] Furthermore, the thickness of the dielectric layer 20 is greater than the thickness of the dielectric layer disposed between adjacent metal layers; this is because the dielectric layer 20 on the substrate layer 10 can prevent the transformer from affecting the substrate layer 10 and reduce the parasitic effect between the transformer and the substrate layer 10. The thicker the dielectric layer 20 is, the stronger the isolation capability is, and the less the parasitic effect is; however, the thickness of the dielectric layer 20 cannot be too thick, otherwise it will affect the performance of other devices on the chip, wherein the thickness of the dielectric layer 20 ranges from 100 to 300 um, and preferably, the thickness of the dielectric layer 20 is 100 um.

[0072] The thickness of all dielectric layers disposed between adjacent metal layers is the same, that is, the thickness of dielectric layer 2 50, dielectric layer 3 60 and dielectric layer 4 70 are all 60-200 nm; preferably, the thickness of dielectric layer 2 50, dielectric layer 3 60 and dielectric layer 4 70 are all 60 nm.

[0073] Among them, for the dielectric layer 2 50, it is grown on the metal layer 1 31, and its thickness is determined according to the size of the applied voltage. In this embodiment, the input voltage is selected to be 48V, and its thickness range is 60-200nm. At the same time, according to the voltage resistance characteristics of the Si3N4 dielectric material, its thickness is selected to be 60nm, which is conducive to the lead-out of the metal ring.

[0074] The dielectric layer three 60 is grown on the metal layer two 32 in order to isolate the primary coil 30 from the secondary coil 40 and allow only the AC signal to pass through the primary coil 30 , thereby improving the performance of the transformer without being broken down. The thickness of the dielectric layer is selected to be 60 nm, which is beneficial to the growth of the metal layer three 41 in the secondary coil 40 .

[0075] The dielectric layer four 70 is used to isolate the metal layer three 41 and the metal layer four 42 in the secondary coil 40 and is conducive to the growth of the metal layer four 42. Preferably, the thickness of the dielectric layer four 70 is 60 nm.

[0076] An on-chip transformer adopts a stacked structure with no misalignment or overlap, and each layer of metal rings is symmetrical with respect to the X-axis. The efficiency of transmitting signals from the metal layer 1 31 in the primary coil 30 to the metal layer 4 42 in the secondary coil 40 is gradually increased, and the resistance and signal losses are reduced. In addition, the on-chip transformer with this structure has very small parasitic resistance during use, which will further reduce the resistance and signal losses and improve the output efficiency.

[0077] There is also an on-chip converter with this structure, which is mainly used in half-bridge and full-bridge isolated DC-DC converters. Compared with the on-chip transformer of the traditional DC-DC converter, it can not only increase the frequency and efficiency, but also greatly reduce the occupied area, improve the coupling efficiency, and improve the efficiency of the DC-DC converter.

[0078] A manufacturing process for preparing the on-chip transformer as described above, comprising the steps of:

[0079] A dielectric layer 20 is coated on the GaN-based substrate layer 10;

[0080] Then, a primary coil 30 and a secondary coil 40 formed of multiple metal layers are sequentially grown on the dielectric layer 1 20, and each metal layer is grown on a different dielectric layer;

[0081] The signal enters from N input terminals provided on the primary coil 30 and is then output through (N+1) output terminals provided in the secondary coil 40 , where N is an integer.

[0082] Furthermore, all the metal rings in all the metal layers and the metal rings adjacent to and corresponding to them above and below are stacked without misalignment along the height direction of the primary coil and the secondary coil; and

[0083] All metal rings are in a ring-shaped spiral structure that spreads from the inside to the outside.

[0084] Further, N is 2, and all dielectric layers are Si3N4 dielectric layers;

[0085] The number of metal layers in the primary coil 30 and the secondary coil 40 is the same, which is two.

[0086] The specific steps are as follows:

[0087] S1. First, a dielectric layer 20 is coated on a GaN-based substrate layer 10.

[0088] The dielectric layer 1 20 can prevent the transformer from affecting the substrate layer 10 and reduce the parasitic effect between the transformer and the substrate layer 10. The thicker the dielectric layer 1 20 is, the stronger the isolation capability is, and the less the parasitic effect is; but the thickness of the dielectric layer 1 20 cannot be too thick, otherwise it will affect the performance of other devices on the chip, wherein the thickness of the dielectric layer 1 20 ranges from 100 to 300 um, and preferably, the thickness of the dielectric layer 1 20 is 100 um.

[0089] S2. Then, grow the metal layer 1 31 of the primary coil 30 on the dielectric layer 1 20 , and grow a dielectric layer 2 50 on the metal layer 1 31 .

[0090] like Figure 3 As shown, the metal layer 1 31 includes two independent metal rings of a spiral structure that are arranged in an annular shape and diffused from the inside to the outside symmetrically along the X-axis, the two metal rings are disconnected, and the number of turns of each metal ring is 3. All metal rings are continuous spiral structures that diffuse outward in an annular shape, and the connection of each spiral annular metal ring is connected by an obtuse angle, and the obtuse angle is 120-160°, preferably, the obtuse angle is 150°. This is because the obtuse angle of 150° is used to connect the annular connection of each spiral diffused outward, which is not only gentle in bending arc and connection change amplitude, but also conducive to resistance balance, and can make the parasitic resistance as consistent as possible at the straight line and the inflection point, that is, to reduce the parasitic effect of the transformer metal coil.

[0091] In order to ensure that the center metal wire of the metal ring in the metal layer 1 31 is led out, a dielectric layer 2 50 is provided on the metal layer 1 31, and the metal layer 1 31 is isolated from the metal layer 2 32, so the thickness of the dielectric layer 2 50 is greater than the thickness of the metal layer 1 31. The dielectric layer 2 50 is grown on the metal layer 1 31, and its thickness is determined according to the magnitude of the applied voltage. In this embodiment, the input voltage is selected to be 48V, and its thickness ranges from 60 to 200nm. At the same time, according to the withstand voltage characteristics of the Si3N4 dielectric material, its thickness is selected to be 60nm, which is conducive to the lead-out of the metal ring.

[0092] S3 , growing a second metal layer 32 on the second dielectric layer 50 , and growing a third dielectric layer 60 on the second metal layer 32 .

[0093] like Figure 4As shown, etching and opening are performed on the dielectric layer 2 50 in sequence, and then a metal layer 2 32 is grown, wherein the metal layer 2 32 also includes two metal rings with the same structure as the metal ring in the metal layer 1 31, and they are respectively overlapped with the metal ring in the metal layer 1 31, and the metal liquid is connected with the metal ring in the metal layer 1 31 through the opening and fills the shape in the etched metal ring to form the metal layer 2 32, and the two adjacent metal rings are connected by a connecting bridge 80, and the connecting bridge 80 is also a structure formed by the solidification of the same metal liquid. Input terminal leads are provided at the outer ring end of the metal layer 2 32, which are respectively the A terminal and the B terminal.

[0094] The dielectric layer three 60 is grown on the metal layer two 32 in order to isolate the primary coil 30 from the secondary coil 40 and allow only the AC signal to pass through the primary coil 30 , thereby improving the performance of the transformer without being broken down. The thickness of the dielectric layer is selected to be 60 nm, which is beneficial to the growth of the metal layer three 41 in the secondary coil 40 .

[0095] S4. Grow a metal layer three 41 on the dielectric layer three 60 , and grow a dielectric layer four 70 on the metal layer three 41 .

[0096] The process of making the primary coil 30 is the same as that of etching and opening holes on the dielectric layer 3 60, and then growing a metal layer 3 41, and the structure of the metal layer 3 41 is the same as that of the metal layer 1 31. Figure 3 The same is omitted here, that is, it includes two independently arranged metal rings, and the metal ring in the metal layer three 41 and the metal ring in the metal layer two 32 are arranged to be stacked up and down.

[0097] A dielectric layer 4 70 is grown on the metal layer 3 41. The dielectric layer 4 70 is used to isolate the metal layer 3 41 and the metal layer 4 42 in the secondary coil 40 and is beneficial to the growth of the metal layer 4 42. Preferably, the thickness of the dielectric layer 4 70 is 60 nm.

[0098] S5. Grow a metal layer 42 on the dielectric layer 470 and set three output terminals on the metal layer 42.

[0099] like Figure 1As shown, etching and opening are performed on the dielectric layer 4 70 in sequence, and then a metal layer 42 is grown. The structure of the metal layer 42 is the same as that of the metal layer 2 32, and it also includes two metal rings. The two metal rings of the metal layer 42 are respectively overlapped with the two metal rings in the metal layer 3 41. The manufacturing process is the same as that of the metal layer 2 32, which is omitted here. The two metal rings in the metal layer 42 are connected by a connecting bridge 80. Output terminal leads are provided at the outer ends of the two metal rings in the metal layer 42, which are the C terminal and the E terminal respectively. At the same time, an output lead of the D terminal is provided on the connecting bridge 80 of the two metal rings in the metal layer 42.

[0100] For the equivalent circuit diagram of the on-chip transformer, Figure 5 As shown, L1 is the inductance value of the A end and the B end of the primary coil 30 , L2 is the inductance value of the C end and the D end of the secondary coil 40 , and L3 is the inductance value of the D end and the E end of the secondary coil 40 .

[0101] The performance parameters of the on-chip transformer obtained by the above-mentioned manufacturing process can be calculated through Z parameter simulation, and the parasitic parameters of the primary coil 30 can be calculated, where imag represents the imaginary part of the Z parameter, real represents the real part of the Z parameter, w represents the angular frequency of the output transformer signal, f represents the frequency of the output signal, and M refers to the mutual inductance of the primary and secondary coils of the transformer. The calculation method is as follows:

[0102] Transformer parasitic resistance: R1 = real (Z 11 )

[0103] The transformer inductance is:

[0104] Transformer mutual inductance: Mutual inductance is:

[0105] Coupling coefficient:

[0106] Quality Factor:

[0107] Through simulation, various parameters of the on-chip transformer of 5-100MHz can be obtained, that is, a simulation diagram of the inductance value of three different ports changing with frequency can be obtained, such as Figure 6 As shown, L1 is the inductance value of the A and B ends of the primary coil 30, L2 is the inductance value of the C and D ends of the secondary coil 40, and L3 is the inductance value of the D and E ends of the secondary coil 40. Simultaneously, the coupling coefficient and quality factor of the on-chip transformer are simulated as a function of frequency, as shown in FIG. Figure 7 As shown, where a is the coupling coefficient K and b is the quality factor Q.

[0108] The on-chip transformer of this structure uses an isolated stacked on-chip transformer, which is formed in a symmetrical way, so the turns ratio can be 1; the maximum quality factor can be 1.9. The quality factor of an inductor indicates the energy storage capacity of the inductor. The higher the quality factor of an inductor, the greater the energy stored in the inductor.

[0109] according to Figure 6 and Figure 7 It can be seen that the on-chip transformer can be used in a relatively wide range, and the higher the frequency, the smaller the parasitic resistance, indicating that the power consumption is also smaller. When the frequency is relatively small, the parasitic inductance is relatively large, indicating that the energy transfer between the primary coil 30 and the secondary coil 40 is increased more. For a general isolated DC-DC converter, it can fully meet the requirements.

[0110] An on-chip transformer and its manufacturing process designed by the present invention have a large coupling area and a small occupied area, and are suitable for half-bridge or full-bridge DC-DC converters. Output of any proportion can be achieved by adjusting the voltage by boosting, bucking or equalizing the voltage, balancing the resistance and reducing the parasitic effect in the coil.

[0111] The lengths of the primary and secondary coils of this structure are the same, and the conversion of the coil turns ratio of 1:1 is accurately achieved. The coupling efficiency is high and the parasitic effect in the coil is small, so that a transformer with a wide frequency range and good parasitic effect can be obtained, and the inductance storage capacity can be improved.

[0112] The above embodiments of the present invention are described in detail, and the contents are only preferred embodiments of the present invention, and cannot be considered to limit the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of application of the present invention should still fall within the scope of the patent coverage of the present invention.

Claims

1. An on-chip transformer, comprising a primary coil and a secondary coil disposed on the same side of a substrate layer, characterized in that: The primary coil and the secondary coil each include multiple metal layers; All the metal layers are stacked and arranged along the height direction of the primary coil and the secondary coil; Each of the metal layers comprises a plurality of independent metal rings with the same structure; The metal ring is configured as a spiral structure that spreads from the inside to the outside; The uppermost metal layer in the primary coil is provided with N input terminals; The uppermost metal layer in the secondary coil has (N+1) output terminals, where N is an integer; The signal enters through the input end and then is output from the output end; All the metal rings in all the metal layers and the metal rings adjacent to and corresponding to them above and below are stacked without misalignment along the height direction of the primary coil and the secondary coil; All of the metal rings are annular spiral structures that are diffused from the inside to the outside; The connection of each spiral ring-shaped metal ring is connected by an arc-shaped metal wire; the connection of the arc-shaped metal wire has an obtuse angle of 120-160° as the inflection point; The number of the metal layers in the primary coil and the secondary coil is the same; All the metal rings in the same metal layer are arranged in the same row; All the metal rings in the uppermost metal layer of the primary coil and the secondary coil are connected to each other via a connecting bridge; All the metal rings in the same metal layers of the primary coil and the secondary coil except the top metal layer are disconnected from each other; The primary coil is arranged close to one side of the substrate layer; between the primary coil and the substrate layer, and Between all adjacent metal layers in the primary coil and the secondary coil, They are all provided with dielectric layers of different structures formed by Si3N4 for isolation; The number of turns of all the metal coils in the primary coil and the secondary coil is the same; The width of each of the metal rings is the same; The gap width in each of the metal rings is the same; The thicknesses of the metal rings in different layers in the primary coil and the secondary coil are different.

2. The on-chip transformer according to claim 1, characterized in that: All the metal rings in the uppermost metal layer of the primary coil and the secondary coil are connected to each other via a connecting bridge; All the metal rings in the metal layers of the same layer except the top metal layer in the primary coil and the secondary coil are disconnected from each other.

3. An on-chip transformer according to any one of claims 1-2, characterized in that: N is 2; The input ends are both arranged in the uppermost metal layer of the primary coil, and are respectively arranged in the outer rings of the two outermost metal rings in the uppermost metal layer of the primary coil.

4. The on-chip transformer according to claim 3, characterized in that: All the output terminals are arranged in the uppermost metal layer of the secondary coil; The two output ends are respectively arranged on the outer rings of the two outermost metal rings in the uppermost metal layer of the secondary coil; The other output terminals are arranged on the connecting bridges in the metal ring.

5. An on-chip transformer according to any one of claims 1-2 and 4, characterized in that: The thickness of the dielectric layer disposed between the primary coil and the substrate layer is greater than the thickness of the dielectric layer disposed between adjacent metal layers; The thickness of the dielectric layer disposed between the primary coil and the substrate layer is 100-300 um.

6. The on-chip transformer according to claim 5, characterized in that: The thickness of the dielectric layer disposed between the primary coil and the substrate layer is 100 um.

7. The on-chip transformer according to claim 6, characterized in that: The thickness of all the dielectric layers disposed between adjacent metal layers is the same, which is 60-200 nm.

8. The on-chip transformer according to claim 7, characterized in that: The thickness of the dielectric layer disposed between adjacent metal layers is 60 nm.

9. A process for preparing an on-chip transformer as claimed in any one of claims 1 to 8, characterized in that the steps include: Coating a dielectric layer on the GaN-based substrate layer; Then, the primary coil and the secondary coil formed by multiple metal layers are sequentially grown on the dielectric layer, and each of the metal layers is grown on a different layer of the dielectric layer; The signal enters from N input terminals arranged on the primary coil and is then output through (N+1) output terminals arranged in the secondary coil, wherein N is an integer.

10. The process for manufacturing an on-chip transformer according to claim 9, characterized in that: N is 2, and all the dielectric layers are Si3N4 dielectric layers; The number of the metal layers in the primary coil and the secondary coil is the same, which is 2.

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