Packaging structure and preparation method

Abstract

The present invention provides a packaging structure and a preparation method thereof, wherein the packaging structure comprises a glass substrate, a metal connection column, a first packaging layer, a connection layer, a semiconductor chip, a filling layer, a second packaging layer, a controllable collapse chip connection layer, a substrate and a heat dissipation housing. The present invention directly forms a metal connection column in the glass substrate, so that the glass substrate can be directly used as an intermediate conductive layer, and forms a semiconductor chip and a controllable collapse chip connection layer at opposite ends of the metal connection column respectively for electrical connection, thereby reducing the process flow of preparing the packaging structure and reducing the preparation cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and in particular to a packaging structure and a preparation method thereof. Background Art

[0002] In the field of semiconductor manufacturing, there is Moore's Law, which is known as the first law of computers. That is, when the price remains unchanged, the number of components that can be accommodated on an integrated circuit will double approximately every 18 to 24 months, and the performance will also double.

[0003] At present, the front-end process has reached the latter part of Moore's Law, the process has reached the physical limit of exposure, and the investment cost is too high. Therefore, future development will focus on the development of back-end advanced packaging technology. Among them, back-end packaging technology can be roughly divided into three line spacings, including substrate level (Substrate Level) line width / line spacing (L / S)>10μm, wafer level (Wafer Level) line width / line spacing (L / S)>2μm, such as fan-out wafer level packaging (Fan Out Wafer Level Package, FOWLP) and wafer processing level (Foundry Level) line width / line spacing (L / S)<2μm.

[0004] The existing system-on-chip packaging SOC (System on a Chip) usually uses chips with different performances prepared by the front-end to be attached to the TSV transfer board (Interposer) respectively, and then connected to the substrate through the TSV Interposer to form a system-level (System In a Package, SIP) 2.5DIC packaging structure. However, in the existing 2.5DIC packaging structure, TSV Interposer is required as an intermediate connector, so the packaging cost is relatively high.

[0005] Therefore, it is necessary to provide a new packaging structure and preparation method. Summary of the invention

[0006] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a packaging structure and a preparation method thereof, so as to solve the problem of high packaging cost in the prior art.

[0007] To achieve the above object and other related objects, the present invention provides a method for preparing a packaging structure, comprising the following steps:

[0008] providing a glass substrate having a groove therein;

[0009] forming a metal connecting column in the groove, wherein the metal connecting column comprises a first end in contact with the glass substrate and an opposite second end;

[0010] The groove and the metal connecting column are encapsulated by a first encapsulation layer, and the first encapsulation layer exposes the second end of the metal connecting column;

[0011] forming a connection layer on the glass substrate, wherein the connection layer includes a metal bump electrically connected to the metal connection column and a dielectric layer covering the first packaging layer and the glass substrate;

[0012] Providing a semiconductor chip, wherein the semiconductor chip is located on the connection layer, and the front side of the semiconductor chip is electrically connected to the metal bump via a chip pad, and the back side of the semiconductor chip is away from the glass substrate;

[0013] Filling the gap between the semiconductor chip and the connection layer with a filling layer to cover the front surface and metal bumps of the semiconductor chip;

[0014] Using a second packaging layer to package the connection layer and the semiconductor chip;

[0015] removing a portion of the glass substrate to expose the first end of the metal connecting column;

[0016] forming a controllable collapse chip connection layer, wherein the controllable collapse chip connection layer comprises a wiring layer and solder bumps, and the wiring layer is electrically connected to the metal connection column;

[0017] Thinning the second packaging layer to expose the back side of the semiconductor chip to form a packaging body;

[0018] Providing a substrate, the package body being electrically connected to the substrate through the solder bumps;

[0019] A heat dissipation housing is provided. The heat dissipation housing is located on the substrate and covers the packaging body. The bottom of the heat dissipation housing is in contact with the packaging body.

[0020] Optionally, the height of the metal connecting column is greater than the depth of the groove.

[0021] Optionally, the first encapsulation layer is formed to cover the glass substrate, and a grinding method is used to expose the second end of the metal connecting column.

[0022] Optionally, the method further includes forming a plastic sealing layer between the controllable collapse chip connection layer and the substrate.

[0023] The present invention also provides a packaging structure, the packaging structure comprising:

[0024] A glass substrate, wherein the glass substrate has a groove penetrating the glass substrate;

[0025] A metal connecting column, the metal connecting column is located in the groove, and the metal connecting column includes a first end and an opposite second end;

[0026] a first packaging layer, wherein the first packaging layer covers the metal connecting column and fills the groove, and the first end and the second end of the metal connecting column are exposed in the first packaging layer;

[0027] A connection layer, located on the glass substrate, the connection layer comprising a metal bump electrically connected to the second end of the metal connection column and a dielectric layer covering the first packaging layer and the glass substrate;

[0028] A semiconductor chip, wherein the semiconductor chip is located on the connection layer, and the front side of the semiconductor chip is electrically connected to the metal bump via a chip pad, and the back side of the semiconductor chip is away from the glass substrate;

[0029] A filling layer, wherein the filling layer fills the gap between the semiconductor chip and the connecting layer to cover the front surface and the metal bumps of the semiconductor chip;

[0030] A second packaging layer, wherein the second packaging layer packages the connection layer and the semiconductor chip and exposes the back side of the semiconductor chip;

[0031] A controllable collapse chip connection layer, the controllable collapse chip connection layer comprising a wiring layer and solder bumps, and the wiring layer is electrically connected to the first end of the metal connection column to form a package;

[0032] a substrate, the package body being electrically connected to the substrate via the solder bumps;

[0033] A heat dissipation shell is located on the substrate and covers the packaging body, and the bottom of the heat dissipation shell is in contact with the packaging body.

[0034] Optionally, the metal connecting column includes one or a combination of an Au metal connecting column, an Ag metal connecting column, a Cu metal connecting column and an Al metal connecting column.

[0035] Optionally, the first encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer; and the second encapsulation layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0036] Optionally, the filling layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0037] Optionally, it also includes a solder bump electrically connected to the substrate; and it also includes a plastic packaging layer located between the controllable collapse chip connection layer and the substrate.

[0038] Optionally, the solder bump includes one of a copper solder bump, a nickel solder bump, a tin solder bump and a silver solder bump; the metal bump includes one of a copper metal bump, a nickel metal bump, a tin metal bump and a silver metal bump.

[0039] As described above, the packaging structure and preparation method of the present invention directly form metal connecting columns in the glass substrate, so that the glass substrate can directly serve as an intermediate conductive layer, and form a semiconductor chip and a controllable collapse chip connection layer at the opposite ends of the metal connecting columns for electrical connection, thereby reducing the process flow of preparing the packaging structure and reducing the preparation cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Shown is a process flow chart of the preparation of the packaging structure of the present invention.

[0041] Figure 2 to Figure 14 It is a schematic diagram of the structure presented in each step of the process of preparing the packaging structure in the present invention, wherein: Fig.14 Shown is a schematic structural diagram of the packaging structure prepared in the present invention.

[0042] Component number description

[0043] 100 Glass substrate

[0044] 101 Groove

[0045] 200 Metal connecting column

[0046] 300 First packaging layer

[0047] 400 Connection layer

[0048] 401 Dielectric Layer

[0049] 402 metal bumps

[0050] 500 Semiconductor Chips

[0051] 600 Filling Layers

[0052] 700 Second packaging layer

[0053] 800 Controllable collapse chip connection layer

[0054] 801 Wiring Layer

[0055] 802 solder bump

[0056] 900 substrate

[0057] 110 Solder Bumps

[0058] 120 Plastic layer

[0059] 130 heat sink DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0062] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can be one or more intervening layers. As used herein, "between..." means including the end point values.

[0063] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0064] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0065] See also Figure 1 This embodiment provides a method for preparing a packaging structure. In this embodiment, a metal connection column is directly formed in a glass substrate, so that the glass substrate can be directly used as an intermediate conductive layer, and a semiconductor chip and a controllable collapse chip connection layer are respectively formed at opposite ends of the metal connection column for electrical connection, thereby reducing the process flow of preparing the packaging structure and reducing the preparation cost. The specific preparation process is as follows:

[0066] First, if Figure 2 , providing a glass substrate 100, wherein the glass substrate 100 has a groove 101.

[0067] Specifically, the glass substrate 100 can be etched to form the groove 101. The preparation method, morphology, and size of the groove 101 can be selected as needed and are not excessively limited herein.

[0068] Next, see Figure 3 A metal connecting column 200 is formed in the groove 101 , and the metal connecting column 200 includes a first end in contact with the glass substrate 100 and an opposite second end.

[0069] Specifically, the metal connection column 200 may include one or a combination of an Au metal connection column, an Ag metal connection column, a Cu metal connection column and an Al metal connection column. In this embodiment, a Cu metal connection column is used, but it is not limited to this.

[0070] As an example, it is preferred that the height of the metal connection column 200 is greater than the depth of the groove, so as to facilitate the electrical connection between the connection layer 400 formed in the subsequent process and the metal connection column 200 .

[0071] Next, see Figure 4-5 The first packaging layer 300 is used to package the groove 101 and the metal connecting column 200 , and the first packaging layer 300 exposes the second end of the metal connecting column 200 .

[0072] Specifically, in this embodiment, it is preferred that the first encapsulation layer 300 covers the glass substrate 100, and a grinding method is used to expose the second end of the metal connecting column 200, so that a smooth surface can be provided through a grinding method, such as one or a combination of mechanical grinding and CMP methods, to facilitate the subsequent formation of the connecting layer 400 and improve the bonding quality.

[0073] Next, see Figure 6 , forming the connection layer 400 on the glass substrate 100 , the connection layer 400 includes a metal bump 402 electrically connected to the metal connection column 200 and a dielectric layer 401 covering the first packaging layer 300 and the glass substrate 100 .

[0074] Among them, the dielectric layer 401 may include one of an epoxy resin dielectric layer, a polyimide dielectric layer and a silicone dielectric layer, and the material of the dielectric layer 401 is not excessively restricted here; the metal bump 402 may include one of a copper metal bump, a nickel metal bump, a tin metal bump and a silver metal bump, and the material of the metal bump 402 is not excessively restricted here.

[0075] Next, see Figure 7, providing a semiconductor chip 500, wherein the semiconductor chip 500 is located on the connecting layer 400, and the front side of the semiconductor chip 500 is electrically connected to the metal bump 402 through a chip pad, and the back side of the semiconductor chip 500 is away from the glass substrate 100, wherein the type and size of the semiconductor chip 500 can be selected as needed, and no excessive restrictions are made here.

[0076] Next, see Figure 8 A filling layer 600 is used to fill the gap between the semiconductor chip 500 and the connection layer 400 to cover the front surface of the semiconductor chip 500 and the metal bumps 402 .

[0077] Specifically, the filling layer 600 may include one of an epoxy resin layer, a polyimide layer and a silicone layer, so that the filling layer 600 can be used as a protective layer to prevent pollutants such as water vapor from contaminating the chip pads and the metal bumps 402 of the semiconductor chip 500, and the filling layer 600 can also play a good fixing role to improve the bonding strength between the semiconductor chip 500 and the metal bumps 402.

[0078] Next, see Fig. 9 , a second packaging layer 700 is used to package the connection layer 400 and the semiconductor chip 500 .

[0079] Specifically, the second encapsulation layer 700 may include one of an epoxy resin layer, a polyimide layer and a silicone layer, and the method of forming the second encapsulation layer 700 may include one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating. The second encapsulation layer 700 can protect the semiconductor chip 500, and the second encapsulation layer 700 can be used as a supporting substrate to facilitate the subsequent thinning of the glass substrate 100 and the preparation of the controllable collapse chip connection layer 800, so as to reduce the process complexity.

[0080] Next, see Fig.10 , remove part of the glass substrate 100 to expose the first end of the metal connecting column 200, wherein the method of removing part of the glass substrate 100 may include one or a combination of mechanical grinding and CMP methods, which can be selected according to needs.

[0081] Next, see Fig.11 , forming the controllable collapse chip connection layer 800, the controllable collapse chip connection layer 800 includes a wiring layer 801 and a solder bump 802, and the wiring layer 801 is electrically connected to the metal connection column 200.

[0082] Specifically, the controllable collapse chip connection layer 800 may include 1 to 5 layers of the wiring layer 801 stacked, and the wiring layer 801 may include one or a combination of Au wiring metal, Ag wiring metal, Cu wiring metal and Al wiring metal; the solder bump 802 may include one of copper solder bumps, nickel solder bumps, tin solder bumps and silver solder bumps, or alloy solder bumps prepared from an alloy formed by Cu, Ni, Sn and Ag metals. The specific selection can be made according to needs, and the preparation method is not limited here.

[0083] Next, see Fig.12 , thinning the second packaging layer 700 to expose the back side of the semiconductor chip 500 to form a packaging body.

[0084] Specifically, the method of thinning the second packaging layer 700 may include one or a combination of mechanical grinding and CMP to reduce the thickness. During the thinning process, the back side of the semiconductor chip 500 may also be thinned according to the type of the semiconductor chip 500, and no excessive restrictions are made here.

[0085] Next, see Fig.13 , providing a substrate 900, and the package body is electrically connected to the substrate 900 through the solder bumps 802.

[0086] Specifically, the substrate 900 may include a PCB, an FPC or a metal circuit board. In this embodiment, a PCB is used as an example. The solder pads on the PCB are electrically connected to the solder bumps 802 for electrical lead-out.

[0087] As an example, the step of forming a solder bump 110 on the substrate 900 is also included to facilitate electrical lead-out through the solder bump 110, wherein the solder bump 110 may include one of a copper solder bump, a nickel solder bump, a tin solder bump and a silver solder bump, and the specific selection can be made according to needs.

[0088] As an example, the method also includes a step of forming a plastic encapsulation layer 120 between the controllable collapse chip connection layer 800 and the substrate 900, wherein the plastic encapsulation layer 120 includes one of an epoxy resin layer, a polyimide layer and a silicone layer to improve the bonding strength between the controllable collapse chip connection layer 800 and the substrate 900, and protect the controllable collapse chip connection layer 800 and the substrate 900 to avoid moisture and oxidation, thereby improving stability.

[0089] Next, see Fig.14 , providing a heat dissipation housing 130, wherein the heat dissipation housing 130 is located on the substrate 900, covers the package body, and the bottom of the heat dissipation housing 130 is in contact with the package body.

[0090] Specifically, the heat dissipation housing 130 may be bonded to the packaging body through a material with good thermal conductivity, so as to further provide a heat dissipation effect.

[0091] like Fig.14 This embodiment also provides a packaging structure, which includes a glass substrate 100, a metal connecting column 200, a first packaging layer 300, a connecting layer 400, a semiconductor chip 500, a filling layer 600, a second packaging layer 700, a controllable collapse chip connecting layer 800, a substrate 900 and a heat dissipation shell 130.

[0092] Specifically, the glass substrate 100 has a groove 101 penetrating the glass substrate 100; the metal connecting column 200 is located in the groove 101, and the metal connecting column 200 includes a first end and an opposite second end; the first packaging layer 300 covers the metal connecting column 200 and fills the groove 101, and the first end and the second end of the metal connecting column 200 are exposed in the first packaging layer 300; the connecting layer 400 is located on the glass substrate 100, and the connecting layer 400 includes a metal bump 402 electrically connected to the second end of the metal connecting column 200 and a dielectric layer 401 covering the first packaging layer 300 and the glass substrate 100; the semiconductor chip 500 is located on the connecting layer 400, and the front side of the semiconductor chip 500 is connected to the metal bump 200 through a chip pad. 0 is electrically connected, and the back side of the semiconductor chip 500 is away from the glass substrate 100; the filling layer 600 fills the gap between the semiconductor chip 500 and the connecting layer 400 to cover the front side of the semiconductor chip 500 and the metal bump 402; the second packaging layer 700 encapsulates the connecting layer 400 and the semiconductor chip 500, and exposes the back side of the semiconductor chip 500; the controllable collapse chip connecting layer 800 includes a wiring layer 801 and a solder bump 802, and the wiring layer 801 is electrically connected to the first end of the metal connecting column 200 to form a package body; the package body is electrically connected to the substrate 900 through the solder bump 802; the heat dissipation housing 130 is located on the substrate 900, covers the package body, and the bottom of the heat dissipation housing 130 is in contact with the package body.

[0093] Specifically, in this embodiment, the packaging structure can be prepared by the above method, but is not limited thereto. In this embodiment, the packaging structure is prepared by the above preparation method, so the relevant preparation process, materials, etc. are not described in detail here.

[0094] The glass substrate 100 of this embodiment directly serves as an intermediate conductive layer, and the semiconductor chip 500 and the controllable collapse chip connection layer 800 are respectively formed at opposite ends of the metal connecting column 200 for electrical connection, thereby reducing the process flow of preparing the packaging structure and reducing the preparation cost.

[0095] As an example, the metal connection column 200 includes one or a combination of an Au metal connection column, an Ag metal connection column, a Cu metal connection column and an Al metal connection column.

[0096] As an example, the first encapsulation layer 300 includes one of an epoxy resin layer, a polyimide layer and a silicone layer; the second encapsulation layer 700 includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0097] As an example, the filling layer 600 includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

[0098] As an example, a solder bump 110 electrically connected to the substrate 900 is also included.

[0099] As an example, a plastic encapsulation layer 120 is further included between the controllable collapse chip connection layer 800 and the substrate 900 .

[0100] As an example, the solder bump 802 includes one of a copper solder bump, a nickel solder bump, a tin solder bump, and a silver solder bump; the metal bump 402 includes one of a copper metal bump, a nickel metal bump, a tin metal bump, and a silver metal bump.

[0101] In summary, the packaging structure and preparation method of the present invention directly form metal connecting columns in the glass substrate, so that the glass substrate can directly serve as an intermediate conductive layer, and form a semiconductor chip and a controllable collapse chip connection layer at the opposite ends of the metal connecting columns for electrical connection, thereby reducing the process flow of preparing the packaging structure and reducing the preparation cost.

[0102] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging structure, characterized in that: The following steps are involved: providing a glass substrate having a groove therein; forming a metal connecting column in the groove, wherein the metal connecting column comprises a first end in contact with the glass substrate and an opposite second end; The groove and the metal connecting column are encapsulated by a first encapsulation layer, and the first encapsulation layer exposes the second end of the metal connecting column; forming a connection layer on the glass substrate, wherein the connection layer includes a metal bump electrically connected to the metal connection column and a dielectric layer covering the first packaging layer and the glass substrate; Providing a semiconductor chip, wherein the semiconductor chip is located on the connection layer, and the front side of the semiconductor chip is electrically connected to the metal bump via a chip pad, and the back side of the semiconductor chip is away from the glass substrate; Filling the gap between the semiconductor chip and the connection layer with a filling layer to cover the front surface and metal bumps of the semiconductor chip; Using a second packaging layer to package the connection layer and the semiconductor chip; Removing a portion of the glass substrate to expose the first end of the metal connecting column; forming a controllable collapse chip connection layer, wherein the controllable collapse chip connection layer comprises a wiring layer and solder bumps, and the wiring layer is electrically connected to the metal connection column; Thinning the second packaging layer to expose the back side of the semiconductor chip to form a packaging body; Providing a substrate, the package body being electrically connected to the substrate via the solder bumps; A heat dissipation housing is provided. The heat dissipation housing is located on the substrate and covers the packaging body. The bottom of the heat dissipation housing is in contact with the packaging body.

2. The method for preparing a packaging structure according to claim 1, characterized in that: The height of the metal connecting column is greater than the depth of the groove.

3. The method for preparing a packaging structure according to claim 1, characterized in that: The first encapsulation layer is formed to cover the glass substrate, and a grinding method is used to expose the second end of the metal connection column.

4. The method for preparing a packaging structure according to claim 1, wherein: The method also includes the step of forming a plastic sealing layer between the controllable collapse chip connection layer and the substrate.

5. A packaging structure, characterized in that: The packaging structure comprises: A glass substrate, wherein the glass substrate has a groove penetrating the glass substrate; A metal connecting column, the metal connecting column is located in the groove, and the metal connecting column includes a first end and an opposite second end; a first packaging layer, wherein the first packaging layer covers the metal connecting column and fills the groove, and the first end and the second end of the metal connecting column are exposed in the first packaging layer; A connection layer, located on the glass substrate, the connection layer comprising a metal bump electrically connected to the second end of the metal connection column and a dielectric layer covering the first packaging layer and the glass substrate; A semiconductor chip, wherein the semiconductor chip is located on the connection layer, and the front side of the semiconductor chip is electrically connected to the metal bump via a chip pad, and the back side of the semiconductor chip is away from the glass substrate; A filling layer, wherein the filling layer fills the gap between the semiconductor chip and the connecting layer to cover the front surface and the metal bumps of the semiconductor chip; A second packaging layer, wherein the second packaging layer packages the connection layer and the semiconductor chip and exposes the back side of the semiconductor chip; A controllable collapse chip connection layer, the controllable collapse chip connection layer comprising a wiring layer and solder bumps, and the wiring layer is electrically connected to the first end of the metal connection column to form a package; a substrate, the package body being electrically connected to the substrate via the solder bumps; A heat dissipation housing, the heat dissipation housing is located on the substrate, covers the packaging body, and the bottom of the heat dissipation housing is in contact with the packaging body; It also includes a solder bump electrically connected to the substrate; and a plastic packaging layer located between the controllable collapse chip connection layer and the substrate.

6. The packaging structure according to claim 5, characterized in that: The metal connection column includes one or a combination of Au metal connection column, Ag metal connection column, Cu metal connection column and Al metal connection column.

7. The packaging structure according to claim 5, characterized in that: The first packaging layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer; the second packaging layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

8. The packaging structure according to claim 5, characterized in that: The filling layer includes one of an epoxy resin layer, a polyimide layer and a silicone layer.

9. The packaging structure according to claim 5, characterized in that: The solder bumps include one of copper solder bumps, nickel solder bumps, tin solder bumps and silver solder bumps; the metal bumps include one of copper metal bumps, nickel metal bumps, tin metal bumps and silver metal bumps.

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