Chip packaging method and structure

Abstract

The chip packaging method and structure provided by the embodiment of the present invention, wherein the chip packaging method comprises: providing a plurality of stacked bare chips; wherein the pads on the surfaces of the plurality of bare chips are exposed by offsetting the plurality of bare chips; and forming metal wires on the surfaces of the plurality of bare chips by a three-dimensional (3D) printing method, wherein the metal wires are used to electrically connect the corresponding pads on the surfaces of the plurality of bare chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip packaging method and structure. Background Art

[0002] The main function of packaging is to wrap the chip with a shell, which not only plays the role of installation, fixing, sealing, protecting the chip and enhancing the electrical and thermal performance, but also connects the wires to the pins of the package shell through the pads on the chip. These pins are connected to other devices through the wires on the circuit board, thereby realizing the connection between the internal chip and the external circuit. Because the chip must be isolated from the outside world to prevent impurities and water vapor in the air from corroding the chip circuit and causing a decrease in electrical performance. In addition, the packaged chip is also easier to install and transport. Since the quality of packaging technology directly affects the performance of the chip itself, as well as the design and manufacture of the circuit board connected to it, packaging is crucial.

[0003] However, the traditional packaging process has many problems, which seriously restricts the development of packaging technology. Therefore, it is urgent to provide a new packaging process. Summary of the invention

[0004] In view of this, an embodiment of the present invention is intended to provide a chip packaging method and structure.

[0005] The chip packaging method provided by the embodiment of the present invention includes:

[0006] Providing a plurality of stacked dies; wherein pads on the surfaces of the plurality of dies are exposed by offsetting the plurality of dies;

[0007] A three-dimensional (3D) printing method is used to form metal wires on the surfaces of the plurality of bare chips, and the metal wires are used to electrically connect corresponding pads on the surfaces of the plurality of bare chips.

[0008] In the above solution, the step of forming metal wires on the surfaces of the plurality of bare chips by using a 3D printing method includes:

[0009] The metal wire is printed using metal powder by 3D printing;

[0010] or,

[0011] The 3D printing method is adopted to print metal lines using a metal solution; and the metal lines are sintered to obtain the metal lines.

[0012] In the above solution, the step of forming metal wires on the surfaces of the plurality of bare chips by using a 3D printing method includes:

[0013] forming a metal layer on the surfaces of the plurality of dies;

[0014] Printing a mask layer at a position on the surface of the metal layer where no metal wire is needed by using a 3D printing method;

[0015] Performing chemical nickel-gold treatment on the metal layer not blocked by the mask layer; removing the mask layer and the metal layer blocked by the mask layer to form the metal wire.

[0016] In the above solution, the step of forming metal wires on the surfaces of the plurality of bare chips by using a 3D printing method includes:

[0017] forming a metal layer on the surfaces of the plurality of dies;

[0018] Printing a mask layer at a position where a metal line needs to be formed on the surface of the metal layer by a 3D printing method;

[0019] The metal layer and the mask layer that are not blocked by the mask layer are removed to form the metal line.

[0020] In the above solution, the metal wire includes a first metal wire layer and a second metal wire layer which are stacked; and the step of forming the metal wires on the surfaces of the plurality of bare chips by using a 3D printing method includes:

[0021] Forming the first metal wire layer on the surfaces of the plurality of bare chips by using a 3D printing method;

[0022] forming a first insulating layer on the first metal wire layer by using a 3D printing method;

[0023] A second metal wire layer is formed on the insulating layer by using a 3D printing method; wherein the first metal wire in the first metal wire layer and the second metal wire in the second metal wire layer are electrically connected through contact between one end of the first metal wire and the corresponding end of the second metal wire.

[0024] In the above solution, the plurality of dies are stacked in a stepped shape, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies;

[0025] The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises:

[0026] A plurality of metal lines are formed on the surfaces of the plurality of dies; wherein each of the plurality of metal lines respectively connects pads on corresponding adjacent dies on different step surfaces.

[0027] In the above solution, the plurality of dies are stacked in a stepped shape, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies;

[0028] The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises:

[0029] A plurality of metal lines are formed on the surfaces of the plurality of dies; wherein at least one metal line crosses over the plurality of step surfaces to connect pads on corresponding spaced dies on different step surfaces.

[0030] In the above solution, the plurality of dies include a first die group offset along a first direction and a second die group offset along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of dies are stacked; the first direction is different from the second direction;

[0031] The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises:

[0032] A plurality of metal lines are formed on the surfaces of the plurality of bare chips; wherein at least one metal line includes a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; and pads on corresponding spaced bare chips on different step surfaces are connected through the first portion and the second portion.

[0033] In the above solution, the plurality of stacked dies are provided, including:

[0034] Provide multiple dies;

[0035] forming a second insulating layer on the side surface and the bottom surface of each die in the plurality of dies;

[0036] A plurality of bare chips formed with the second insulating layer are stacked.

[0037] In the above solution, forming a second insulating layer on the side surface and bottom surface of each bare chip in the plurality of bare chips includes:

[0038] Separating a plurality of bare chips by a dicing path; a spacing between the separated plurality of bare chips is a width of the dicing path;

[0039] forming a first insulating material covering bottom surfaces of the plurality of dies;

[0040] Pressing a portion of the first insulating material into the gaps between the plurality of dies to form a second insulating layer covering the side surface of each of the plurality of dies;

[0041] Forming a second insulating material covering the remaining first insulating material on the bottom surfaces of the plurality of bare chips; the first insulating material on the side surface of each bare chip and the first insulating material and the second insulating material on the bottom surface form the second insulating layer;

[0042] The second insulating layer in the gaps between the plurality of dies is cut to obtain a plurality of separated dies.

[0043] In the above scheme, the method further includes:

[0044] Before forming the first insulating material covering the bottom surfaces of the plurality of dies, rearrange the plurality of dies on the carrier so as to increase the spacing between the plurality of dies;

[0045] After forming a second insulating material covering the remaining first insulating material on bottom surfaces of the plurality of dies, the carrier is removed.

[0046] In the above scheme, the method further includes:

[0047] forming the stacked plurality of dies on a first surface of a semiconductor substrate;

[0048] After forming metal wires on the surfaces of the plurality of bare chips by a 3D printing method, forming a plastic packaging layer covering the semiconductor substrate, the plurality of bare chips and the metal wires;

[0049] A plurality of metal solder balls are formed on a second surface of the semiconductor substrate; the second surface is the opposite surface of the first surface.

[0050] In the above solution, before forming the metal line, the method further includes performing a first plasma treatment on the surface of the die to remove oxide on the pad and roughen the die.

[0051] In the above scheme, the method further includes:

[0052] After forming the metal lines, a second plasma treatment is performed on the surface of the die to remove residues from 3D printing.

[0053] An embodiment of the present invention further provides a chip packaging structure, wherein the packaging structure includes a packaging structure prepared by using the chip packaging method described in any one of the above schemes.

[0054] In the above solution, the plurality of dies are stacked in a stepped shape, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies;

[0055] The surfaces of the multiple bare chips are provided with a first metal wire layer and a second metal wire layer arranged in a stacked manner; a first insulating layer is also included between the first metal wire layer and the second metal wire layer; the first metal wire in the first metal wire layer is electrically connected to the second metal wire in the second metal wire layer through contact between one end of the first metal wire and the corresponding end of the second metal wire.

[0056] In the above solution, the plurality of dies are stacked in a stepped shape, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies;

[0057] A plurality of metal lines are disposed on the surfaces of the plurality of dies, and each of the plurality of metal lines respectively connects pads on corresponding adjacent dies on different step surfaces.

[0058] In the above solution, the plurality of dies are stacked in a stepped shape, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies;

[0059] A plurality of metal lines are arranged on the surfaces of the plurality of bare chips, at least one metal line spans across a plurality of step surfaces, and pads on corresponding spaced bare chips on different step surfaces are connected via the at least one metal line.

[0060] In the above solution, the plurality of dies include a first die group offset along a first direction and a second die group offset along a second direction; the first direction and the second direction are both perpendicular to the direction in which the plurality of dies are stacked; the first direction is different from the second direction;

[0061] A plurality of metal lines are arranged on the surfaces of the plurality of bare chips; wherein at least one metal line comprises a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; and pads on corresponding spaced bare chips on different step surfaces are connected via the first portion and the second portion.

[0062] The chip packaging method and structure provided by the embodiment of the present invention include: providing a plurality of stacked bare chips; wherein, by offsetting the plurality of bare chips, the pads on the surfaces of the plurality of bare chips are exposed; and forming metal wires on the surfaces of the plurality of bare chips by 3D printing, wherein the metal wires are used to electrically connect the corresponding pads on the surfaces of the plurality of bare chips. The chip packaging method and structure of the embodiment of the present invention adopts 3D printing technology to replace the traditional packaging technology, and has the following advantages: (1) The stacking structure can be more compact, thereby increasing the area of ​​the bare chips in the stacking structure under the same packaging size; (2) The metal wires are formed at one time and do not need to be printed multiple times; (3) The packaging thickness can be thinner without being affected by wire arcs; (4) The metal wires are in direct contact with the bare chips, and have better heat dissipation performance; (5) Compared with the traditional packaging technology, the packaging method of 3D printing metal wires has a relatively short metal wire path, so the formed semiconductor device has better high-frequency performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] Figure 1 A schematic diagram of a chip packaging method provided by an embodiment of the present invention;

[0064] Figure 2a-2k A schematic cross-sectional view of the steps of forming a second insulating layer on the side and bottom surface of each bare chip in a chip packaging method provided by an embodiment of the present invention;

[0065] Figure 3a-3f A cross-sectional schematic diagram of the steps of forming a second insulating layer on the side and bottom of each bare chip in another chip packaging method provided by an embodiment of the present invention;

[0066] Figure 4a-4c A schematic diagram of pre-processing a bare chip surface before 3D printing in a chip packaging method provided by an embodiment of the present invention;

[0067] Figure 5a-5c A schematic diagram of pre-processing a bare chip surface before 3D printing in another chip packaging method provided by an embodiment of the present invention;

[0068] Figure 6 A schematic diagram of the design of multiple bare chip surface metal lines in a chip packaging method provided by an embodiment of the present invention;

[0069] Figure 7 A schematic diagram of the design of multiple bare chip surface metal lines in another chip packaging method provided by an embodiment of the present invention;

[0070] Figure 8 A schematic diagram of the design of multiple bare chip surface metal lines in another chip packaging method provided by an embodiment of the present invention;

[0071] Fig. 9 A schematic diagram of the design of multiple bare chip surface metal lines in another chip packaging method provided by an embodiment of the present invention;

[0072] Fig.10a A schematic cross-sectional view of a packaging structure of a chip packaging method provided according to an embodiment of the present invention;

[0073] Fig.10b for Fig.10a Enlarged schematic diagram of point C in the middle. DETAILED DESCRIPTION

[0074] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0075] In the description of the present invention, it is necessary to understand that the terms "length", "width", "depth", "up", "down", "outside", etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0076] In the embodiments of the present invention, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0077] In an embodiment of the present invention, the term "layer" refers to a material portion including an area with a thickness. The layer may extend over the entirety of the lower or upper structure, or may have a range that is smaller than the range of the lower or upper structure. In addition, the layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, the layer may be located between the top surface and the bottom surface of the continuous structure, or the layer may be between any horizontal faces at the top surface and the bottom surface of the continuous structure. The layer may extend horizontally, vertically and / or along an inclined surface. The layer may include multiple sublayers. For example, an interconnect layer may include one or more conductors and contact sublayers (where interconnects and / or via contacts are formed), and one or more dielectric sublayers.

[0078] In the embodiments of the present invention, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0079] It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0080] In the related art, the traditional packaging technology for stacking memory chips generally uses a wire bump (WB) process. However, the wire bump process has the following problems:

[0081] (1) The wire bonding process has a long conductive path, which limits the high-frequency performance of the chip;

[0082] (2) During the wire bonding process, the wire loop will occupy a certain package height, thus affecting the design of the package structure;

[0083] (3) The wire bonding process time (which can be expressed as Production Time, CT) is long, requiring a certain number of wire bonding machines;

[0084] (4) The wire bonding process generally uses gold wire. Gold is a precious metal with high price and is easily affected by market factors, which makes the wire bonding process costly and difficult to control.

[0085] 3D printing is a rapid prototyping technology that has been increasingly used in industrial fields in recent years, such as the automotive, construction, electronics and medical industries; at the same time, the development of 3D printing technology has accelerated the process of product innovation.

[0086] The chip packaging method of the embodiment of the present invention adopts a 3D printing process to replace the traditional packaging process, and proposes a new chip packaging method, which has the following advantages: (1) the stacking structure can be more compact, thereby increasing the area of ​​the bare chip in the stacking structure under the condition of the same packaging size; (2) the metal wire is formed at one time and does not need to be printed multiple times; (3) it is not affected by wire arcs, and the packaging thickness can be thinner; (4) the metal wire is in direct contact with the bare chip, and has better heat dissipation performance; (5) compared with the traditional packaging process, the packaging method of 3D printing metal wire has a relatively short metal wire path, so the formed semiconductor device has better high-frequency performance.

[0087] An embodiment of the present invention provides a chip packaging method. Figure 1 The following is a schematic diagram of a chip packaging method provided in an embodiment of the present application. Figure 1 As shown, the method comprises the following steps:

[0088] Step 101: providing a plurality of stacked bare chips; wherein pads on the surfaces of the plurality of bare chips are exposed by offsetting the plurality of bare chips;

[0089] Step 102: Form metal wires on the surfaces of the plurality of bare chips using a 3D printing method, wherein the metal wires are used to electrically connect corresponding pads on the surfaces of the plurality of bare chips.

[0090] Figure 2a-Figure 3f The following is a schematic cross-sectional diagram of the implementation steps of a chip packaging method provided by an embodiment of the present invention. It should be understood that Figure 1 The operations shown in are not exclusive, and other operations may be performed before, after, or between any of the operations shown. Figure 1 , Figure 2a-Figure 3f The chip packaging method of this embodiment is described.

[0091] First, in step 101 , a plurality of stacked dies are provided.

[0092] In one embodiment, providing a plurality of stacked dies comprises:

[0093] Provide multiple dies;

[0094] A second insulating layer is formed on each die side surface and bottom surface of the die;

[0095] A plurality of bare chips formed with the second insulating layer are stacked.

[0096] In actual applications, each bare chip is a device that has not been packaged after the wafer has been cut and tested. This bare chip has a pad for packaging and cannot be directly used in actual circuits. When the bare chip is packaged into a semiconductor chip, it can be directly used in actual circuits.

[0097] In practical applications, there are usually some test pads in the wafer dicing grooves, and metal residues will remain after dicing, so each die needs to be insulated. A second insulating layer is formed on the side and bottom of each of the multiple dies, which, on the one hand, plays an insulating and side protection role, and on the other hand, can increase the mechanical strength of the die, so that the formed semiconductor device has better reliability.

[0098] In one embodiment, forming a second insulating layer on the side surface and the bottom surface of each die in the plurality of dies comprises:

[0099] A plurality of bare chips are separated by cutting paths; the spacing between the separated bare chips is the width of the cutting paths; a first insulating material covering the bottom surfaces of the plurality of bare chips is formed; a portion of the first insulating material is pressed into the gaps between the plurality of bare chips to form a second insulating layer covering the side surfaces of each bare chip in the plurality of bare chips; a second insulating material covering the remaining first insulating material on the bottom surfaces of the plurality of bare chips is formed; the first insulating material on the side surfaces of each bare chip and the first insulating material and the second insulating material on the bottom surface form the second insulating layer; the second insulating layer in the gaps between the plurality of bare chips is cut to obtain a plurality of separated bare chips.

[0100] The following will refer to Figure 2a-2k The above specific steps are explained.

[0101] like Figure 2a , Figure 2b As shown, multiple dies 201 are separated by dicing lines; the spacing between the separated multiple dies 201 is the width of the dicing line 203. Specifically, the front side of the die is fixed on the grinding film 202, and the bottom side of the die 201 is ground to expose the die dicing line 203.

[0102] like Figure 2c As shown, a first insulating material 204 covering the bottom surfaces of the plurality of bare chips 201 is formed on the bottom surface of the bare chip 201. In practical applications, the first insulating material 204 includes an Ajinomoto Build-up Film (ABF film) or an epoxy molding compound (EMC).

[0103] like Figure 2d As shown, the polishing film 202 is removed.

[0104] like Figure 2e As shown, the bare chip 201 is pasted face down onto the adhesive layer 206 of the carrier 205 (which can be expressed as PanelCarrier in English); then Figure 2f As shown, a pressing module 207 is used to press part of the first insulating material 204 into the gaps between the plurality of bare chips 201, so that the first insulating material 204 covers the bottom surface and side surfaces of each bare chip 201 in the plurality of bare chips 201; Figure 2g As shown, the first insulating material 204 in the gaps between the plurality of dies 201 forms a second insulating layer 208A covering the side surface of each die 201 in the plurality of dies 201 .

[0105] like Figure 2h , Figure 2i As shown, a second insulating material 209 is formed to cover the remaining first insulating material 204 on the bottom surfaces of the plurality of dies 201; the first insulating material 204 and the second insulating material 209 on the bottom surface of each die form a second insulating layer 208B covering the bottom surface of each die 201 in the plurality of dies 201; the second insulating layer 208A on the side surface of each die 201 and the second insulating layer 208B on the bottom surface constitute a second insulating layer 208 covering each die 201 in the plurality of dies 201. In practical applications, the second insulating material 209 includes a die attach film (DAF film).

[0106] like Figure 2j As shown, the carrier 205 and the adhesive layer 206 are removed.

[0107] like Figure 2k As shown, the second insulating layer 208A in the gaps between the plurality of dies 201 is cut to obtain a plurality of separated dies.

[0108] In practical applications, the insulating material on the side of the bare chip is relatively thin, specifically, the thickness of the insulating material is about 5um-10um.

[0109] In the above embodiment, the bottom and side surfaces of the bare die 201 are coated with insulating material on the wafer, and after the coating is completed, the plurality of bare die are separated by cutting paths on the surface of the wafer, so that the bare die does not need to be re-mounted on the substrate during the bare die coating process, thereby saving costs.

[0110] The above embodiment describes a method of forming the second insulating layer 208 on the side and bottom of each die 201 . Another method of forming the second insulating layer 208 on the side and bottom of each die 201 will be described below with multiple embodiments.

[0111] In one embodiment, before forming the first insulating material 204 covering the bottom surfaces of the plurality of bare chips 201, the plurality of bare chips 201 are rearranged on the carrier 205 so as to increase the spacing between the plurality of bare chips 201; after forming the second insulating material 209 covering the remaining first insulating material 204 on the bottom surfaces of the plurality of bare chips 201, the carrier 205 is removed.

[0112] The following will refer to Figure Figure 3a-3f Specific steps of forming the second insulating layer 208 are described below.

[0113] like Figure 3a As shown, the wafer is cut on a wafer dicing tape 210 (which can be expressed as Dicing Tape in English) to obtain individual bare chips 201 .

[0114] like Figure 3b As shown, the bare chips 201 are rearranged with their front sides facing downwards at a certain interval and then pasted onto the adhesive layer 206 of the carrier 205 .

[0115] like Figure 3c As shown, a first insulating material 204 covering the bottom surfaces of the plurality of dies is formed on the bottom surface of the die 201, and then a pressing module ( Figure 3c (not shown) a portion of the first insulating material 204 is pressed into the gaps between the plurality of bare chips 201 to form a second insulating layer 208A covering the side of each bare chip 201 in the plurality of bare chips 201. In practical applications, the first insulating material 204 includes an ABF film or an epoxy resin molding compound.

[0116] like Figure 3d As shown, a second insulating material 209 is formed to cover the remaining first insulating material 204 on the bottom surfaces of the plurality of dies 201; the first insulating material 204 and the second insulating material 209 on the bottom surface of each die 201 form a second insulating layer 208B covering the bottom surface of each die 201 in the plurality of dies 201; the second insulating layer 208A on the side surface of each die 201 and the second insulating layer 208B on the bottom surface constitute a second insulating layer 208 covering each die 201 in the plurality of dies 201. In practical applications, the second insulating material includes a DAF film.

[0117] like Figure 3e As shown, the carrier 205 and the adhesive layer 206 are removed.

[0118] like Figure 3f As shown, the second insulating layer 208A in the gaps between the plurality of dies 201 is cut to obtain a plurality of separated dies.

[0119] In practical applications, the thickness of the insulating material coated on the side of the die can be specifically designed according to the requirements. In one embodiment, the thickness of the insulating material is about 10um-20um.

[0120] In the above embodiment, before forming the first insulating material 204 covering the bottom surfaces of the plurality of dies, the plurality of dies 201 are rearranged on the carrier 205. Therefore, the spacing between the dies 201 can be adjusted as needed, thereby adjusting the width of the insulating material between the side walls of adjacent dies 201.

[0121] In one embodiment, the insulating material layer on the sidewall of the die 201 may be designed to have a certain slope, thereby reducing the difficulty in the subsequent process of forming metal lines on the surface of the die.

[0122] Next, in step 101 , after a second insulating layer is formed on the side surface and bottom surface of each of the plurality of dies, the pads on the surfaces of the plurality of dies are exposed by offsetting the plurality of dies.

[0123] In practical applications, the plurality of dies may be offset in any direction parallel to the surfaces of the plurality of dies. Specifically, two adjacent dies along the stacking direction may be offset so that the pads on the surface of the other die are exposed. In one embodiment, the plurality of dies are stacked in a stepped manner, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies. The plurality of dies except the bottommost die are offset in a first direction so that the pads on the surfaces of the plurality of dies are exposed. The first direction is perpendicular to the stacking direction of the plurality of dies.

[0124] In step 102, metal wires are formed on the surfaces of the plurality of die using a 3D printing method, and the metal wires are used to electrically connect corresponding pads on the surfaces of the plurality of die.

[0125] In practical applications, the material forming the metal wire may include copper, silver, and titanium, but is not limited thereto.

[0126] In one embodiment, the metal wire is a copper wire, which has lower cost than the traditional wire bonding process using gold wire.

[0127] In practical applications, when the metal wires are formed on the surfaces of the multiple bare chips by 3D printing, compared with the traditional wire bonding process, the metal wires are in direct contact with the bare chips, so they have better heat dissipation performance. When the metal wires are formed by 3D printing, the stacked structure formed by the multiple bare chips is not affected by the wire arc, and the package thickness can be thinner and tighter, thereby increasing the area of ​​the bare chips in the stacked structure under the same package size. The metal wires on the multiple bare chips are formed at one time and do not need to be printed multiple times. It can be understood that even if the number of the multiple bare chips is increased, the printing of the metal wires can be completed at one time. In addition, compared with the traditional packaging process, the packaging method of 3D printing metal wires has a relatively short metal wire path, so the formed semiconductor device has better high-frequency performance.

[0128] In one embodiment, before forming the metal line, the process further includes pre-processing the surface of the die.

[0129] Specifically, oxides and organic matter on the test pad are removed by plasma or laser treatment, and the surface of the die is roughened to increase the activation energy of the die surface, so as to facilitate subsequent 3D printing.

[0130] In practical applications, such as Figure 4a As shown, the die surface includes organic contaminants; Figure 4b As shown, oxygen plasma is used to pre-treat the surface of the die to ashed the organic matter on the surface of the die. Specifically, the organic matter on the surface of the die mainly generates carbon monoxide and carbon dioxide gas under the action of oxygen plasma. The pre-treated die is as shown in FIG. Figure 4c After the bare chip is treated by plasma, the organic matter on the surface is ashed and the hydrophilicity is good.

[0131] In practical applications, such as Figure 5a As shown, the die surface includes oxide near the die surface; Figure 5b As shown, oxygen plasma is used to pre-treat the surface of the die to remove oxides on the surface of the die. Specifically, the oxides on the surface of the die mainly generate water under the action of oxygen plasma; the pre-treated die is as follows Figure 5c After the bare chip is treated with plasma, there is no residual oxide on the surface, and the hydrophilicity is good; at the same time, the surface of the bare chip is roughened, and the activation energy of the bare chip surface is increased, which is conducive to subsequent 3D printing.

[0132] In one embodiment, the forming of metal wires on the surfaces of the plurality of bare chips by 3D printing includes: printing the metal wires by metal powder by 3D printing. Preferably, after printing the metal wires by metal powder, the method further includes sintering the metal wires at low temperature.

[0133] In one embodiment, the forming of metal lines on the surfaces of the plurality of bare chips by using a 3D printing method includes: using a 3D printing method to print metal lines using a metal solution, and performing low temperature sintering on the metal lines to obtain the metal lines.

[0134] Here, the low temperature sintering temperature is lower than the temperature at which the die warps. In one embodiment, the low temperature sintering temperature is about 100° C. to 150° C. It is understood that after the metal lines are formed using the metal solution, a sintering process must be performed to allow the metal ions in the metal solution to precipitate to form the metal lines.

[0135] In one embodiment, the method of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method includes: forming a metal layer on the surfaces of the plurality of bare chips; printing a mask layer at a position on the surface of the metal layer where the metal lines are not required by using a 3D printing method; performing electroless nickel immersion gold coating on the metal layer that is not blocked by the mask layer. ， ENIG) treatment; removing the mask layer and the metal layer blocked by the mask layer to form the metal line.

[0136] In one embodiment, the use of 3D printing to form metal wires on the surfaces of the multiple bare chips includes: forming a metal layer on the surfaces of the multiple bare chips; printing a mask layer at a position on the surface of the metal layer where the metal wires need to be formed by using 3D printing; and removing the metal layer and the mask layer that are not blocked by the mask layer to form the metal wires.

[0137] In practical applications, the mask layer may include photoresist, but is not limited thereto.

[0138] It should be noted that, in the above-mentioned embodiments, the shapes and positions of the plurality of bare chip surface mask layers are determined according to the design of the metal wires and the selected 3D printing process.

[0139] In one embodiment, after forming the metal line, the surface of the die is cleaned.

[0140] In practical applications, after the metal wires are formed by 3D printing, some contaminants such as metal materials may remain on the surface of the die, so the surface of the die needs to be cleaned. Specifically, the cleaning process includes treating the contaminants with oxygen plasma or laser.

[0141] In one embodiment, after the metal line is formed, a line type treatment is performed on the metal line.

[0142] In practical applications, after the metal wire is formed by 3D printing, the metal wire may be bent or otherwise not in accordance with the requirements, so the metal wire needs to be processed in a linear manner. Specifically, oxygen plasma or laser is used to process the metal wire to remove the redundant parts of the metal wire.

[0143] In one embodiment, if Figure 6 As shown, the metal wire includes a first metal wire layer 31 and a second metal wire layer 32 which are stacked; the method of forming the metal wire on the surface of the plurality of bare chips 201 by using the 3D printing method includes: forming the first metal wire layer 31 on the surface of the plurality of bare chips 201 by using the 3D printing method; forming a first insulating layer 33 on the first metal wire layer 31 by using the 3D printing method; forming the second metal wire layer 32 on the insulating layer 33 by using the 3D printing method; wherein the first metal wire in the first metal wire layer 31 and the second metal wire in the second metal wire layer 32 are electrically connected through contact between one end of the first metal wire and the corresponding end of the second metal wire.

[0144] In practical applications, the material of the first insulating layer 33 may include polyimide (PI), but is not limited thereto.

[0145] In practical applications, such as Figure 6 As shown, the second metal wire layer 32 completely covers the first metal wire layer 31, one end of the second metal wire in the second metal wire layer 32 is connected to the pad 200 on the die 201, and the other end is electrically connected through contact with the corresponding end of the first metal wire, thereby realizing electrical interconnection between the first metal wire layer 31, the second metal wire layer 32 and the plurality of die. It can be understood that the electrical interconnection between the first metal wire layer 31, the second metal wire layer 32 and the plurality of die 201 can be realized through the reasonable arrangement of the first metal wire layer 31 and the second metal wire layer 32, so that there is no need to occupy additional packaging space and increase the process. In other words, when the metal wire is formed by 3D printing, the packaging process is simplified and the packaging size is reduced by the wiring method of metal wire stacking design and the stacking is separated by adding an insulating layer.

[0146] In one embodiment, a PI layer is formed on the first metal wire layer 31 by a 3D printing method. Specifically, a liquid PI resin is formed on the first metal wire layer 31 by a 3D printing method, and the liquid PI resin is baked and cured to obtain the PI layer. In practical applications, after the PI layer is formed by 3D printing, the die is cleaned to remove the residual PI material and other contaminants on the surface of the die.

[0147] In one embodiment, if Figure 7As shown, the multiple bare chips 201 are stacked in a stepped shape, and a plurality of pads 200 are arranged on the exposed step surface of each bare chip 201 in the multiple bare chips 201; the metal wires 300 are formed on the surfaces of the multiple bare chips 201 by using the 3D printing method, including: forming a plurality of metal wires 300 on the surfaces of the multiple bare chips 201; wherein each of the plurality of metal wires 300 connects the pads 200 on the corresponding adjacent bare chips 201 on different step surfaces.

[0148] Here, the pads 200 on each die 201 are connected to the pads 200 corresponding to the adjacent die 201, and the metal wires 300 do not need to span across multiple step surfaces. It is understandable that each pad 200 on each die 201 needs to be connected to the metal wires 300, and the metal wires 300 do not need jumpers.

[0149] In practical applications, after the plurality of dies 201 are stacked, the metal wires 300 on the plurality of dies 201 can be formed at one time without multiple printings. It is understandable that even if the number of the plurality of dies 201 is increased, the metal wires 300 can be printed at one time.

[0150] In one embodiment, if Figure 8 As shown, the multiple bare chips 201 are stacked in a stepped shape, and a plurality of pads 200 are arranged on the exposed step surface of each bare chip 201 in the multiple bare chips 201; the metal wires 300 are formed on the surfaces of the multiple bare chips 201 by using the 3D printing method, including: forming a plurality of metal wires 300 on the surfaces of the multiple bare chips 201; wherein at least one metal wire 300 spans across the multiple step surfaces to connect the pads 200 on the corresponding spaced bare chips 201 on different step surfaces.

[0151] Here, the spacer die 201 can be understood as the corresponding die 201 on two different step surfaces, and the two different steps contain at least one or more steps in between, that is, in the direction in which the multiple die 201 are stacked, the spacer die 201 contains at least one or more die 201.

[0152] In practical applications, when the pads 200 on some of the bare chips 201 do not need to be electrically connected, the metal wire 300 can cross over the pads 200 on the multiple step surfaces and connect to the pads 200 corresponding to the spaced bare chips 201. It is understandable that the metal wire 300 does not need to be connected to each pad 200 on each bare chip 201, and the metal wire 300 can pass between the pads 200 when a jumper is required.

[0153] In one embodiment, if Fig. 9As shown, the multiple bare chips 201 include a first bare chip group 201A offset along a first direction and a second bare chip group 201B offset along a second direction; the first direction and the second direction are both perpendicular to the direction in which the multiple bare chips 201 are stacked; the first direction is different from the second direction; the use of 3D printing to form metal wires 300 on the surfaces of the multiple bare chips 201 includes: forming multiple metal wires 300 on the surfaces of the multiple bare chips 201; wherein at least one metal wire 300 includes a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; and the pads 200 on the corresponding spacer bare chips 201 on different step surfaces are connected through the first portion and the second portion.

[0154] It should be noted that in the above-mentioned multiple embodiments, the layout of the metal wires on the surfaces of the multiple bare chips is designed according to the circuit requirements of the semiconductor device, and the layout of the metal wires can be performed by reasonably offsetting the multiple bare chips when necessary. That is to say, when the multiple bare chips are stacked, the stacking method of the multiple bare chips is adjusted according to the layout of the metal wires, that is, the offset and offset direction of each bare chip in the multiple bare chips are adjusted according to the layout of the metal wires. It can be understood that by stacking the multiple bare chips in an offset manner, a reasonable line space can be reserved for the metal wires.

[0155] In one embodiment, the stacked multiple bare chips are formed on the first surface of the semiconductor substrate; after forming metal wires on the surfaces of the multiple bare chips using a 3D printing method, a plastic encapsulation layer covering the semiconductor substrate, the multiple bare chips and the metal wires is formed; and multiple metal solder balls are formed on the second surface of the semiconductor substrate; the second surface is the opposite side of the first surface.

[0156] In one embodiment, after forming the plastic encapsulation layer, printing is further included; after forming the plurality of metal solder balls, the plurality of stacked bare chips on the semiconductor substrate are cut to obtain semiconductor devices.

[0157] It should be noted that, although an exemplary chip packaging method is described herein, it is understandable that one or more steps may be omitted from the chip packaging process.

[0158] Based on the above chip packaging method, an embodiment of the present invention further provides a chip packaging structure. Fig.10a A schematic cross-sectional view of a chip packaging structure provided by an embodiment of the present invention, Fig.10b for Fig.10a The enlarged schematic diagram of point C in the figure. Fig.10aAs shown, the packaging structure includes: the stacked multiple bare chips 201 are offset between the multiple bare chips 201, so that the pads 200 on the surfaces of the multiple bare chips 201 are all exposed; the surfaces of the multiple bare chips 201 include metal wires 300 formed by 3D printing, and the metal wires 300 are used to electrically connect the corresponding pads 200 on the surfaces of the multiple bare chips 201.

[0159] In practical applications, such as Fig.10a As shown, each of the plurality of dies 201 includes a second insulating layer 208 on the side and bottom; wherein the second insulating layer 208 includes a second insulating layer 208A on the side of each die 201 and a second insulating layer 208B on the bottom, and the second insulating layer 208A on the side of each die 201 includes a first insulating material 204; Fig.10b As shown, the second insulating layer 208B on the bottom surface of each bare chip 201 includes a first insulating material 204 and a second insulating material 209. In practical applications, the first insulating material 204 includes an ABF film; the second insulating material 204 includes a DAF film. It can be understood that the second insulating layer 208 plays an insulating and side protection role on the one hand, and on the other hand, can increase the mechanical strength of the bare chip 201, so that the formed semiconductor device has better reliability.

[0160] In one embodiment, if Fig.10a As shown, the stacked multiple bare chips 201 are located on the first surface of the semiconductor substrate 20; the packaging structure also includes a plastic layer 34, and the plastic layer 34 covers the semiconductor substrate 20, the multiple bare chips 201 and the metal wire 300; the second surface of the semiconductor substrate 20 also includes a plurality of metal solder balls 35; the second surface is the opposite side of the first surface.

[0161] In practical applications, the plastic packaging layer 34 includes EMC plastic, but is not limited thereto.

[0162] In one embodiment, if Figure 6 As shown, the multiple bare chips 201 are stacked in a step shape, and a plurality of pads 200 are arranged on the exposed step surface of each bare chip 201 in the multiple bare chips 201; the surfaces of the multiple bare chips 201 include a first metal wire layer 31 and a second metal wire layer 32 arranged in a stacked manner; a first insulating layer 33 is also included between the first metal wire layer 31 and the second metal wire layer 32; the first metal wire in the first metal wire layer 31 and the second metal wire in the second metal wire layer 32 are electrically connected through the contact between one end of the first metal wire and the corresponding end of the second metal wire.

[0163] It is understandable that the electrical interconnection between the first metal wire layer 31, the second metal wire layer 32 and the plurality of bare chips 201 can be achieved by properly arranging the first metal wire layer 31 and the second metal wire layer 32, thereby eliminating the need to occupy additional packaging space and increase process flow. In other words, when metal wires are formed by 3D printing, the packaging process is simplified and the packaging size is reduced by designing metal wire stacks and spacing the stacks by adding insulating layers.

[0164] In one embodiment, if Figure 7 As shown, the multiple bare chips 201 are stacked in a stepped shape, and a plurality of pads 200 are arranged on the exposed step surface of each bare chip 201 in the multiple bare chips 201; the surfaces of the multiple bare chips 200 include a plurality of metal wires 300, and each of the multiple metal wires 300 connects the pads 200 on the corresponding adjacent bare chips 201 on different step surfaces.

[0165] Here, the pads 200 on each die 201 are connected to the pads 200 corresponding to the adjacent die 201, and the metal wires 300 do not need to span across multiple step surfaces. It is understandable that each pad 200 on each die 201 needs to be connected to the metal wires 300, and the metal wires 300 do not need jumpers.

[0166] In practical applications, after the plurality of dies 201 are stacked, the metal wires 300 on the plurality of dies 201 can be formed at one time without multiple printings. It is understandable that even if the number of the plurality of dies 201 is increased, the metal wires 300 can be printed at one time.

[0167] In one embodiment, if Figure 8 As shown, the multiple bare chips 201 are stacked in a stepped shape, and a plurality of solder pads 200 are arranged on the exposed step surface of each bare chip 201 in the multiple bare chips 201; the surfaces of the multiple bare chips 201 include a plurality of metal wires 300, at least one metal wire 300 spans across the multiple step surfaces, and the solder pads 200 on the corresponding spaced bare chips 201 on different step surfaces are connected via the at least one metal wire 300.

[0168] In practical applications, when the pads 200 on some of the bare chips 201 do not need to be electrically connected, the metal wire 300 can cross over the pads 200 on the multiple step surfaces and connect to the pads 200 corresponding to the spaced bare chips 201. It is understandable that the metal wire 300 does not need to be connected to each pad 200 on each bare chip 201, and the metal wire 300 can pass between the pads 200 when a jumper is required.

[0169] In one embodiment, if Fig. 9As shown, the multiple bare chips 201 include a first bare chip group 201A offset along a first direction and a second bare chip group 201B offset along a second direction; the first direction and the second direction are both perpendicular to the direction in which the multiple bare chips 201 are stacked; the first direction is different from the second direction; the surfaces of the multiple bare chips 201 include multiple metal wires 300; wherein at least one metal wire 300 includes a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; the pads 200 on the corresponding spacer bare chips 201 on different step surfaces are connected through the first portion and the second portion.

[0170] The chip packaging method and structure provided by the embodiment of the present invention include: providing a plurality of stacked bare chips; wherein, by offsetting the plurality of bare chips, the pads on the surfaces of the plurality of bare chips are exposed; and forming metal wires on the surfaces of the plurality of bare chips by 3D printing, wherein the metal wires are used to electrically connect the corresponding pads on the surfaces of the plurality of bare chips. The chip packaging method and structure of the embodiment of the present invention adopts 3D printing technology to replace the traditional packaging technology, and has the following advantages: (1) The stacking structure can be more compact, thereby increasing the area of ​​the bare chips in the stacking structure under the same packaging size; (2) The metal wires are formed at one time and do not need to be printed multiple times; (3) The packaging thickness can be thinner without being affected by wire arcs; (4) The metal wires are in direct contact with the bare chips, and have better heat dissipation performance; (5) Compared with the traditional packaging technology, the packaging method of 3D printing metal wires has a relatively short metal wire path, so the formed semiconductor device has better high-frequency performance.

[0171] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A chip packaging method, characterized in that: include: Providing a plurality of stacked dies; wherein pads on the surfaces of the plurality of dies are exposed by offsetting the plurality of dies; A three-dimensional 3D printing method is used to form metal wires on the surfaces of the multiple bare chips, and the metal wires are used to electrically connect the corresponding pads on the surfaces of the multiple bare chips; wherein the metal wires include a first metal wire layer and a second metal wire layer that are stacked, a first insulating layer is included between the first metal wire layer and the second metal wire layer, and a first metal wire in the first metal wire layer is electrically connected to a second metal wire in the second metal wire layer through contact between one end of the first metal wire and the corresponding end of the second metal wire.

2. The chip packaging method according to claim 1, characterized in that: The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: The metal wire is printed using metal powder by 3D printing; or, The 3D printing method is adopted to print metal lines using a metal solution; and the metal lines are sintered to obtain the metal lines.

3. The chip packaging method according to claim 1, characterized in that: The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: forming a metal layer on the surfaces of the plurality of dies; Printing a mask layer at a position on the surface of the metal layer where no metal wire is needed by using a 3D printing method; Performing chemical nickel-gold treatment on the metal layer not blocked by the mask layer; removing the mask layer and the metal layer blocked by the mask layer to form the metal wire.

4. The chip packaging method according to claim 1, characterized in that: The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: forming a metal layer on the surfaces of the plurality of dies; Printing a mask layer at a position where a metal line needs to be formed on the surface of the metal layer by a 3D printing method; The metal layer and the mask layer that are not blocked by the mask layer are removed to form the metal line.

5. The chip packaging method according to claim 1, characterized in that: The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: Forming the first metal wire layer on the surfaces of the plurality of bare chips by using a 3D printing method; forming a first insulating layer on the first metal wire layer by using a 3D printing method; A second metal wire layer is formed on the insulating layer by using a 3D printing method.

6. The chip packaging method according to claim 1, characterized in that: The plurality of dies are stacked in a step-like manner, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies; The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: A plurality of metal lines are formed on the surfaces of the plurality of dies; wherein each of the plurality of metal lines respectively connects pads on corresponding adjacent dies on different step surfaces.

7. The chip packaging method according to claim 1, characterized in that: The plurality of dies are stacked in a step-like manner, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies; The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: A plurality of metal lines are formed on the surfaces of the plurality of dies; wherein at least one metal line crosses over the plurality of step surfaces to connect pads on corresponding spaced dies on different step surfaces.

8. The chip packaging method according to claim 1, characterized in that: The plurality of dies include a first die group offset along a first direction and a second die group offset along a second direction; the first direction and the second direction are both perpendicular to a direction in which the plurality of dies are stacked; the first direction is different from the second direction; The step of forming metal lines on the surfaces of the plurality of bare chips by using a 3D printing method comprises: A plurality of metal lines are formed on the surfaces of the plurality of bare chips; wherein at least one metal line includes a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; and pads on corresponding spaced bare chips on different step surfaces are connected through the first portion and the second portion.

9. The chip packaging method according to claim 1, characterized in that: The method provides a plurality of stacked dies, comprising: Provide multiple dies; forming a second insulating layer on the side surface and the bottom surface of each die in the plurality of dies; A plurality of bare chips formed with the second insulating layer are stacked.

10. The chip packaging method according to claim 9, characterized in that: The second insulating layer is formed on the side surface and the bottom surface of each bare chip in the plurality of bare chips, comprising: Separating a plurality of bare chips by a dicing path; a spacing between the separated plurality of bare chips is a width of the dicing path; forming a first insulating material covering bottom surfaces of the plurality of dies; Pressing a portion of the first insulating material into the gaps between the plurality of dies to form a second insulating layer covering the side surface of each of the plurality of dies; Forming a second insulating material covering the remaining first insulating material on the bottom surfaces of the plurality of bare chips; the first insulating material on the side surface of each bare chip and the first insulating material and the second insulating material on the bottom surface form the second insulating layer; The second insulating layer in the gaps between the plurality of dies is cut to obtain a plurality of separated dies.

11. The chip packaging method according to claim 10, characterized in that: The method further comprises: Before forming the first insulating material covering the bottom surfaces of the plurality of dies, rearrange the plurality of dies on the carrier so as to increase the spacing between the plurality of dies; After forming a second insulating material covering the remaining first insulating material on bottom surfaces of the plurality of dies, the carrier is removed.

12. The chip packaging method according to claim 1, characterized in that: The method further comprises: forming the stacked plurality of dies on a first surface of a semiconductor substrate; After forming metal wires on the surfaces of the plurality of bare chips by a 3D printing method, forming a plastic packaging layer covering the semiconductor substrate, the plurality of bare chips and the metal wires; A plurality of metal solder balls are formed on the second surface of the semiconductor substrate; the second surface is the opposite surface of the first surface.

13. The chip packaging method according to claim 1, characterized in that: The method further comprises: Before forming the metal line, a first plasma treatment is performed on the die surface to remove oxide on the pad and roughen the die surface.

14. The chip packaging method according to claim 1, characterized in that: The method further comprises: After forming the metal lines, a second plasma treatment is performed on the surface of the die to remove residues from 3D printing.

15. A chip packaging structure, characterized in that: The packaging structure includes a packaging structure prepared by the chip packaging method according to any one of claims 1 to 14.

16. The packaging structure according to claim 15, characterized in that: The plurality of dies are stacked in a step-like manner, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies; A plurality of metal lines are disposed on the surfaces of the plurality of dies, and each of the plurality of metal lines respectively connects pads on corresponding adjacent dies on different step surfaces.

17. The packaging structure according to claim 15, characterized in that: The plurality of dies are stacked in a step-like manner, and a plurality of pads are arranged on the exposed step surface of each of the plurality of dies; A plurality of metal lines are arranged on the surfaces of the plurality of bare chips, at least one metal line spans across a plurality of step surfaces, and pads on corresponding spaced bare chips on different step surfaces are connected via the at least one metal line.

18. The packaging structure according to claim 15, characterized in that: The plurality of dies include a first die group offset along a first direction and a second die group offset along a second direction; the first direction and the second direction are both perpendicular to a direction in which the plurality of dies are stacked; the first direction is different from the second direction; A plurality of metal lines are arranged on the surfaces of the plurality of bare chips; wherein at least one metal line comprises a first portion spanning the step surface along the first direction and a second portion spanning the step surface along the second direction; and pads on corresponding spaced bare chips on different step surfaces are connected via the first portion and the second portion.

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