A transistor chip structure with high antistatic ability

Abstract

The invention discloses a transistor chip structure with high antistatic ability, comprising two MOS structures and a capacitor structure, wherein the two MOS structures both comprise a substrate layer, a first conductive layer, a heavily doped first conductive layer, a second conductive layer, an insulating layer, a polysilicon layer, a silicon nitride insulating layer, a PSG layer and a metal electrode layer, wherein the source or drain of the first-level MOS structure of the two MOS structures serves as the gate of the second-level MOS structure, a parallel diode is arranged between the gate of the first MOS and a common ground electrode, and one end of the parallel diode is connected to the gate electrode of the first MOS structure, and the other end is connected to the ground electrode, and by reversely connecting a diode in parallel in a traditional 2T1C driver chip, the driver chip can better withstand the impact of static electricity during processing and transfer, thereby increasing the yield rate of a display unit, improving the display effect, making full use of the MOS structure space, and the process flow and manufacturing process are completely consistent with the original MOS manufacturing process, which will not lead to cost increase and has obvious advantages.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor chips, and in particular relates to a transistor chip structure with high antistatic capability. Background Art

[0002] At present, 2T1C and other circuits have been widely used as drivers in LCD, OLED and other display fields to control the brightness of pixels and thus realize image display. However, conventional 2T1C and other circuits are not designed with anti-static protection. They are easily damaged by static electricity during chip operation and use, causing chip failure. Especially in the fields of Mini LED and Micro LED display, a large number of driver chips need to be transferred to the substrate during the product manufacturing process. The low anti-static ability of the driver chip will directly affect the yield of the finished product and cause product failure. Summary of the invention

[0003] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a transistor chip structure with high antistatic ability, which solves the problem that conventional 2T1C and other circuits do not have antistatic protection design, and are easily damaged by static electricity during chip operation and use, resulting in chip failure. Especially in the fields of Mini LED and Micro LED display, a large number of driver chips need to be transferred to the substrate during the product manufacturing process. The low antistatic ability of the driver chip will directly affect the yield of the finished product and cause product failure.

[0004] To achieve the above-mentioned purpose, the present invention provides the following technical solution (taking NMOS of N-type substrate as an example): a transistor chip structure with high antistatic ability, including two MOS structures and a capacitor structure, the two MOS structures both include a substrate layer, a first conductive layer, a heavily doped first conductive layer, a second conductive layer, an insulating layer, a polysilicon layer, a silicon nitride insulating layer, a PSG layer and a metal electrode layer, the two MOS structures wherein the source or drain of the first-level MOS structure serves as the gate of the second-level MOS structure, a parallel diode is arranged between the gate of the first MOS and a common ground electrode, and one end of the parallel diode is connected to the gate electrode of the first MOS structure, and the other end is connected to the ground electrode.

[0005] Preferably, the first conductive layer, the heavily doped first conductive layer and the second conductive layer are prepared with high temperature polysilicon or single crystal silicon as the main material, and the substrate material can be a conductive material, in which case the conductive property of the semiconductor of the first conductive layer is opposite to that of the substrate; in addition, the substrate material can also be an insulating material, in which case the first conductive layer can be an N-type or P-type semiconductor; the carrier concentration of the second conductive layer is 5×10 18 ~5×10 19 cm -3The impurity ion concentration of the heavily doped first conductive layer is 5×10 18 ~2×10 20 cm -3 .

[0006] Preferably, the diode is arranged in a region between the MOS structure gate and a common ground electrode.

[0007] Preferably, the first electrode of the diode is a common ground electrode, and the doping type of the semiconductor layer connected to the first electrode of the diode is opposite to the doping type of the semiconductor layer in the source and drain region of the MOS structure, and can be manufactured by ion implantation or in-situ doping.

[0008] Preferably, the electrode at the other end of the diode is connected to the gate electrode of the first-level MOS structure (i.e., the scanning transistor), the conductive properties of the semiconductor layer connected thereto are the same as the conductive properties of the source and drain layer semiconductor of the MOS structure, and the semiconductor layer connected to the first electrode of the diode forms a pn junction.

[0009] Compared with the prior art, the present invention has the following beneficial effects:

[0010] The present invention connects a diode in reverse parallel to the traditional 2T1C driver chip, so that the driver chip can better withstand the impact of static electricity during processing and transfer, thereby increasing the yield rate of the display unit and improving the display effect; at the same time, the structure and method proposed by the present invention fully utilize the MOS structure space, and the process flow and manufacturing process are completely consistent with the original MOS manufacturing process, which will not lead to cost increase and has obvious advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic cross-sectional view of the NMOS structure of the N-type substrate of the present invention;

[0012] Figure 2 It is a schematic diagram of the structural principle of the circuit of the present invention.

[0013] In the figure: 1. substrate layer; 2. first conductive layer; 3. heavily doped first conductive layer; 4. second conductive layer; 5. insulating layer; 6. polysilicon layer; 7. silicon nitride insulating layer; 8. PSG layer; 9. metal electrode layer. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] like Figure 1-Figure 2 As shown, a transistor chip structure with high antistatic ability includes two MOS structures and a capacitor structure. The two MOS structures include a substrate layer 1, a first conductive layer 2, a heavily doped first conductive layer 3, a second conductive layer 4, an insulating layer 5, a polysilicon layer 6, a silicon nitride insulating layer 7, a PSG layer 8 and a metal electrode layer 9. In the two MOS structures, the source or drain of the first-level MOS structure serves as the gate of the second-level MOS structure. A parallel diode is arranged between the gate of the first MOS and a common ground electrode, and one end of the parallel diode is connected to the gate electrode of the first MOS structure, and the other end is connected to the ground electrode. The first conductive layer 2, the heavily doped first conductive layer 3 and the second conductive layer 4 are prepared with high-temperature polysilicon or single-crystal silicon as the main material, and the substrate material can be a conductive material. At this time, the conductive property of the first conductive layer semiconductor is opposite to that of the substrate; in addition, the substrate material can also be an insulating material. At this time, the first conductive layer 2 can be an N-type or P-type semiconductor; the carrier concentration of the second conductive layer 4 is 5×10 18 ~5×10 19 cm -3 , the impurity ion concentration of the heavily doped first conductive layer 3 is 5×10 18 ~2×10 20 cm -3 The diode is arranged in the area between the gate of the MOS structure and the common ground electrode. The first electrode of the diode is the common ground electrode, and the doping type of the semiconductor layer connected to the first electrode of the diode is opposite to the doping type of the semiconductor layer in the source and drain area of ​​the MOS structure. It can be manufactured by ion implantation or in-situ doping and other processes. The other end electrode of the diode is connected to the gate electrode of the first-level MOS structure, i.e., the scanning transistor. The conductive property of the semiconductor layer connected to it is the same as the conductive property of the source and drain layer semiconductor of the MOS structure. The semiconductor layer connected to the first electrode of the diode forms a pn junction. The semiconductor layer can be manufactured synchronously with the source and drain doping process. By adjusting the spatial distance between the semiconductor layer and the above-mentioned semiconductor layer, the antistatic ability and voltage resistance of the diode can be adjusted to ensure that the diode can protect the MOS structure by ensuring normal operation according to the working conditions of this structure.

[0016] The working principle of the above technical solution is as follows:

[0017] The present invention connects a diode in reverse parallel to the traditional 2T1C driver chip, so that the driver chip can better withstand the impact of static electricity during processing and transfer, thereby increasing the yield rate of the display unit and improving the display effect; at the same time, the structure and method proposed by the present invention fully utilize the MOS structure space, and the process flow and manufacturing process are completely consistent with the original MOS manufacturing process, which will not lead to cost increase and has obvious advantages.

[0018] The working principle and use process of the present invention are as follows: the MOS structure is manufactured, firstly, the first conductive layer 2 is implanted on the substrate layer 1, then field oxygen is manufactured, and photolithography and etching are performed, then the first conductive layer 3 is heavily doped by photolithography, and ion implantation is performed, then the capacitor area is photolithography, the second conductive layer 4 is N-type ion implanted, and then the polysilicon layer 6 is manufactured, the polysilicon 6 is deposited, and etching is performed, and finally the PSG layer 8 and through-hole etching are performed, and metal is deposited to form a metal electrode layer 9 for easy electrical connection. By reversely connecting a diode in parallel in the traditional 2T1C driver chip, the driver chip can better withstand the impact of static electricity during processing and transfer, thereby improving the yield rate of the display unit and improving the display effect; at the same time, the structure and method proposed by the present invention make full use of the MOS structure space, and the process flow and manufacturing process are completely consistent with the original MOS manufacturing, which will not lead to cost increase and has obvious advantages.

[0019] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made thereto without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A transistor chip structure with high antistatic capability, comprising two MOS structures and a capacitor structure, characterized in that: The two MOS structures each comprise a substrate layer (1), a first conductive layer (2), a heavily doped first conductive layer (3), a second conductive layer (4), an insulating layer (5), a polysilicon layer (6), a silicon nitride insulating layer (7), a PSG layer (8) and a metal electrode layer (9); in the two MOS structures, a source or a drain of the first-level MOS structure serves as a gate of the second-level MOS structure; a parallel diode is arranged between the gate of the first-level MOS and a common ground electrode; one end of the parallel diode is connected to the gate electrode of the first MOS structure, and the other end is connected to the ground electrode; The first electrode of the diode is a common ground electrode, and the doping type of the semiconductor layer connected to the first electrode of the diode is opposite to the doping type of the semiconductor layer in the source and drain regions of the MOS structure, and is manufactured by ion implantation or in-situ doping process; The other end electrode of the diode is connected to the gate electrode of the first-level MOS structure, the conductive property of the semiconductor layer connected to it is the same as the conductive property of the source and drain layer semiconductor of the MOS structure, and the semiconductor layer connected to the first electrode of the diode forms a pn junction; The first conductive layer (2), the heavily doped first conductive layer (3) and the second conductive layer (4) are prepared using high temperature polysilicon or single crystal silicon as the main material, and the substrate material is a conductive material, in which case the conductive properties of the semiconductor of the first conductive layer are opposite to those of the substrate; or the substrate material is an insulating material, in which case the first conductive layer (2) is an N-type or P-type semiconductor.

2. The transistor chip structure with high antistatic capability according to claim 1, characterized in that: The carrier concentration of the second conductive layer (4) is 5×10 18 ~5×10 19 cm -3 The impurity ion concentration of the heavily doped first conductive layer (3) is 5×10 18 ~2×10 20 cm -3 .

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