Brain electrode device and preparation method thereof

Abstract

The present invention relates to the field of brain electrode technology, and the present invention discloses a brain electrode device and a preparation method thereof. The brain electrode device comprises a signal acquisition chip, a brain electrode structure and a circuit board, wherein the signal acquisition chip is arranged on the circuit board, and the signal acquisition chip can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board, and the pad area of ​​the signal acquisition chip is connected to the pad structure of the brain electrode structure by flip-chip welding, and the brain electrode structure is used to collect brain electrical signals. The brain electrode device provided by the present application has the advantages of high integration and high signal transmission quality.

Description

Technical Field

[0001] The present invention relates to the technical field of brain electrodes, and in particular to a brain electrode device and a preparation method thereof. Background Art

[0002] Brain-computer interface is a multidisciplinary cross-technology involving neuroscience, signal detection and signal processing, and has important research significance and huge application potential in the fields of biomedicine, neurorehabilitation and intelligent robotics. It establishes a direct communication and control channel between the human brain and a computer or other electronic device, collects EEG signals from the cerebral cortex, and converts them into signals that can be recognized by the computer through amplification, filtering, A / D conversion, etc., then pre-processes the signals, extracts characteristic signals, and then uses these characteristics for pattern recognition, and finally converts them into specific instructions to control external devices, thereby achieving control of external devices.

[0003] Neuroelectrophysiological monitoring plays an irreplaceable role in brain science research and brain disease diagnosis. High-quality neuroelectrophysiological signal acquisition technology is the basis for the smooth development of basic brain science research and clinical research on brain diseases in China. The method of collecting neuroelectrophysiological signals mainly relies on brain-computer interface. According to the way of information acquisition, it is usually divided into non-invasive, semi-invasive and invasive. These three different types have their own advantages and limitations. Non-invasive scalp electrodes are directly attached to the scalp without surgery, but due to the attenuation of the skull, the collected EEG signals are inaccurate; semi-invasive cortical electrodes are attached to the cortex, and the EEG signals are more accurate; invasive deep electrodes are directly implanted deep in the brain, and the collected EEG signals are the most accurate. Stereo EEG signals can be collected, minimally invasive implantation, and long-term implantable deep electrodes are gradually becoming one of the mainstream technologies of brain-computer interfaces in the future.

[0004] In general, the signals collected by the electrodes can be transmitted from the body to external hardware using Omnetics / micro-nano connectors, fixed to the skull, or percutaneous wires. However, these interfaces have the risk of persistent infection, so researchers have proposed wireless communications based on antenna-based radio frequency technology, inductive coupling, electrical coupling and capacitive coupling IBC, ultrasound, light, molecular nanonetworks and other methods. Despite this, affected by power supply and bandwidth, the lifespan and number of channels of wireless implants are still a major difficulty. Therefore, the main communication method between thousands or even tens of thousands of EEG devices and the back end is still wired connection.

[0005] Currently, brain electrode devices are first soldered to a printed circuit board, and then connected to a commercially available processing circuit board through a matching interface. After preliminary amplification on the signal processing circuit board, they are sent to a computer via a cable, thus completing the entire process of EEG signal collection and processing.

[0006] The above-mentioned way of transmitting signals is to use a flexible cable. By manufacturing the probe base and the electrode insertion end together on a single chip, data can be directly transmitted from the probe to the processing end through a flexible cable, and 384 channels can be transmitted at present. The good flexibility of this method provides great convenience for subsequent animal experiments, but this method requires the voltage signal to be filtered, amplified, multiplexed and digitized on the electrode substrate to produce a noise-free digital signal. Otherwise, the unprocessed signal will be susceptible to noise interference during the transmission of the cable, affecting the accuracy of the data; and the number of channels that can be connected by the flexible cable is also limited. To achieve thousands or even tens of thousands of brain electrode channels, multiple cables need to be assembled. This connection method is not only cumbersome and complicated, but also has a low degree of integration. In addition, there is a "micro-motion" effect, which is the independent movement of the implant relative to the brain, which will cause tissue wear. Eliminating the interface cable can reduce this effect. Summary of the invention

[0007] The present invention aims to solve the technical problems of the prior art that signal processing is performed on an electrode substrate and signal transmission is performed using cables, resulting in a small number of channels and low integration.

[0008] In order to solve the above technical problems, the present application discloses, on one hand, a brain electrode device, which includes a signal acquisition chip, a brain electrode structure and a circuit board;

[0009] The signal acquisition chip is arranged on the circuit board, and the signal acquisition chip can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board;

[0010] The pad area of ​​the signal acquisition chip is connected to the pad structure of the brain electrode structure by flip-chip bonding;

[0011] The brain electrode structure is used to collect brain electrical signals.

[0012] Optionally, a first solder point array is provided on the pad area;

[0013] The pad structure is provided with a second soldering point array corresponding to the first soldering point array.

[0014] Optionally, the brain electrode structure includes a contact electrode structure connected to the pad structure;

[0015] The contact electrode structure collects EEG signals by contacting the scalp layer;

[0016] The contact electrode structure is any one of non-invasive, semi-invasive and invasive types.

[0017] Optionally, the signal acquisition chip is located in the first area of ​​the circuit board;

[0018] The first area is close to the end of the circuit board;

[0019] The contact electrode structure can extend out of the end of the circuit board to contact the scalp layer.

[0020] Optionally, the contact electrode structure includes a flexible support layer, an electrode line structure and an insulating layer;

[0021] The electrode line structure is arranged on the flexible supporting layer;

[0022] The electrode line structure includes an electrode line and a contact electrode;

[0023] One end of the electrode line is connected to the contact electrode, and the other end of the electrode line is connected to the welding point of the pad structure;

[0024] The insulating layer is disposed on the electrode line structure, and the insulating layer includes an electrode hole, and the electrode hole is used to expose the contact electrode.

[0025] Optionally, the material of the contact electrode includes chromium / gold, chromium / silver or chromium / platinum;

[0026] The flexible supporting layer is made of flexible film material.

[0027] Optionally, the first solder joint array includes 128×128 solder joints;

[0028] The second solder joint array includes 128×128 solder joints;

[0029] And the spacing between adjacent solder joints is 100 microns.

[0030] Optionally, the contact electrode structure includes K sub-contact electrode structures, where K is an integer greater than or equal to 1;

[0031] There is a preset interval between adjacent sub-contact electrode structures in the K sub-contact electrode structures.

[0032] Optionally, the K sub-contact electrode structures are located in the same plane.

[0033] In another aspect, the present application also discloses a method for preparing a brain electrode device, which comprises:

[0034] The brain electrode structure is prepared; the brain electrode structure is used to collect brain electrical signals;

[0035] Connecting the pad structure of the brain electrode structure to the pad area of ​​the signal acquisition chip by flip-chip bonding;

[0036] The signal acquisition chip is mounted on a circuit board, and the signal acquisition chip can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board.

[0037] By adopting the above technical solution, the brain electrode device provided by the present application has the following beneficial effects:

[0038] The brain electrode device includes a signal acquisition chip, a brain electrode structure and a circuit board. The signal acquisition chip is arranged on the circuit board. The signal acquisition chip can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board. The pad area of ​​the signal acquisition chip is connected to the pad structure of the brain electrode structure by flip-chip welding. The brain electrode structure is used to collect brain electrical signals. The above-mentioned method of directly connecting the brain electrode structure with the signal acquisition chip not only improves the integration of the device, but also can improve the signal transmission quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 This is a schematic diagram of the structure of the first optional brain electrode device of this application;

[0041] Figure 2 This is a schematic diagram of the structure of the second optional brain electrode structure of this application;

[0042] Figure 3 A top view of an optional contact electrode structure of the present application;

[0043] Figure 4 This is a schematic diagram of the structure of a second optional brain electrode device of the present application;

[0044] Figure 5 This is a schematic diagram of the structure of an optional signal acquisition chip for this application;

[0045] Figure 6 This is a schematic diagram of the structure of an optional pixel circuit of the present application;

[0046] Figure 7 This is a schematic diagram of the structure of another optional pixel circuit of the present application;

[0047] Figure 8 This is a schematic diagram of the structure of an optional parallel pixel circuit of the present application;

[0048] Fig. 9 This is a schematic diagram of the arrangement of the first optional contact electrodes of the present application;

[0049] Fig.10This is the potential distribution model diagram of the contact electrode structure at time t1;

[0050] Fig.11 This is the potential distribution model diagram of the contact electrode structure at time t2;

[0051] Fig.12 An optional equivalent circuit diagram of the present application when the contact electrode structure is inserted into the brain tissue in the working state;

[0052] Fig.13 This is a schematic diagram of the arrangement of the second optional contact electrodes of the present application;

[0053] Fig.14 This is a schematic diagram of the arrangement of the third optional contact electrodes of the present application;

[0054] Fig.15 A flowchart of an optional control method of a brain electrode module for the present application;

[0055] Fig.16 This is a schematic diagram of the structure of a third optional brain electrode device of the present application;

[0056] Fig.17 This is a schematic diagram of the structure of a fourth optional brain electrode device of the present application;

[0057] Fig.18 This is a schematic structural diagram of the fifth optional brain electrode device of the present application.

[0058] The following is a supplementary description of the attached drawings:

[0059] 1-signal acquisition chip; 11-solder pad area; 111-solder column; 112-solder ball; 2-brain electrode structure; 21-solder pad structure; 22-contact electrode structure; 221-contact electrode; 222-sub-contact electrode structure; 223-first contact electrode; 224-second contact electrode; 3-circuit board; 4-stimulation module; 5-test module; 6-digital-to-analog conversion module; 7-power module; 8-field programmable gate array chip; 9-first PCB board; 10-packaging glue. DETAILED DESCRIPTION

[0060] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] The term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present application. In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the accompanying drawings, which is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first" and "second" are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may include one or more of the features explicitly or implicitly. Moreover, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described here can be implemented in an order other than those illustrated or described here.

[0062] Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values ​​set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements.

[0063] When a numerical range is disclosed herein, the above range is deemed to be continuous and includes the minimum and maximum values ​​of the range, as well as each value between such minimum and maximum values. Further, when a range refers to an integer, each integer between the minimum and maximum values ​​of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges can be merged. In other words, unless otherwise indicated, all ranges disclosed herein should be understood to include any and all sub-ranges included therein. For example, a specified range from "1 to 10" should be deemed to include any and all sub-ranges between a minimum of 1 and a maximum of 10. Exemplary sub-ranges of ranges 1 to 10 include, but are not limited to, 1 to 6.1, 3.5 to 7.8, 5.5 to 10, etc.

[0064] See also Figure 1-2 , Figure 1 This is a schematic diagram of the structure of the first optional brain electrode structure of this application. Figure 2This is a schematic diagram of the structure of the second optional brain electrode structure of the present application. The brain electrode device includes a signal acquisition chip 1, a brain electrode structure 2 and a circuit board 3. The signal acquisition chip 1 is arranged on the circuit board 3. The signal acquisition chip 1 can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board 3. The pad area 11 of the signal acquisition chip 1 is connected to the pad structure 21 of the brain electrode structure 2 by flip-chip welding. The brain electrode structure 2 is used to collect brain electrical signals.

[0065] The brain electrode 1 also includes a contact electrode structure 22 connected to a pad structure 22, the contact electrode structure 22 is used to contact the scalp layer, the pad structure 22 includes N welding points; N is an integer greater than or equal to 2, the contact electrode structure 22 includes N contact electrodes; the N welding points are connected to the N contact electrodes in a one-to-one correspondence, the N contact electrodes include M first contact electrodes 223 and M second contact electrodes 224 (see below) Fig. 9 ), M is an integer greater than or equal to 1; the M first contact electrodes 223 correspond one-to-one to the M second contact electrodes 224, and the distance between the corresponding first contact electrode 223 and the second contact electrode 224 is less than or equal to a first preset distance, the signal acquisition chip 1 includes a connected processor and N pixel circuits; the N pixel circuits are connected one-to-one to the N solder joints, and the processor is used to control the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is turned on, the processor controls any one of the pixel circuits to output a stimulation signal or a test signal to achieve stimulation of the target brain by any one of the contact electrodes or control of the corresponding pixel circuit.

[0066] Optionally, the contact electrode structure 22 is any one of non-invasive, semi-invasive and invasive.

[0067] In a possible implementation, the signal acquisition chip 1 is located in a first area of ​​the circuit board 3 , the first area is close to an end of the circuit board 3 , and the contact electrode structure 22 can extend out of the end of the circuit board 3 to contact the scalp layer.

[0068] It should be noted that when the brain electrode structure 2 is connected to the signal acquisition chip 1, the contact electrode structure 22 of the brain electrode structure 2 needs to extend from the side of the signal acquisition chip 1 with fewer components. For example, the signal acquisition chip 1 is located at the sidemost edge of the circuit board 3 to ensure the length of the contact electrode structure 22 inserted into the brain tissue.

[0069] In one possible implementation, see Figure 3 , Figure 3This is a top view of an optional contact electrode structure of the present application. The contact electrode structure 22 includes a flexible support layer, an electrode line structure and an insulating layer. The electrode line structure is provided on the flexible support layer. The electrode line structure includes an electrode line and a contact electrode 221. One end of the electrode line is connected to the contact electrode 221, and the other end of the electrode line is connected to the solder joint of the pad structure 21. The insulating layer is provided on the electrode line structure, and the insulating layer includes an electrode hole, which is used to expose the contact electrode 221.

[0070] In a possible implementation manner, the material of the contact electrode 221 includes chromium / gold, chromium / silver or chromium / platinum, and the flexible support layer is a flexible film material; optionally, the flexible film material includes polyimide.

[0071] In one possible implementation, see Figure 4 , Figure 4 This is a schematic diagram of the structure of the second optional brain electrode device of the present application. The contact electrode structure 22 includes K sub-contact electrode structures 222, where K is an integer greater than or equal to 1, and there is a preset interval between adjacent sub-contact electrode structures 222 in the K sub-contact electrode structures 222.

[0072] In a possible implementation manner, the K sub-contact electrode structures 222 are located on the same plane.

[0073] See also Figure 2 and Figure 5 , Figure 5 The schematic diagram of the structure of an optional signal acquisition chip of the present application is shown in FIG. 1. In the embodiment of the present application, a first solder point array is provided on the solder pad area 11, and a second solder point array corresponding to the first solder point array is provided on the solder pad structure 21.

[0074] In a possible implementation, the first solder point array includes 128×128 solder points, and the spacing between adjacent solder points is 100 microns. That is, the signal acquisition chip 1 includes 128×128 channels, and the size of each solder point can be 80×80 microns. The second solder point array includes 128×128 solder points, so that it can completely correspond to the signal acquisition chip 1. Subsequently, the first solder point array and the second solder point array are vertically bonded by flip-chip bonding, thereby achieving high integration of the device, effectively overcoming the problem that the two can only be connected by cables in the prior art, and there are low channels and poor signal transmission quality.

[0075] Optionally, the signal acquisition chip 1 can be MOKOTO, which includes 128×128 pixel circuits. The signal acquisition chip 1 includes four signal control lines, each signal control line controls a sub-control line on the north and south sides, and each sub-control line is connected in parallel with 128 pixel circuits. Therefore, only 4 signal inputs can achieve a maximum of 4×2×128=1024 stimulation channels, that is, the above N is 1024.

[0076] It should be noted that in order to isolate and protect adjacent sub-control lines, a separation circuit is provided between adjacent sub-control lines. The above-mentioned N pixel circuits are not necessarily all the solder joints of the control chip, but only correspond to the N contact electrodes. In fact, the control chip may include M pixel circuits, where M is an integer greater than N.

[0077] It should be noted that the number of channels of the control chip may be L times 64 channels, where L may be an integer greater than or equal to 2, for example, 64 channels, 128 channels, 256 channels, etc. That is, N may be 64, 128, 256, etc.

[0078] The following description will be made using the signal acquisition chip 1 as MOKOTO.

[0079] In a possible embodiment, see Figure 6 , Figure 6 This is a schematic diagram of the structure of an optional pixel circuit of the present application. Each pixel circuit includes a first capacitor C1, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, the first end of the first capacitor C1 is connected to the signal input line V0, the second end of the first capacitor C1 is connected to the first end of the second switch S2, the first end of the first switch S1 is connected to the second end of the first capacitor C1, the second end of the first switch S1 is connected to the signal input line V0, the signal input line V0 is connected to the processor, the second end of the second switch S2 is connected to the first end of the third switch S3, and the third end of the second switch S2 is connected to the horizontal control signal line S X[n] Connect the lateral control signal line S X[n] The second end of the third switch S3 is connected to the first end of the fourth switch S4, and the third end of the third switch S3 is connected to the longitudinal control signal line S Y[m] Connect the vertical control signal line S Y[m]The processor inputs a stimulation signal or a test signal to the pixel circuit through the signal input line V0; the processor controls the pixel circuit through the horizontal control signal line S X[n] Control the opening or closing of the second switch S2; the processor controls the vertical signal line S Y[m] Control the opening or closing of the third switch S3.

[0080] Optionally, the two selection signal lines, namely the horizontal control signal line S X[n] and the longitudinal control signal line S Y[m] The register in the processor controls the pixel circuit that needs to be operated, so that the pixel circuit that needs to be operated can be selected from the 128×128 pixel circuits, that is, the horizontal control signal line S X[n] and the longitudinal control signal line S Y[m] You can select the number of stimulation channels you want to achieve and select adjustable stimulation channels. Figure 6 S X[n] Indicates the nth row of horizontal control signal lines; S Y[m] Indicates the m-th column vertical control signal line.

[0081] Optionally, the opening or closing of the first switch S1 and the fourth switch S4 can be controlled based on the user's operation. Since the opening and closing of the first switch S1 and the fourth switch S4 will form different control signals, when the first switch S1 and the fourth switch S4 are closed, "0" will be output, so that the processor controls the voltage signal input to the signal input line V0 from the outside to flow to the output port as a stimulation signal, and then reaches the contact electrode; on the contrary, if the first switch S1 and the fourth switch S4 are closed, "1" will be output, so that the processor controls the voltage signal input to the signal input line V0 from the outside to flow to the amplification circuit as a test signal, and finally outputs the signal through other I / O ports of the chip to an externally connected signal analysis device for observation.

[0082] It should be noted that the test signal mentioned above and below means that when the control chip receives the test signal, it will test the target pixel circuit to determine whether the pixel circuit can operate normally, which can be determined according to different test result signals output by the control chip; in most cases, the control chip mainly collects EEG signals from the target brain. The collected EEG signals can be output by controlling the closing of the fourth switch S4.

[0083] Of course, it is also possible to directly control the first switch S1 and the fourth switch S4 based on an external trigger signal, so that the processor controls the opening or closing of the first switch S1 and the fourth switch S4 based on the trigger signal, thereby realizing the control of the two switches.

[0084] Similarly, other switches in the pixel circuit, such as the second switch S2, the third switch S3 and the fifth switch S5 described below, can be controlled by the above two methods, which are not limited here.

[0085] In a possible embodiment, see Figure 7 , Figure 7 This is a schematic diagram of the structure of another optional pixel circuit of the present application. To achieve more stimulation types and meet the analysis of neural signals under diversified stimulation. Each pixel circuit also includes a second capacitor C2 and a fifth switch S5; the first end of the second capacitor C2 is connected to the first end of the fourth switch S4, and the second end of the second capacitor C2 is connected to the corresponding solder joint; the first end of the fifth switch S5 is connected to the first end of the second capacitor C2, and the second end of the fifth switch S5 is connected to the second end of the second capacitor C2; the processor controls the pixel circuit to output DC or AC by controlling the opening or closing of the fifth switch S5. In other words, the second capacitor C2 can be controlled to be short-circuited by controlling the opening or closing of the fifth switch S5. It can be set that when the fifth switch S5 is disconnected, the output "0" is output, and the signal input line V0 will input AC, otherwise, when the fifth switch S5 is closed, the second capacitor C2 is short-circuited, and the output "1" is output, then the signal input line V0 will input DC.

[0086] Optional, see Figure 8 , Figure 8 This is a schematic diagram of the structure of an optional parallel pixel circuit of the present application. Figure 8 The two parallel pixel circuits shown belong to the same row, so they can be controlled by the same horizontal control signal line S X[n] The vertical control signal line of the first pixel circuit is S Y[m] , the vertical control signal line of the second pixel circuit is S Y[n+1] When multiple pixel units are connected in parallel, the same applies, including multiple vertical control signal lines S Y[m] Controlled pixel unit.

[0087] In a feasible embodiment, the contact electrode structure 22 also includes a flexible substrate and an insulating layer, N contact electrodes are arranged on the flexible substrate, the insulating layer is arranged on the N contact electrodes, and the insulating layer includes N electrode holes, and the N electrode holes correspond one-to-one to the N contact electrodes.

[0088] It should be noted that when different pixel circuits correspond to contact electrodes with different arrangements, since the contact electrodes may be located in different areas of the brain tissue and at different distances from the brain tissue, adjusting the correspondence between the contact electrodes and the pixel circuits will affect the area of ​​the stimulated tissue, the number of stimulation channels, the form of stimulation, and the intensity of stimulation, etc.; for example, when the contact electrode is far away from the corresponding site of the brain tissue, in order to achieve the required stimulation energy, it is necessary to increase the intensity of the stimulation voltage / current, and conversely, it is necessary to reduce the intensity of the stimulation voltage / current.

[0089] In order to achieve charge balance, reduce the complexity of external integrated circuits, and reduce the circuit area. Fig. 9 , Fig. 9 This is a schematic diagram of the arrangement of the first optional contact electrode of the present application. The top of the flexible substrate includes a first side and a second side relative to each other, the M first contact electrodes 223 are located on the first side, the M second contact electrodes 224 are located on the second side, and there is a second preset distance between adjacent first contact electrodes 223; the second preset distance is greater than or equal to the first preset distance, and there is the second preset distance between adjacent second contact electrodes 224. The first contact electrode 223 will subsequently input a first stimulation signal, and the second contact electrode 224 will input a second stimulation signal, and the first stimulation signal is a signal with the same amplitude, phase and shape as the second stimulation signal, so as to achieve charge balance in the corresponding brain tissue area.

[0090] It should be noted that the above-mentioned first stimulation signal and second stimulation signal are not instantaneous signals, but signals with equal amplitude, phase and shape formed in a relatively short period of time; the signals formed at time t1 and time t2 below are also signals with equal amplitude, phase and shape.

[0091] The following will be based on Fig. 9 The principle of achieving charge balance by the contact electrode structure 22 is described below:

[0092] Fig. 9 The contact electrode structure 22 includes 24 pairs of contact electrodes, each of which includes a first contact electrode 223 located on the first side and a second contact electrode 224 located on the second side; it should be understood that when the contact electrode receives a stimulation signal, the brain tissue it contacts will be injected with electric charge, so the surrounding electric potential will also change. Assuming that at time t0, there is no voltage signal input to the first signal input line V1 connected to the first contact electrode 223 and the second signal input line V2 connected to the second contact electrode 224, then the electric potential of the tissue connected to the contact electrode is equal everywhere and is in a relatively balanced state. Fig.10 , Fig.10is a potential distribution model diagram of the contact electrode structure at time t1. When at time t1, the first signal input line V1 inputs a signal with an amplitude of "1", and the second signal input line V2 inputs a signal with an amplitude of "0", the first contact electrode 223 on the first side forms a high potential due to the injection of charge, and the second contact electrode 224 on the second side forms a relatively low potential, and a potential difference is formed between the adjacent first contact electrode 223 and the second contact electrode 224, so there is I sti From the first contact electrode 223 to the second contact electrode 224, Fig.10 See Fig.11 , Fig.11 t2 is a potential distribution model diagram of the contact electrode structure. At time t2, the first signal input line V1 inputs a signal with an amplitude of "0", and the second signal input line V2 inputs a signal with an amplitude of "1". The first contact electrode 223 on the first side is at a low potential, and the second contact electrode 224 on the second side is at a high potential. sti From the second contact electrode 224 to the first contact electrode 223. Since the actual distance between the first contact electrode 223 and the second contact electrode 224 is very close, the current formed by the potential difference can be considered to flow only between the two electrodes and hardly diffuse outward. The equivalent schematic diagram of the loop formed by the first contact electrode 223-tissue-tissue-second contact electrode 224 is as follows: Fig.12 As shown, Fig.12 This is an optional equivalent circuit diagram of the present application when the contact electrode structure is inserted into the brain tissue. In a very short time, it can be considered that I with equal magnitude and opposite direction is generated at time t1 and time t2. sti Therefore, after time t2, the charges injected into the brain tissue due to stimulation are offset by each other, achieving charge balance. The present application not only solves the charge balance problem by alternately inputting stimulation through two signal lines, avoiding brain tissue damage and electrode electrolysis, but also improves integration and simplifies the external circuit.

[0093] It should be noted that Fig.12 Re is the contact electrode resistance, R and Ci are the equivalent resistance and capacitance in the brain tissue, and Rs is the resistance between the two contact electrode paths.

[0094] In a possible embodiment, see Fig.13 , Fig.13This is a schematic diagram of the arrangement of the second optional contact electrodes of the present application. The N contact electrodes form a contact electrode set, which includes a first contact electrode set and a second contact electrode set, the first contact electrode set is located on the first side, the second contact electrode set is located on the second side, the first contact electrodes 223 and the second contact electrodes 224 in the first contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of the first contact electrodes 223 and the number of the second contact electrodes 224 in the first contact electrode set is equal to M, the first contact electrodes 223 and the second contact electrodes 224 in the second contact electrode set are staggered along the length direction of the flexible substrate, the sum of the number of the first contact electrodes 223 and the number of the second contact electrodes 224 in the second contact electrode 224 is equal to M, wherein the arrangement of the contact electrodes in the first contact electrode set is the same as the arrangement of the contact electrodes in the second contact electrode 224.

[0095] In another possible embodiment, see Fig.14 , Fig.14 This is a schematic diagram of a third optional arrangement of contact electrodes in the present application. The arrangement of the contact electrodes in the first contact electrode set is opposite to the arrangement of the contact electrodes in the second contact electrode 224 .

[0096] It should be noted that the above-mentioned brain electrode module can select the voltage control mode when stimulating brain tissue, and can achieve charge-balanced electrical stimulation by generating a balanced bidirectional voltage pulse in the external circuit and inputting it into the signal input line V0. This method can achieve a total of 1024-channel stimulation with 4 different stimulation waveforms.

[0097] In a feasible embodiment, the signal input line V0 includes three sub-signal input lines V0, and the phase difference between adjacent sub-signal input lines V0 arranged along a preset direction is 120 degrees. That is to say, when the electrode position controlled by the three signal lines just forms an angle of 120°, and the three external signal input ports give an initial stimulation with a phase difference of 120°, it is possible to form autonomous power generation, that is, there is no need to supply the stimulation signal from an external voltage generator, but to use the phase difference to make the signal continue. Similarly, using four signal lines to form a phase difference of 90° can also form a four-phase generator, which is an excellent development point in future wireless, sustainable, and energy-saving designs.

[0098] Optionally, when the signal acquisition chip 1 is the above-mentioned MOKOTO chip, and the brain electrode 1 is a device with 2640 channels, the pad structure 22 of the brain electrode 1 is a 30×88 solder point array; the distance between adjacent solder points is 200 microns, and the distance between adjacent pixel circuit units in the MOKOTO chip is 100 microns, then the two can be flip-chip soldered, thereby improving the integration and ensuring the signal quality; since the distance between adjacent solder points of the brain electrode 1 is twice the distance between adjacent pixel units, the adjacent solder points can be connected to the spaced pixel units, so that the number of solder points that can be connected to the pixel units of MOKOTO is 30×64, and since the MOKOTO chip has only 8 rows of arrays with corresponding signal lines, only 30×8=240 channels can be used for the stimulation part. However, by adjusting the distance between the solder points, the corresponding number of channels can also be changed, and the above is only an example of an optional embodiment.

[0099] In summary, in the brain electrode module provided by this application, since the signal acquisition chip 1 includes multiple pixel circuits, corresponding to multiple contact electrodes of the brain electrode 1, it is possible to control the opening of different stimulation channels, realize the stimulation of adjustable sites, and configurable bipolar voltage stimulation to achieve charge balance, reduce the complexity of external integrated circuits, and reduce the circuit area; and the optional DC / AC stimulation can adapt to specific experimental scenarios. This application not only realizes high-channel stimulation, further fills the gap in high-channel stimulation on the market, but also can adapt to changes in different needs in the biomedical field, has higher flexibility, reduces R&D costs, and shortens the experimental cycle.

[0100] See also Fig.15 , Fig.15 This is a flow chart of an optional control method of a brain electrode module of the present application. In another aspect, the present application also discloses a control method of a brain electrode module, which is applied to the above-mentioned brain electrode module, and the control method comprises the following steps:

[0101] S1501: Acquire a site control signal.

[0102] S1502: Controlling the pixel circuit at the corresponding site to be turned on based on the site control signal.

[0103] As described above, the horizontal control signal line S can be controlled by controlling the number of rows. X[n] The number of vertical control signal lines S Y[m] , thereby controlling the opening and closing of the corresponding second switch S2 and the third switch S3 to achieve the conduction of the corresponding pixel circuit as a whole.

[0104] S1503: Receive a function control signal.

[0105] Optionally, the functional control signal may include two types, one is a control signal for controlling the pixel circuit to output a stimulation / test signal; the other is a control signal for controlling the pixel circuit to output a direct current / alternating current.

[0106] S1504: Based on the functional control signal, the pixel circuit is controlled to output a stimulation signal or a test signal to achieve stimulation of the target brain by the contact electrode or control of the corresponding pixel circuit.

[0107] Referring to the above description, the input stimulation signal or test signal can be realized by the signals generated by the opening and closing of the first switch S1 and the fourth switch S4. When it is a stimulation signal, it is input into the brain tissue through the output port, and when it is a test signal, it is input into the amplifier circuit.

[0108] It is also possible to determine whether the stimulation signal input into the pixel circuit is AC or DC by controlling the fifth switch S5 to be turned on or off. The specific implementation method is described above and will not be repeated here.

[0109] The present application also provides a brain electrode device, see Fig.16 , Fig.16 This is a schematic diagram of the structure of the third optional brain electrode device of the present application. The brain electrode device also includes a stimulation module 4 and a test module 5 arranged on the same circuit board 3 mentioned above, and the stimulation module 4 and the test module 5 are respectively connected to the signal acquisition chip 1, and the stimulation module 4 is used to generate a stimulation signal, and the stimulation signal is used to stimulate the cerebral cortex through the brain-brain electrode structure 2; the signal acquisition chip 1 is used to control the on-off of the channel of the brain-brain electrode structure 2, and the switching input of the test signal and the stimulation signal; the test module 5 is used to receive the test result signal sent by the signal acquisition chip 1, and perform digital-to-analog conversion processing on the test result signal; the test result signal is a signal generated by the signal acquisition chip 1 based on the test signal.

[0110] Therefore, the brain-computer interface front-end device provided by the present application can not only realize the acquisition and stimulation of the cerebral cortex, but also can realize the test of the pixel circuit in the signal acquisition chip 1 based on the cooperation of the signal acquisition chip 1 and the test module 5. For example, it can be a test of the short circuit and open circuit of the above pixel circuit.

[0111] In order to better transmit information without distortion and compress data, it is necessary to perform analog-to-digital conversion on the analog signal directly collected by the electrode. Fig.17 , Fig.17This is a schematic diagram of the structure of the fourth optional brain electrode device of the present application. The brain electrode device also includes a digital-to-analog conversion module 6 and a power module 7; the digital-to-analog conversion module 6 is connected to the signal acquisition chip 1; the power module 7 is connected to the signal acquisition chip 1 and the digital-to-analog conversion module 6; the power module 7 is used to supply power to the signal acquisition chip 1 and the digital-to-analog conversion module 6; the power module 7 includes a lithium battery, a first low-voltage difference linear regulator and a second low-voltage difference linear regulator; the lithium battery is connected to the signal acquisition chip 1 through the first low-voltage difference linear regulator; the lithium battery is connected to the digital-to-analog conversion module 6 through the second low-voltage difference linear regulator; the digital-to-analog conversion module 6 is used to receive the EEG signal sent by the signal acquisition chip 1 and perform digital-to-analog conversion on the EEG signal. The use of lithium batteries can ensure the accuracy of electrical signals and has low noise, and can power some sensitive power supplies, such as some devices (corresponding pins) in the above-mentioned signal acquisition chip 1 and some devices (corresponding pins) in the digital-to-analog conversion module 6. In addition, since the actual EEG signal is very weak, often only tens of μV to a few mV, it is seriously affected by noise, so the noise requirement is very high. The present application adopts a low-voltage differential signal to transmit the signal, and adopts a low-voltage and low-current driving method to achieve low power consumption, low bit error rate, low crosstalk, low radiation, and low noise.

[0112] Generally, for low-density electrodes, the area and power restrictions can be relaxed, signal amplification and analog-to-digital conversion can be performed on-chip, and the generated digital data flows to the acquisition board through a serial peripheral interface. However, when high-density EEG devices are used, in order to prevent brain tissue damage during the recording process, the area and power of the implant in the brain are greatly limited. Therefore, for high-throughput electrodes, a series of processes such as amplification of neural signals cannot be integrated on the electrode single board like existing low-throughput active devices. An additional PCB board is required to integrate a neural signal amplification chip on the board, and then cooperate with ADC circuits to perform off-chip conversion. However, the chip integrated on the current external circuit board can only achieve a flux of 32 sites, which is relatively low. Optionally, the control chip in this application can be the above-mentioned MOKOTO, because it can achieve a maximum of 4×2×128=1024 stimulation channels. And in order to improve the data conversion efficiency, the above-mentioned digital-to-analog conversion module 6 can include two submodules, and a submodule can be provided near the north and south sides of the signal acquisition chip 1.

[0113] Optionally, when the signal acquisition chip 1 is MOKOTO, the acquisition rate of each channel of the signal acquisition chip 1 is greater than or equal to 40 frames / second. Through multiplexing within the chip, there are 16 outputs on each of the north and south sides. Therefore, the sampling rate of each output channel is required to be no less than 128×64×40 / 16=20.48Msample / s. Furthermore, in order to make the quantization noise much lower than the thermal noise floor, a digital-to-analog conversion module 6 resolution of at least 12 bits is required. Therefore, the data transmission rate of the entire chip must be no less than 12bit×20.48M×16×2=7.86G bits / second.

[0114] In an optional embodiment, see Fig.17 The brain electrode device also includes a field programmable gate array (FPGA) chip; the field programmable gate array chip 8 is connected to the signal acquisition chip 1, the digital-to-analog conversion module 6, the test module 5 and the stimulation module 4; the field programmable gate array chip 8 is used to supply power to the test module 5 and the stimulation module 4, and send the received EEG signal sent by the digital-to-analog converter to the signal acquisition device.

[0115] Optionally, the voltage of the field programmable gate array chip 8 includes 5 volts. The field programmable gate array chip 8 can provide power for devices that do not require high accuracy of power supply signals, and can output different voltages by connecting it to different low voltage difference linear regulators.

[0116] Optionally, the field programmable gate array chip 8 can power the following modules of the digital-to-analog conversion module 6, the stimulation module 4 and the signal acquisition chip 1, wherein the pins of the digital-to-analog conversion module 6 include DVDD_TI_ADC (1.2V), TI_ADC (1.8V), MISC (3.3V), the pins of the stimulation module 4 include VREF (3.5V), and the pins of the signal acquisition chip 1 include VDDIO (3.3V) and VDDD (3.3V); it should be noted that VDDIO and VDDD are pins for powering the signal acquisition chip 1, and VREF is used to power the chip in the stimulation module 4 that needs to generate a 3.3V reference voltage. Since the output level range of the signal acquisition chip 1 is about 0-3.3V, and the input signal of the digital-to-analog conversion module 6 is required to be about 0-1.8V, level conversion is required. Therefore, the MISC is used to power the level conversion module located in the digital-to-analog conversion module 6.

[0117] In an optional embodiment, the voltage of the lithium battery includes 3.7 volts; the voltage range output by the first low-voltage difference linear regulator includes 0.5 to 3.3 volts; and the voltage output by the second low-voltage difference linear regulator includes 1 to 1.8 volts.

[0118] Optionally, the test result signal output by the signal acquisition chip 1 may be input via MBS_N MBS_S of the test module 5 .

[0119] In order to realize high-precision stimulation signals, in an optional embodiment, the stimulation module 4 can be a chip with a resolution of 12 bits and a DNL of only 0.5LSB. The stimulation voltage output by the stimulation module 4 is in the range of 0-3.3 volts, and the error range between the stimulation voltage value output by the stimulation module 4 and the preset voltage value is 0-0.4 millivolts. With extremely high precision, in addition to generating high-precision voltage stimulation, a grounding switch is also required, which is turned on and grounded after each stimulation cycle to promptly release the unbalanced charge accumulated due to impedance changes, power supply mismatch, etc., so that long-term cyclic stimulation can be performed, so that the electrode voltage is kept within the safety threshold, and irreversible damage to the tissue due to charge accumulation is avoided.

[0120] It can be seen from the above examples that the design of the brain-computer interface front-end device provided in this application can provide a good solution for the acquisition and processing of high-throughput EEG signals, integrating the signal amplification, filtering, analog-to-digital conversion, and stimulation on an external PCB to realize the processing and conversion of high-throughput EEG signals; and integrating the signal amplification, filtering chip, analog-to-digital conversion, and stimulation module 4 in the same neural recording front end, separated from the probe, to relieve the pressure of implant noise, power, and area, and to minimize the damage to the living detection object; at the same time, up to 1024 channels can be stimulated simultaneously, with a resolution of up to 12Bit, and the switch controls the ground short circuit to release the accumulated charge in the stimulation gap to achieve stimulation charge balance. By combining the above device with the brain-brain electrode structure 2, the changes in neuronal electrical activity and neuromolecules in physiological and pathological processes can be accurately recorded, based on which how the brain circuit works and the possible functional disorders in the disease can be deciphered, and the stimulation function is assisted, and the stimulation parameters are adjusted according to the feedback of the detected results, so as to cooperate with the early disputes and neuroregulatory treatment of brain diseases such as Parkinson's and epilepsy.

[0121] Considering the crosstalk between 10,000-channel signals and the high requirements for noise quality, the contact electrodes of the brain-to-brain electrode structure 2 provided by the present application will not integrate active circuits, but will only be responsible for the collection and transmission of EEG signals. A signal acquisition chip 1 is required to amplify and filter the collected 10,000-channel signals. The processed signals are multiplexed at the north and south ends of the EEG signal processing chip and output through 16 I / O ports respectively. The circuit on the PCB board is then converted through a series of SPI and transmitted to the field programmable gate array chip 8 for data integration control. Finally, the field programmable gate array chip 8 transmits the signal to the client through a 10,000-Gigabit cable for visualization processing. Based on the above-mentioned brain electrode device, the functions of collection, stimulation, and testing can be realized, and high-throughput signal transmission can be achieved.

[0122] In summary, the brain electrode device provided by the present application has the shortest signal path, the highest assembly density, good electrical performance and good heat dissipation, and the noise interference of the real signal is greatly reduced in the process of weak EEG signals from being collected to being converted into amplified digital signals, which improves the accuracy of the signal, and its output signal can be directly transmitted to FPGA for data processing such as spike classification. It has a very high degree of integration, greatly reduces the area of ​​the high-channel brain-computer interface system, and provides a reliable method for the application of future product miniaturization. The use of flip-chip welding technology is low-cost, fast and flexible for product development, prototyping and small-batch production, and is easy to use automated equipment to expand to wafer-based mass production. Since the interconnection between the brain electrode structure 2 and the signal acquisition chip 1 is realized by flip-chip welding, the use of cables is eliminated, making the entire system more solid in hardware, increasing the stability of the system, and reducing the "micro-movement" between the electrode and the tissue, reducing tissue wear, and extending the service life of the device.

[0123] In another aspect, the present application also discloses a method for preparing a brain electrode device, which comprises:

[0124] 1) Prepare the brain electrode structure 2; the brain electrode structure 2 is used to collect brain electrical signals.

[0125] 2) The pad structure 21 of the brain electrode structure 2 is connected to the pad area 11 of the signal acquisition chip 1 by flip-chip bonding.

[0126] In step 2), the flip-chip bonding process may be a thermocompression flip-chip bonding process. An optional thermocompression flip-chip bonding process includes the following steps:

[0127] 2.1 First, solder joints are grown on the signal acquisition chip 1 to form a pad area 11. The height of each solder joint in the pad area 11 can be adjusted accordingly according to the solder joint gap. Optionally, the height of the solder joint is in the range of 60-10 microns to adapt to the spacing between the solder joints of the pad structure 21. The spacing between the solder joints of the pad structure 21 can actually be adjusted according to demand. Continuing with the above embodiment, the spacing between the solder joints of the pad structure 21 is 200 microns. Fig.18 , Fig.18 This is a schematic diagram of the structure of the fifth optional brain electrode device of the present application. When the spacing between the solder joints of the above-mentioned solder pad structure 21 is reduced, the height of the solder joints in the solder pad area 11 can also be appropriately reduced.

[0128] Optionally, the solder joint of the pad area 11 includes a solder column 111 and a solder ball located on the solder column 112 , and the material of the solder column includes copper; the material of the solder ball includes tin-silver.

[0129] 2.2 When step 2.1 is prepared on a large uncut plate containing multiple signal acquisition chips, it is also necessary to thin and slice the large plate to obtain a single signal acquisition chip.

[0130] 2.3 The signal acquisition chip is bonded to a corresponding first PCB substrate 9, and a wire bonding groove can be provided at a location where wire bonding is required on the subsequent signal acquisition chip 1, such as Fig.18 As shown, the subsequent wiring operation is convenient and the fault tolerance is improved.

[0131] 2.4 Mount the required components such as capacitors and resistors on the first PCB board.

[0132] 2.5 The signal acquisition chip is connected to the corresponding components on the first PCB substrate 9 by wire bonding. Optionally, the material of the wire includes gold. The diameter of the gold wire ranges from 0.5 to 0.7 mil, which can be 0.5 mil, 0.6 mil or 0.7 mil.

[0133] 2.6 The wire bonding area is packaged using packaging glue 10.

[0134] 2.8 Based on the above step 2.6, a signal acquisition chip device to be welded can be obtained. The brain electrode structure is placed in the preset area, and the pad structure 21 of the brain electrode structure is facing upward. A signal acquisition chip device is taken, and the solder points of the pad area 11 of the signal acquisition chip device are aligned with the solder points of the above pad structure 21. Reflow soldering is performed by heating without applying pressure, and the welding temperature can be 217 degrees Celsius.

[0135] 3) The signal acquisition chip 1 is mounted on the circuit board 3. The signal acquisition chip 1 can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board 3. The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A brain electrode device, characterized in that: It comprises a signal acquisition chip (1), a brain electrode structure (2) and a circuit board (3); The signal acquisition chip (1) is arranged on the circuit board (3), and the signal acquisition chip (1) can realize analog-to-digital conversion, amplification and filtering of the signal by cooperating with the peripheral circuit of the circuit board (3); The pad area (11) of the signal acquisition chip (1) is connected to the pad structure (21) of the brain electrode structure (2) by flip-chip welding; the pad area (11) includes N solder joints, and the brain electrode structure (2) includes N contact electrodes; The brain electrode structure (2) is used to collect brain electrical signals; The signal acquisition chip (1) comprises a processor and N pixel circuits connected to each other; the N pixel circuits are connected to the N welding points in a one-to-one correspondence, and the processor is used to control the on or off of any one of the N contact electrodes by controlling the on or off of any one of the N pixel circuits; and when any one of the pixel circuits is on, the processor controls any one of the pixel circuits to output a stimulation signal or a test signal to stimulate the target brain by any one of the contact electrodes or to control the corresponding pixel circuit; Each of the pixel circuits includes a first capacitor C1, a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4, wherein a first end of the first capacitor C1 is connected to a signal input line V0, a ​​second end of the first capacitor C1 is connected to a first end of the second switch S2, a first end of the first switch S1 is connected to a second end of the first capacitor C1, a second end of the first switch S1 is connected to the signal input line V0, the signal input line V0 is connected to the processor, a second end of the second switch S2 is connected to a first end of the third switch S3, and a third end of the second switch S2 is connected to a transverse control signal line S X[n] Connect the lateral control signal line S X[n] The second end of the third switch S3 is connected to the first end of the fourth switch S4, and the third end of the third switch S3 is connected to the longitudinal control signal line S Y[m] Connect the vertical control signal line S Y[m] connected to the processor; a first end of the fourth switch S4 is connected to the output port, the output port is connected to the corresponding welding point, and a second end of the fourth switch S4 is connected to the test signal processing circuit.

2. The brain electrode device according to claim 1, characterized in that: A first welding point array is provided on the welding pad area (11); The pad structure (21) is provided with a second soldering point array corresponding to the first soldering point array.

3. The brain electrode device according to claim 1, characterized in that: The brain electrode structure (2) comprises a contact electrode structure (22) connected to the pad structure (21); The contact electrode structure (22) collects brain electrical signals by contacting the scalp layer; The contact electrode structure (22) is any one of a non-invasive type, a semi-invasive type and an invasive type.

4. The brain electrode device according to claim 3, characterized in that: The signal acquisition chip (1) is located in the first area of ​​the circuit board (3); The first area is close to the end of the circuit board (3); The contact electrode structure (22) can extend out of the end of the circuit board (3) to contact the scalp layer.

5. The brain electrode device according to claim 3, characterized in that: The contact electrode structure (22) comprises a flexible support layer, an electrode line structure and an insulating layer; The electrode wire structure is provided on the flexible supporting layer; The electrode line structure comprises an electrode line and a contact electrode (221); One end of the electrode wire is connected to the contact electrode (221), and the other end of the electrode wire is connected to a welding point of the pad structure (21); The insulating layer is provided on the electrode line structure, and the insulating layer comprises an electrode hole, wherein the electrode hole is used to expose the contact electrode (221).

6. The brain electrode device according to claim 5, characterized in that: The material of the contact electrode (221) includes chromium / gold, chromium / silver or chromium / platinum; The flexible supporting layer is made of a flexible film material.

7. The brain electrode device according to claim 2, characterized in that: The first solder joint array includes 128×128 solder joints; The second solder joint array includes 128×128 solder joints; And the spacing between adjacent solder joints is 100 microns.

8. The brain electrode device according to claim 3, characterized in that: The contact electrode structure (22) comprises K sub-contact electrode structures (222), wherein K is an integer greater than 1; There is a preset interval between adjacent sub-contact electrode structures (222) in the K sub-contact electrode structures (222).

9. The brain electrode device according to claim 8, characterized in that: The K sub-contact electrode structures (222) are located on the same plane.

10. A method for preparing a brain electrode device according to any one of claims 1 to 9, characterized in that: include: The brain electrode structure (2) is prepared; the brain electrode structure (2) is used to collect brain electrical signals; Connecting the pad structure (21) of the brain electrode structure (2) to the pad area (11) of the signal acquisition chip (1) by flip-chip bonding; The signal acquisition chip (1) is mounted on a circuit board (3); the signal acquisition chip (1) can achieve analog-to-digital conversion, amplification and filtering of signals by cooperating with the peripheral circuit of the circuit board (3).

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