An exposed series dual chipset package, packaging method and PCB board

Abstract

The present invention discloses an exposed series dual-chipset package, a packaging method and a PCB board, belonging to the field of semiconductor packaging. The device includes a lead frame and a plastic package, and also includes a first chip set and a second chip set, the second chip set and the first chip set are stacked up and down, wherein the first chip set includes a first chip and a second chip; the second chip set includes a third chip and a fourth chip; the gates of the first chip, the second chip, the third chip and the fourth chip are all bonded to the gate pin of the lead frame; the source of the fourth chip is bonded to the source pin of the lead frame. The present invention can improve the voltage strength under the condition of the same current and the same area of ​​the plastic package; with the help of the dual-chipset heteropolar series bonding plastic package structure, the manufacturing cost of at least one chip plastic package can be reduced; the same chip heteropolar series bonding plastic package structure can be used to reduce the development, production and inventory costs of different chips and packages.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging, and in particular to an exposed series-connected dual-chipset package, a packaging method and a PCB board. Background Art

[0002] The traditional typical MOSFET power chip packaging generally adopts a packaging body that places a single MOSFET power chip in a package body. The key process of MOSFET power chip packaging process is divided into several packaging process methods and steps due to different applications. The more critical process changes are mainly the way of bonding the pins inside the metal lead frame outside the chip from the functional area on the front of the chip. The bonding methods are nothing more than pure metal wire bonding, metal strip plus metal wire mixed bonding, metal sheet with metal solder paste bonding plus metal wire mixed bonding, and full metal sheet with metal solder paste bonding.

[0003] The process flows and methods of the above-mentioned different bonding technologies are also different. However, no matter which bonding method is used, it is basically the traditional mainstream packaging mode to install a single MOSFET power chip in a single package.

[0004] The existing traditional single MOSFET power chip packaging model has the following defects:

[0005] 1. If the traditional single power chip packaging type is used in the case of higher voltage, it is necessary to specially develop a single higher voltage MOSFET power chip and then package the single MOSFET power chip, which requires increased development costs, increased production costs, and extended product development cycles;

[0006] 2. Increasing the development of higher voltage MOSFET power chips will increase the inventory cost of different MOSFET power chips;

[0007] 3. Another way is to use multiple single MOSFET power chip packages, connect multiple low-power MOSFET power chips in series, and solder them on the PCB board to increase the voltage. This will increase the number of single packages, and also increase the number of packages and the production cost of plastic packages;

[0008] 4. When the packages of multiple single MOSFET power chips are soldered in series on the PCB board, the use area of ​​the PCB board is increased, which in turn increases the production cost and inventory cost of the PCB board area.

[0009] 5. The existing MOSFET power chip packaging body is a plastic package that completely covers the power chip. When the power is high, the heat dissipation is not timely, and the power chip is easily damaged due to excessive temperature.

[0010] Therefore, the defects presented by the above-mentioned existing traditional single MOSFET power chip are also the trend that the industry urgently needs to overcome and reduce costs. It is also the difficulty in reducing costs in the field of fast charging that requires MOSFET high voltage acceleration. Summary of the invention

[0011] The present invention provides an exposed series dual-chip package, which can solve the problems of high cost, long development cycle and poor heat dissipation effect existing in the single chip packaging method in the prior art.

[0012] The present invention also provides a packaging method for an exposed series dual-chip set package, which is used to prepare the package.

[0013] The present invention also provides a PCB board, which can reduce the area of ​​the circuit board and reduce the production cost of the PCB board.

[0014] An exposed series dual-chipset package, comprising a lead frame and a plastic package, and also comprising a first chipset, a second chipset, a source conductive plate and a gate conductive plate;

[0015] The first chipset includes a first chip and a second chip, the second chipset includes a third chip and a fourth chip, and the second chipset and the first chipset are stacked up and down; wherein,

[0016] The source conductive plate, the fourth chip, the third chip, the second chip, the first chip and the lead frame are arranged in sequence from top to bottom;

[0017] The drain of the first chip is connected to the drain pin through the base island, the drain of the second chip is aligned with the source of the first chip, the drain of the third chip is aligned with the source of the second chip, and the drain of the fourth chip is aligned with the source of the third chip;

[0018] The source of the fourth chip is connected to the source pin through the source conductive plate;

[0019] The gate of the first chip, the gate of the second chip, the gate of the third chip and the gate of the fourth chip are all connected to the gate pin through the gate conductive plate; wherein,

[0020] The source conductive plate is partially located outside the plastic package.

[0021] More preferably, the first chip and the second chip are arranged in a staggered manner so that the projection of the gate of the first chip in the vertical direction is completely exposed to the projection of the second chip; the third chip and the fourth chip are arranged in a staggered manner so that the projection of the gate of the third chip in the vertical direction is completely exposed to the projection of the fourth chip;

[0022] The first chip group and the second chip group are staggered so that projections of the gate of the first chip and the gate of the second chip along the vertical direction are completely exposed to projections of the third chip and the fourth chip.

[0023] More preferably, the gate conductive plate includes a first gate plate, a second gate plate and a third gate plate;

[0024] The first chip and the second chip are staggered so that the projection of the gate of the first chip along the vertical direction is completely exposed to the projection of the second chip; the third chip and the fourth chip are staggered so that the projection of the gate of the third chip along the vertical direction is completely exposed to the projection of the fourth chip; the second chip and the third chip are staggered so that the projection of the gate of the second chip along the vertical direction is completely exposed to the projection of the third chip;

[0025] The first gate plate connects the gate of the first chip and the gate pin, the second gate plate connects the gate of the second chip and the third gate plate, and the third gate plate connects the gate of the third chip, the gate of the fourth chip, and the first gate plate.

[0026] More preferably, a connecting portion is extended from one side of the source conductive plate, and the connecting portion is connected to the source pin of the lead frame; a receiving groove is provided on the source pin, and the receiving groove matches the connecting portion.

[0027] More preferably, the source conductive plate and the gate conductive plate are made of copper or aluminum.

[0028] More preferably, a metal spacer is disposed between the first chip and the second chip, the source electrode of the first chip and the drain electrode of the second chip are connected via the metal spacer, and the metal spacer forms a bonding space for accommodating a bonding wire between the first chip and the second chip;

[0029] A metal spacer is disposed between the second chip and the third chip, the source electrode of the second chip and the drain electrode of the third chip are connected through the metal spacer, and the metal spacer forms a bonding space for accommodating a bonding wire between the second chip and the third chip;

[0030] A metal spacer is arranged between the third chip and the fourth chip, the source of the third chip and the drain of the fourth chip are connected through the metal spacer, and the metal spacer forms a bonding space for accommodating bonding wires between the third chip and the fourth chip.

[0031] A packaging method for an exposed series dual-chipset package, comprising the following steps:

[0032] S1, coating a conductive adhesive material on the base island, so that the drain electrode of the first chip is connected to the base island through the adhesive material;

[0033] S2, coating an adhesive material on the source electrode of the first chip, connecting the drain electrode of the second chip to the source electrode of the first chip through the adhesive material, and making the projection of the gate electrode of the first chip in the vertical direction completely exposed to the projection of the second chip;

[0034] S3, coating an adhesive material on the source electrode of the second chip, connecting the drain electrode of the third chip to the source electrode of the second chip through the adhesive material, and making the projection of the gate electrode of the second chip in the vertical direction completely exposed to the projection of the third chip;

[0035] S4, coating an adhesive material on the source electrode of the third chip, connecting the drain electrode of the fourth chip to the source electrode of the third chip through the adhesive material, and making the projection of the gate electrode of the third chip in the vertical direction completely exposed to the projection of the fourth chip;

[0036] S5, coating the gate of the first chip, the gate of the second chip, the gate of the third chip, the gate of the fourth chip, the source pin of the lead frame, and the gate pin of the lead frame with an adhesive material, and connecting the source pin and the source of the fourth chip with the source conductive plate through the adhesive material;

[0037] S6, connecting the gate conductive plate to the gate of the first chip, the gate of the second chip, the gate of the third chip, the gate of the fourth chip and the gate pin through an adhesive material;

[0038] S7, performing plastic sealing to form a plastic sealing body;

[0039] S8, singulating to obtain an exposed series dual chipset package.

[0040] A packaging method for an exposed series dual-chipset package, comprising the following steps:

[0041] S1, coating a conductive adhesive material on the base island, so that the drain electrode of the first chip is connected to the base island through the adhesive material;

[0042] S2, coating an adhesive material on the source electrode of the first chip, connecting the drain electrode of the second chip to the source electrode of the first chip through the adhesive material, and making the projection of the gate electrode of the first chip in the vertical direction completely exposed to the projection of the second chip;

[0043] S3, coating an adhesive material on the source electrode of the second chip, connecting the drain electrode of the third chip to the source electrode of the second chip through the adhesive material, and making the projection of the gate electrode of the second chip in the vertical direction completely exposed to the projection of the third chip;

[0044] S4, coating an adhesive material on the source electrode of the third chip, connecting the drain electrode of the fourth chip to the source electrode of the third chip through the adhesive material, and making the projection of the gate electrode of the third chip in the vertical direction completely exposed to the projection of the fourth chip;

[0045] S5, coating the gate of the first chip, the gate of the second chip, the gate of the third chip, the gate of the fourth chip, the source pin of the lead frame, and the gate pin of the lead frame with an adhesive material, and connecting the source pin and the source of the fourth chip with the source conductive plate through the adhesive material;

[0046] S6, connecting the first gate plate to the gate pin and the gate of the first chip, connecting the second gate plate to the gate of the second chip and the third gate plate, and connecting the third gate plate to the second gate plate, the gate of the third chip, the gate of the fourth chip, and the first gate plate;

[0047] S7, performing plastic sealing to form a plastic sealing body;

[0048] S8, singulating to obtain an exposed series dual chipset package.

[0049] A PCB board comprises at least one package as described above.

[0050] The present invention provides an exposed series dual-chipset package, which can achieve at least one of the following effects:

[0051] 1. It can improve the voltage strength under the condition of the same current and the same area of ​​plastic package;

[0052] 2. With the dual-chip set heteropolar series bonding plastic packaging structure, the manufacturing cost of at least one chip plastic packaging body can be reduced;

[0053] 3. The use of power chip heteropolar series bonding plastic packaging structure can reduce the development, production and packaging inventory costs of different power chips.

[0054] 4. By exposing the source conductive plate, the heat dissipation efficiency can be improved.

[0055] The invention provides a packaging method for an exposed series dual-chip set package, which has a simple process flow.

[0056] The present invention provides a PCB board, which can realize a plastic package with the same area, thereby reducing the increase in the use area and cost caused by the need to increase higher power when using the PCB board. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 1 ;

[0058] Figure 2 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 2 ;

[0059] Figure 3 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 3 ;

[0060] Figure 4 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 4 ;

[0061] Figure 5 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 5 ;

[0062] Figure 6 The internal structure of an exposed series dual chipset package provided by the present invention is schematically shown. Figure 6 ;

[0063] Figure 7 A schematic diagram of the internal structure of an exposed series dual chipset package provided by another embodiment;

[0064] Figure 8 A schematic diagram of the structure of an exposed series dual chipset package provided by the present invention;

[0065] Fig. 9 for Figure 8 Schematic diagram of the cross-sectional structure.

[0066] Description of reference numerals:

[0067] 00 bonding material; 10 base island; 11 drain pin; 12 source pin; 13 gate pin; 20 first chip; 21 second chip; 30 source conductive plate; 31 gate conductive plate; 311 first gate plate; 312 second gate plate; 313 third gate plate; 40 third chip; 41 fourth chip; 60 plastic package. DETAILED DESCRIPTION

[0068] A specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings, but it should be understood that the protection scope of the present invention is not limited by the specific implementation.

[0069] Embodiment 1:

[0070] like Figures 1 to 6 As shown, an exposed series dual chipset package provided by an embodiment of the present invention includes a lead frame, a plastic package 60, a first chipset, a second chipset, a source conductive plate 30 and a gate conductive plate 31, wherein the second chipset and the first chipset are stacked up and down, wherein:

[0071] The first chip group includes a first chip 20 and a second chip 21, the second chip 21 and the first chip 20 are stacked up and down, and the source of the first chip 20 is arranged opposite to the drain of the second chip 21; the drain of the first chip 20 is bonded to the drain pin 11 of the lead frame, and the source of the first chip 20 is bonded to the drain of the second chip 21;

[0072] The second chip group includes a third chip 40 and a fourth chip 41, wherein the fourth chip 41 and the third chip 40 are stacked up and down and the source of the third chip 40 is arranged opposite to the drain of the fourth chip 41; the drain of the third chip 40 is bonded to the source of the second chip 21;

[0073] The gates of the first chip 20 , the second chip 21 , the third chip 40 and the fourth chip 41 are all bonded to the gate pin 13 of the lead frame; the source of the fourth chip 41 is connected to the source pin 12 through the source conductive plate 30 , and part of the source conductive plate 30 is located outside the plastic package 60 .

[0074] In this embodiment, description is made by taking the example that the first chip 20 , the second chip 21 , the third chip 40 and the fourth chip 41 are all MOSFET power chips.

[0075] like Figure 1 and Figure 6 As shown, it shows the structural schematic diagram when some structures are omitted in turn. Figure 4 and Figure 5 The schematic diagram of the connection structure between the gate conductive plate 31 and the first chip 20 to the fourth chip 41 is shown. Figure 6 As shown, the source conductive plate 30, the fourth chip 41, the third chip 40, the second chip 21, the first chip 20 and the lead frame are arranged in sequence from top to bottom;

[0076] like Figure 1 As shown, the drain of the first chip 20 is connected to the drain pin 11 through the base island 10, and the drain of the second chip 21 is attached to the source of the first chip 20, as shown in FIG. Figure 4As shown, the drain of the third chip 40 is attached to the source of the second chip 21, and the drain of the fourth chip 41 is attached to the source of the third chip 40;

[0077] like Figure 2 As shown, the first chip 20 and the second chip 21 are staggered in a certain direction, so that the projection of the gate of the first chip 20 in the vertical direction is completely exposed to the projection of the second chip 21, so as to facilitate the subsequent gate bonding; Figure 4 As shown, the third chip 40 and the fourth chip 41 are staggered in a certain direction, and the staggered direction is the same as the staggered direction of the first chip 20 and the second chip 21, so that the projection of the gate of the third chip 40 in the vertical direction is completely exposed to the projection of the fourth chip 41, so as to facilitate the subsequent gate bonding;

[0078] like Figure 4 and Figure 5 As shown, the first chip group and the second chip group are staggered so that the projections of the gate of the first chip 20 and the gate of the second chip 21 along the vertical direction are completely exposed to the projections of the third chip 40 and the fourth chip 41 .

[0079] Specifically Figure 5 As shown in the example, the first chip 20 and the second chip 21 are staggered along the direction of the side where the drain pin 11 is located, and the third chip 40 and the fourth chip 41 are also staggered along the direction of the side where the drain pin 11 is located, and the staggered direction of the first chip group and the second chip group is perpendicular to the staggered direction of the side where the drain pin 11 is located.

[0080] like Figure 6 As shown, the source of the fourth chip 41 is connected to the source pin 12 through the source conductive plate 30; the gate of the first chip 20, the gate of the second chip 21, the gate of the third chip 40 and the gate of the fourth chip 41 are all connected to the gate pin 13 through the gate conductive plate 31. Specifically, as Figure 4 and Figure 5 As shown in the example, the gate conductive plate 31 is roughly an M-shaped structure and an N-shaped structure that are fixed together. The M-shaped structure includes three first bonding pins extending downward, and the three first bonding pins are respectively connected to the gate pin 13, the gate of the first chip 20, and the gate of the second chip 21. The N-shaped structure includes two second bonding pins extending downward, and the two second bonding pins are respectively connected to the gate of the third chip 40 and the gate of the fourth chip 41. The N-shaped structure is connected to the M-shaped structure. Through the gate conductive plate 31, the first chip 20, the second chip 21, the third chip 40, the fourth chip 41 and the gate pin 13 are bonded to each other to achieve electrical connection.

[0081] Since the drain of the second chip 21 and the source of the first chip 20 are in contact with each other, in order to enable the gate of the first chip 20 to be smoothly led out of the gate conductive plate 31 or the lead (when wire bonding is used) so as to enable bonding, the following methods can also be used to achieve the above purpose.

[0082] In the first mode, a metal spacer is provided between the first chip 20 and the second chip 21. The metal spacer can realize the conduction of the source of the first chip 20 and the drain of the second chip 21, and at the same time, a certain gap can be formed between the first chip 20 and the second chip 21, so that the lead can be led out through the gap, so that the gate of the first chip 20 is bonded to the gate pin 13. When the gate conductive plate 31 is used, one end of the gate conductive plate 31 is connected to the gate pin 13, and the other end forms two bonding antennae (such as two bonding wires), one bonding antennae is connected to the gate of the first chip 20, and the other bonding antennae is connected to the gate of the second chip 21. In this mode, the projections of the first chip 20 and the second chip 21 in the vertical direction do not need to be staggered. The same applies to the second chip 21 and the third chip 40, and the third chip 40 and the fourth chip 41.

[0083] In the second method, the first chip 20 and the second chip 21 may be arranged in a staggered manner so that the gate of the first chip 20 is exposed for bonding. Figures 1 to 6 A staggered arrangement is shown and described.

[0084] like Figure 7 As shown, another staggered arrangement is shown. The gate of the first chip 20 and the gate of the second chip 21 are located on opposite sides, the gate of the third chip 40 and the gate of the fourth chip 41 are located on opposite sides, and the gate of the second chip 21 and the gate of the third chip 40 are located on opposite sides. The gate conductive plate 31 includes a first gate plate 311, a second gate plate 312 and a third gate plate 313, the first gate plate 311 connects the gate of the first chip 20 and the gate pin 13, the second gate plate 312 connects the gate of the second chip 21 and the third gate plate 313, and the third gate plate 313 connects the gate of the third chip 40, the gate of the fourth chip 41 and the first gate plate 311; the source of the fourth chip 41 is connected to the source pin 12 through the source conductive plate 30.

[0085] It is understandable that the MOSFET power chip can also be adapted by changing the shape of the source conductive plate 30 and the gate conductive plate 31, and / or changing the position and shape of the source pin 12 and the gate pin 13 to achieve the MOSFET power chip series connection process.

[0086] In the third mode, the first chip 20 and the second chip 21 can be arranged overlapping in the vertical direction, and the second chip 21 can be rotated along its central axis, such as 45 degrees, to expose the gate of the first chip 20. The third chip 40 and the fourth chip 41 are similar and will not be described in detail.

[0087] Regardless of the method, the ultimate goal is to enable the gate of the first chip 20, the gate of the second chip 21, the gate of the third chip 40 and the gate of the fourth chip 41 to be bonded to the gate pin 13. It should be understood that those skilled in the art can also implement the technical solution of the present invention according to other general practices that can achieve the above purpose, which should also fall within the protection scope of the present invention.

[0088] It is worth noting that Figure 8 and Fig. 9 As shown, the upper end surface of the source conductive plate 30 is flush with the upper end surface of the plastic package 60, so that the upper end surface of the source conductive plate 30 is exposed to the air. This structure is beneficial for the source conductive plate 30 to better conduct the heat of the chip to the outside, so as to avoid the internal temperature of the plastic package 60 being too high and damaging the chip.

[0089] Specifically, the source conductive plate 30 and the gate conductive plate 31 are made of copper or aluminum.

[0090] Since the source of the MOSFET power chip is connected to the source pin 12 using a source conductive plate 30, and the gate is connected to the gate pin 13 using a gate conductive plate 31, it has a smaller on-resistance than the existing metal wire bonding. In addition, the conductive plate has a larger volume than the metal wire bonding, which can improve the heat absorption capacity and thus improve the instantaneous temperature fluctuation during operation.

[0091] Embodiment 2:

[0092] On the basis of the first embodiment, a connection portion is provided on one side of the source conductive plate 30 extending downward, and the connection portion is connected to the source pin 12; a receiving groove is provided on the source pin 12, and the receiving groove matches the connection portion. Through the cooperation of the receiving groove and the connection portion, the connection portion of the source conductive plate 30 can be mounted in the receiving groove, and connected using a conductive adhesive material 00, so that when the source conductive plate 30 is installed, the source conductive plate 30 can be limited, so that more precise alignment can be achieved, and during packaging, the problem of deflection, rotation or warping of the source conductive plate 30 caused by the flow of the conductive adhesive material 00 can be improved.

[0093] Embodiment three:

[0094] A packaging method for an exposed series dual-chipset package, comprising the following steps:

[0095] S1, coating a conductive adhesive material 00 on the base island 10, so that the drain of the first chip 20 is connected to the base island 10 through the adhesive material 00, and the conductive adhesive material 00 can be selected from metal solder paste, conductive silver glue or other conductive adhesive materials 00;

[0096] S2, coating the adhesive material 00 on the source electrode of the first chip 20, connecting the drain electrode of the second chip 21 to the source electrode of the first chip 20 through the adhesive material 00, and making the projection of the gate electrode of the first chip 20 in the vertical direction completely exposed to the projection of the second chip 21;

[0097] S3, coating the adhesive material 00 on the source electrode of the second chip 21, connecting the drain electrode of the third chip 40 to the source electrode of the second chip 21 through the adhesive material 00, and making the projection of the gate electrode of the second chip 21 in the vertical direction completely exposed to the projection of the third chip 40;

[0098] S4, coating the source electrode of the third chip 40 with an adhesive material 00, connecting the drain electrode of the fourth chip 41 to the source electrode of the third chip 40 through the adhesive material 00, and making the projection of the gate electrode of the third chip 40 in the vertical direction completely exposed to the projection of the fourth chip 41;

[0099] S5, coating the gate of the first chip 20, the gate of the second chip 21, the gate of the third chip 40, the gate of the fourth chip 41, the source pin 12 of the lead frame, and the gate pin 13 of the lead frame with an adhesive material 00, and connecting the source conductive plate 30 to the source pin 12 and the source of the fourth chip 41 through the adhesive material 00;

[0100] S6, connecting the gate conductive plate 31 to the gate of the first chip 20, the gate of the second chip 21, the gate of the third chip 40, the gate of the fourth chip 41 and the gate pin 13 through the adhesive material 00;

[0101] S7, performing plastic sealing to form a plastic sealing body 60;

[0102] S8, singulating to obtain an exposed series dual chipset package.

[0103] Through this packaging method, two MOSFET power chips can be connected in series.

[0104] In another embodiment, the gate conductive plate 31 includes a first gate plate 311, a second gate plate 312 and a third gate plate 313, and the above-mentioned S6 step is: connecting the first gate plate 311 to the gate pin 13 and the gate of the first chip 20, connecting the second gate plate 312 to the gate of the second chip 21 and the third gate plate 313, connecting the third gate plate 313 to the second gate plate 312, the gate of the third chip 40, the gate of the fourth chip 41 and the first gate plate 311, and the rest is the same as the above steps.

[0105] Embodiment 4:

[0106] A PCB board includes at least one of the above-mentioned packages, and the specific number of packages is determined according to the design of the PCB board. During the packaging process, the series connection of the dual MOSFET power chipset is completed. When the application requires a higher voltage requirement, the PCB board only needs to install and weld an embedded series dual chipset package, which can avoid mounting more packages of single MOSFET power chips on the PCB board. In addition to saving the area cost required for the PCB board, it can also reduce the use and production cost of the MOSFET power chip package.

[0107] The above disclosures are only several specific embodiments of the present invention. However, the embodiments of the present invention are not limited thereto. Any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. An exposed series dual chipset package, comprising a lead frame and a plastic package (60), characterized in that: It also includes a first chip group, a second chip group, a source conductive plate (30) and a gate conductive plate (31); The first chipset comprises a first chip (20) and a second chip (21), the second chipset comprises a third chip (40) and a fourth chip (41), and the second chipset and the first chipset are stacked one above the other; wherein: The source conductive plate (30), the fourth chip (41), the third chip (40), the second chip (21), the first chip (20) and the lead frame are arranged in sequence from top to bottom; The drain of the first chip (20) is connected to the drain pin (11) through the base island (10), the drain of the second chip (21) is bonded to the source of the first chip (20), the drain of the third chip (40) is bonded to the source of the second chip (21), and the drain of the fourth chip (41) is bonded to the source of the third chip (40); The source of the fourth chip (41) is connected to the source pin (12) through the source conductive plate (30); The gate of the first chip (20), the gate of the second chip (21), the gate of the third chip (40) and the gate of the fourth chip (41) are all connected to the gate pin (13) through the gate conductive plate (31); wherein: The source conductive plate (30) is partially located outside the plastic package (60); The gate conductive plate (31) comprises a first gate plate (311), a second gate plate (312) and a third gate plate (313); The first chip (20) and the second chip (21) are arranged in a staggered manner so that the projection of the gate of the first chip (20) in the vertical direction is completely exposed to the projection of the second chip (21); the third chip (40) and the fourth chip (41) are arranged in a staggered manner so that the projection of the gate of the third chip (40) in the vertical direction is completely exposed to the projection of the fourth chip (41); the second chip (21) and the third chip (40) are arranged in a staggered manner so that the projection of the gate of the second chip (21) in the vertical direction is completely exposed to the projection of the third chip (40); The first gate plate (311) connects the gate of the first chip (20) and the gate pin (13), the second gate plate (312) connects the gate of the second chip (21) and the third gate plate (313), and the third gate plate (313) connects the gate of the third chip (40), the gate of the fourth chip (41) and the first gate plate (311).

2. The exposed series dual chipset package as claimed in claim 1, characterized in that: A connecting portion is extended from one side of the source conductive plate (30), and the connecting portion is connected to the source pin (12) of the lead frame; a receiving groove is provided on the source pin (12), and the receiving groove matches the connecting portion.

3. The exposed series dual chipset package as claimed in claim 1, characterized in that: The source conductive plate (30) and the gate conductive plate (31) are made of copper or aluminum.

4. The exposed series dual chipset package as claimed in claim 1, characterized in that: A metal spacer is provided between the first chip (20) and the second chip (21); a source electrode of the first chip (20) and a drain electrode of the second chip (21) are connected via the metal spacer; the metal spacer forms a bonding space for accommodating a bonding wire between the first chip (20) and the second chip (21); A metal spacer is provided between the second chip (21) and the third chip (40); the source electrode of the second chip (21) and the drain electrode of the third chip (40) are connected via the metal spacer; the metal spacer forms a bonding space for accommodating a bonding wire between the second chip (21) and the third chip (40); A metal spacer is arranged between the third chip (40) and the fourth chip (41); the source of the third chip (40) and the drain of the fourth chip (41) are connected via the metal spacer; the metal spacer forms a bonding space for accommodating bonding wires between the third chip (40) and the fourth chip (41).

5. The packaging method of the exposed series dual chipset package according to claim 1, characterized in that: The steps include: S1, coating an adhesive material (00) on the base island (10), so that the drain electrode of the first chip (20) is connected to the base island (10) through the adhesive material (00); S2, coating an adhesive substance (00) on the source electrode of the first chip (20), connecting the drain electrode of the second chip (21) to the source electrode of the first chip (20) through the adhesive substance (00), and making the projection of the gate electrode of the first chip (20) in the vertical direction completely exposed to the projection of the second chip (21); S3, coating an adhesive substance (00) on the source electrode of the second chip (21), connecting the drain electrode of the third chip (40) to the source electrode of the second chip (21) through the adhesive substance (00), and making the projection of the gate electrode of the second chip (21) in the vertical direction completely exposed to the projection of the third chip (40); S4, coating an adhesive material (00) on the source electrode of the third chip (40), connecting the drain electrode of the fourth chip (41) to the source electrode of the third chip (40) through the adhesive material (00), and making the projection of the gate electrode of the third chip (40) in the vertical direction completely exposed to the projection of the fourth chip (41); S5, coating the gate of the first chip (20), the gate of the second chip (21), the gate of the third chip (40), the gate of the fourth chip (41), the source pin (12) of the lead frame, and the gate pin (13) of the lead frame with an adhesive substance (00), and connecting the source pin (12) and the source of the fourth chip (41) with the source conductive plate (30) through the adhesive substance (00); S6, connecting the first gate plate (311) to the gate pin (13) and the gate of the first chip (20), connecting the second gate plate (312) to the gate of the second chip (21) and the third gate plate (313), and connecting the third gate plate (313) to the second gate plate (312), the gate of the third chip (40), the gate of the fourth chip (41), and the first gate plate (311); S7, performing plastic sealing to form a plastic sealing body (60); S8, singulating to obtain an exposed series dual chipset package.

6. A PCB board, characterized in that: Comprising at least one package according to any one of claims 1 to 4.

Images