Brushless DC motor control circuit and method based on PWM-ON control mode

Abstract

The present invention relates to a brushless DC motor control circuit based on a PWM-ON control mode, which belongs to the field of brushless DC motor commutation technology and solves the problem of the lack of brushless DC motor control peripheral circuits for the PWM-ON control mode in the prior art. A brushless DC motor control circuit based on a PWM-ON control mode comprises: a commutation control logic circuit, which generates a commutation control logic signal adapted to the PWM-ON control mode based on a direction control signal, a PWM signal and a position Hall signal output by a brushless DC motor; the power main circuit, based on the commutation control logic signal, controls the power main circuit to execute the PWM-ON control process and outputs a motor input control signal for driving the DC motor to work.

Description

Technical Field

[0001] The present invention relates to the technical field of brushless DC motor commutation, and in particular to a brushless DC motor control circuit and method based on a PWM-ON control mode. Background Art

[0002] At present, there are mainly two methods for the commutation control circuit of a brushless DC motor. The first method is a method that adopts a position sensor, a bridge drive circuit and a processor chip to jointly implement the method. The processor chip collects the signal of the position sensor, and outputs a control signal to control the bridge drive circuit to realize the commutation of the motor according to the commutation control algorithm. The advantages of this method are mature technology and simple control algorithm, but the disadvantages are that due to the need for a processor chip and peripheral circuits, the circuit is complex, large in size, and high in cost, which is limited when used in low-cost applications. The second method is a method without a position sensor, which uses a processor chip, a control algorithm and a detection circuit to jointly realize the commutation of the motor. The advantage of this method is that the position sensor is omitted and the motor leads are reduced, but the disadvantage is that the detection circuit and the control algorithm are relatively complex, and the processor chip and the control algorithm need to be combined, resulting in high cost, reduced reliability, and large switching loss and motor loss.

[0003] The PWM-ON control method is a common power main circuit. However, the prior art lacks a brushless DC motor control peripheral circuit for this control method, which severely limits the application scope of the brushless DC motor drive circuit. Summary of the invention

[0004] In view of the above analysis, an embodiment of the present invention aims to provide a brushless DC motor control circuit and method based on PWM-ON control mode, so as to solve the problem of lack of brushless DC motor control peripheral circuit for PWM-ON control mode in the prior art.

[0005] On the one hand, the present invention discloses a brushless DC motor control circuit based on PWM-ON control mode, comprising:

[0006] A commutation control logic circuit generates a commutation control logic signal adapted to a PWM-ON control mode based on a direction control signal, a PWM signal and a position Hall signal output by a brushless DC motor;

[0007] The power main circuit controls the power main circuit to perform a PWM-ON regulation process based on the commutation control logic signal, and outputs a motor input control signal for driving the DC motor to work.

[0008] On the basis of the above scheme, the present invention also makes the following improvements:

[0009] Furthermore, it also includes a driving circuit for driving and amplifying the phase-changing control logic signal, and the power main circuit generates the motor input control signal based on the phase-changing control logic signal after driving and amplifying.

[0010] Furthermore, a position sensor is included for collecting the position Hall signal.

[0011] Furthermore, the position Hall signal includes an A-phase position Hall signal, a B-phase position Hall signal and a C-phase position Hall signal.

[0012] Furthermore, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR and the commutation control logic signals S1-S6 is:

[0013] If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is a PWM signal, signals S2, S3, S4, and S5 are low level, and signal S6 is high level;

[0014] If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is at a high level, signals S3, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal;

[0015] If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level;

[0016] If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal;

[0017] If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level;

[0018] If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal;

[0019] When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

[0020] Further, the signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

[0021] Furthermore, if the waveform of S1 is a PWM signal, signals S2, S3, S4, and S5 are all low levels, and signal S6 is high level, then the input control signal UA of the A-phase brushless DC motor is an alternating change between DC+ / 2 and 0: when the PWM signal is high level, it is DC+ / 2, and when the PWM signal is low level, it is 0; the input control signal UB of the B-phase brushless DC motor is 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2;

[0022] If the waveform of signal S1 is high level, signals S3, S4, S5, S6 are all low level, and signal S2 is a PWM signal, then UA is DC+ / 2; UC is the alternating change between DC+ / 2 and 0; UB is the linear increase from -DC+ / 2 to DC+ / 2;

[0023] If the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level, then UB is an alternating change between DC+ / 2 and 0, UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0024] If the waveform of signal S3 is high level, signals S1, S2, S5, and S6 are all low level, and signal S4 is a PWM signal, then UB is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0025] If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level, then UC is an alternating change between DC+ / 2 and 0, UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0026] If the waveform of signal S5 is high level, signals S1, S2, S3, and S4 are all low level, and signal S6 is a PWM signal, then UC is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

[0027] Furthermore, the commutation control logic circuit includes: the commutation control logic circuit includes: S1-S6 control logic modules, logical NOT modules, each control logic module is composed of an AND gate and an OR gate; the logical NOT module includes NOT gates 1-4, which are used to perform logical NOT operations on HA, HB, HC and DIR respectively and then output signals HA1, HB1, HC1 and DIR1; wherein:

[0028] The S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S2' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1;

[0029] The S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 8 and AND gate 10 respectively, and the output end of OR gate 3 outputs signal S3'; the two input ends of AND gate 11 receive signals S3' and S4' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3;

[0030] The S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 are connected to the output end of the AND gate 13 and the signal DIR respectively; the two input ends of the AND gate 15 receive signals HC1 and HA respectively, and the two input ends of the AND gate 16 are connected to the output end of the AND gate 15 and the signal DIR1 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 14 and the AND gate 16 respectively, and the output end of the OR gate 5 outputs a signal S5'; the two input ends of the AND gate 17 receive signals S6' and S5' respectively; the two input ends of the AND gate 18 receive signals S5' and PWM respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 17 and the AND gate 18 respectively; the output end of the OR gate 6 outputs a signal S5;

[0031] The S2 control logic module includes AND gates 19-26 and OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 7 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 7 outputs signal S2'; the two input ends of AND gate 25 receive signals S3' and S2' respectively; the two input ends of AND gate 26 receive signals S2' and PWM respectively; the two input ends of OR gate 8 are connected to the output ends of AND gate 25 and AND gate 26 respectively; the output end of OR gate 8 outputs signal S2;

[0032] The S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the output end of OR gate 9 outputs signal S4'; the two input ends of AND gate 33 receive signals S4' and S5' respectively; the two input ends of AND gate 34 receive signals S4' and PWM respectively; the two input ends of OR gate 10 are connected to the output ends of AND gate 33 and AND gate 34 respectively; the output end of OR gate 10 outputs signal S4;

[0033] The S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input ends of AND gate 35 receive signals HB and HC1 respectively, and the two input ends of AND gate 36 receive signals DIR1 and ST respectively; the two input ends of AND gate 37 are connected to the output ends of AND gate 35 and AND gate 36 respectively; the two input ends of AND gate 38 receive signals HB1 and HC respectively, and the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S1' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM respectively; the two input ends of OR gate 12 are connected to the input ends of AND gate 41 and AND gate 42 respectively, and the output end of OR gate 12 outputs signal S6;

[0034] The signal ST is 1.

[0035] Furthermore, the driving circuit includes three IR2110 driving chips, and each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit.

[0036] On the other hand, the present invention also discloses a brushless DC motor control method based on PWM-ON control mode, comprising the following steps:

[0037] Based on the direction control signal, PWM signal and the position Hall signal output by the brushless DC motor, a commutation control logic signal suitable for the PWM-ON control mode is generated;

[0038] Based on the commutation control logic signal, the power main circuit is controlled to perform a PWM-ON regulation process, and a motor input control signal for driving the DC motor to work is output.

[0039] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0040] The brushless DC motor commutation drive circuit provided by the present invention can realize the commutation control of the brushless DC motor by adopting a commutation control logic circuit, and only one PWM signal and one square control signal are used. At this time, the power main circuit control mode adopts the PWM-ON mode, which solves the problem of the lack of peripheral circuits for brushless DC motor control in the prior art for the PWM-ON control mode, and is conducive to reducing switching loss and motor loss. The circuit has the advantages of high reliability, small size, low cost, etc.

[0041] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0043] Figure 1 The brushless DC motor control circuit based on PWM-ON control mode in Embodiment 1 of the present invention;

[0044] Figure 2 The phase-change control logic circuit in Embodiment 1 of the present invention;

[0045] Figure 3 The driving circuit in Embodiment 1 of the present invention;

[0046] Figure 4 The main power circuit in Embodiment 1 of the present invention;

[0047] Figure 5 This is a flow chart of the brushless DC motor control method based on PWM-ON control mode in Example 2 of the present invention. DETAILED DESCRIPTION

[0048] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0049] Example 1

[0050] A specific embodiment 1 of the present invention discloses a brushless DC motor control circuit based on PWM-ON control mode, the structural diagram of which is shown in FIG. Figure 1 As shown, it includes: a commutation control logic circuit (adapted to the PWM-ON control mode), which generates a commutation control logic signal adapted to the PWM-ON control mode based on the direction control signal, the PWM signal and the position Hall signal output by the brushless DC motor; the power main circuit (based on the PWM-ON control mode), based on the commutation control logic signal, controls the power main circuit to execute the PWM-ON control process, and outputs a motor input control signal for driving the DC motor to work.

[0051] Compared with the prior art, the brushless DC motor control circuit based on PWM-ON regulation mode provided in this embodiment is designed in conjunction with the PWM modulation mode of the power main circuit. The commutation control of the brushless DC motor can be achieved through only one PWM signal and one direction control signal, which solves the problem of the lack of peripheral circuits for brushless DC motor control in the prior art for PWM-ON regulation mode. It has the advantages of simple circuit structure, high reliability, and small size, and is also beneficial to reducing switching loss and motor loss.

[0052] The brushless DC motor control circuit also includes a driving circuit for driving and amplifying the commutation control logic signal, and the power main circuit generates the motor input control signal based on the commutation control logic signal after driving and amplification; and also includes a position sensor for collecting the position Hall signal.

[0053] It should be noted that the direction control signal in this embodiment is used to indicate whether the brushless DC motor rotates forward or reversely. In this embodiment, when the motor is controlled to rotate forward, the direction control signal DIR is set to a high level; when the motor is controlled to rotate reversely, the direction control signal DIR is set to a low level; in addition, the PWM signal in this embodiment is used to adjust the speed of the brushless DC motor. Optionally, the frequency of the PWM signal can be set to 5k~20kz, and the duty cycle d of the PWM signal ranges from 0 to 1. The motor speed regulation can be achieved by changing the duty cycle of the PWM signal: the larger the duty cycle, the higher the corresponding motor speed; the smaller the duty cycle, the smaller the corresponding motor speed; a duty cycle of 1 corresponds to the highest adjustable speed, and a duty cycle of 0 corresponds to the lowest adjustable speed (i.e., 0 speed).

[0054] like Figure 1As shown, the position Hall signals output by the brushless DC motor include the A-phase position Hall signal HA, the B-phase position Hall signal HB, and the C-phase position Hall signal HC; the corresponding signals of the position Hall signals HA, HB, HC and the direction control signal DIR after the signal shaping circuit performs a negation logic operation are represented as HA1, HB1, HC1, and DIR1 respectively; the commutation control logic circuit processes the signals HA, HB, HC, DIR, HA1, HB1, HC1, DIR1 and the PWM signal, and outputs the commutation logic signals S1-S6; among which, the signals S1, S3, S5 is the switching control logic signal for the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; signals S2, S4, and S6 are the switching control logic signals for the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on the same bridge arm, and the connection point of VT1 and VT4 outputs signal UA; VT3 and VT6 are on the same bridge arm, and the connection point of VT3 and VT6 outputs signal UB; VT5 and VT2 are on the same bridge arm, and the connection point of VT5 and VT2 outputs signal UC. After being driven by the driving circuit, signals S1-S6 output driving signals G1-G6, wherein signal S1 drives the amplified output signal G1, signal S2 drives the amplified output signal G2, signal S3 drives the amplified output signal G3, signal S4 drives the amplified output signal G4, signal S5 drives the amplified output signal G5, and signal S6 drives the amplified output signal G6. The power main circuit adjusts the opening or closing of the power tubes VT1-VT6 according to the drive signals G1-G6, and outputs the brushless DC motor input control signals UA, UB, UC, and uses UA, UB, UC to control the rotation of the brushless DC motor. Specifically, the signals G1, G2, G3, G4, G5, and G6 perform PWM chopping control in the first 60° of their respective 120° conduction cycles, are constantly on for the next 60°, and are constantly off in the remaining 240°. Therefore, when the power main circuit control mode adopts the PWM-ON mode, it is beneficial to reduce switching losses and motor losses.

[0055] When the motor rotates one circle, the position Hall signals HA, HB, and HC will have six states, namely "101", "100", "110", "010", "011", and "001". Assuming that the duty cycle of the PWM signal is d (the range of duty cycle d is 0 to 1), then when the PWM modulation mode is PWM-ON mode (that is, the upper bridge arm is in PWM chopping mode, and the lower bridge arm is in a constant on or constant off state), the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0056] If HA, HB, HC, and DIR are "1011" or "0100", after passing through the commutation circuit, the waveform of signal S1 is a PWM signal with a duty cycle of d, signals S2, S3, S4, and S5 are low levels, and signal S6 is high level; after passing through the drive circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G2, G3, G4, and G5 are all low levels, and G6 is high level. When passing through the power main circuit, VT1 of the power main circuit is modulated by the G1 signal and is in an alternating on-off action (when G1 is 1 , VT1 is turned on, G1 is 0, VT1 is turned off), VT2, VT3, VT4, and VT5 of the power main circuit are all turned off, and VT6 is turned on due to the high level of G6. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when the PWM signal takes a high level, VT1 is turned on, UA is DC+ / 2; when the PWM signal takes a low level, VT1 is turned off, UA is 0), UB is 0, and UC is a linear decrease from DC+ / 2 to -DC+ / 2 (when HA, HB, and HC are "101");

[0057] If HA, HB, HC, DIR are "1001" or "0110", after passing through the commutation circuit, signal S1 is high, signals S3, S4, S5, S6 are all low, and signal S2 is a PWM signal; after passing through the drive circuit, G1 is high, G3, G4, G5, G6 are all low, and the waveform of G2 is a PWM signal with a duty cycle of d. When passing through the power main circuit, VT1 of the power main circuit is turned on due to the high level of G1, and VT3, VT4, VT5, VT6 of the power main circuit are all turned off. VT2 is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is turned on, and when G2 is 0, VT2 is turned off). At this time, UA of the power main circuit is DC+ / 2; UC is an alternating change between DC+ / 2 and 0; UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0058] If HA, HB, HC, and DIR are "1101" or "0010", after passing through the commutation circuit, the waveform of signal S3 is a PWM signal with a duty cycle of d, and signals S1, S4, S5, and S6 are all low levels, and signal S2 is a high level; after passing through the drive circuit, the waveform of G3 is a PWM signal with a duty cycle of d, and G1, G4, G5, and G6 are all low levels, and G2 is a high level. When passing through the power main circuit, VT3 of the power main circuit is affected by the G3 signal The modulation is in the on-off alternating action (when G3 is 1, VT3 is on, when G3 is 0, VT3 is off), VT1, VT4, VT5, VT6 of the power main circuit are all off, VT2 is turned on due to the high level of G2, at this time, UB of the power main circuit is the alternating change of DC+ / 2 and 0 (when VT3 is on, UB is DC+ / 2, when VT3 is off, UB is 0), UC is 0, and UA is the linear decrease from DC+ / 2 to -DC+ / 2;

[0059] If HA, HB, HC, DIR are "0101" or "1010", after passing through the commutation circuit, signal S3 is high, signals S1, S2, S5, S6 are all low, and signal S4 is a PWM signal; after passing through the drive circuit, G3 is high, G1, G2, G5, G6 are all low, and the waveform of G4 is a PWM signal with a duty cycle of d. When passing through the power main circuit, VT3 of the power main circuit is turned on due to the high level of G3, and VT1, VT2, VT5, and VT6 of the power main circuit are all turned off. VT4 is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is turned on, and when G4 is 0, VT4 is turned off). At this time, UB of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0060] If HA, HB, HC, and DIR are "0111" or "1000", after passing through the commutation circuit, signal S5 is a PWM signal with a duty cycle of d, signals S1, S2, S3, and S6 are all low levels, and signal S4 is high level; after passing through the drive circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, and G6 are all low levels, and G4 is high level. When passing through the power main circuit, VT5 of the power main circuit is affected by the G5 signal. Modulation is in the on-off alternating action (when G5 is 1, VT5 is on, when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT4 is turned on due to the high level of G4. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT5 is on, UC is DC+ / 2, when VT5 is off, UC is 0), UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0061] If HA, HB, HC, and DIR are "0011" or "1100", after passing through the commutation circuit, signal S5 is high, signals S1, S2, S3, and S4 are all low, and signal S6 is a PWM signal; after passing through the drive circuit, G5 is high, G1, G2, G3, and G4 are all low, and the waveform of G6 is a PWM signal with a duty cycle of d. When passing through the power main circuit, VT5 of the power main circuit is turned on due to the high level of G5, and VT1, VT2, VT3, and VT4 of the power main circuit are all turned off. VT6 is modulated by the G6 signal and is in an alternating on-off action (when G6 is 1, VT6 is turned on, and when G6 is 0, VT6 is turned off). At this time, UC of the power main circuit is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

[0062] Preferably, the commutation control logic circuit is as follows Figure 2 As shown, the phase-change control logic circuit includes: S1-S6 control logic modules and a logic NOT module, each of which is composed of an AND gate and an OR gate; the logic NOT module includes NOT gates 1-4, which are used to perform logic NOT operations on HA, HB, HC and DIR respectively and then output signals HA1, HB1, HC1 and DIR1; wherein:

[0063] The S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S2' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1;

[0064] The S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 8 and AND gate 10 respectively, and the output end of OR gate 3 outputs signal S3'; the two input ends of AND gate 11 receive signals S3' and S4' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3;

[0065] The S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 are connected to the output end of the AND gate 13 and the signal DIR respectively; the two input ends of the AND gate 15 receive signals HC1 and HA respectively, and the two input ends of the AND gate 16 are connected to the output end of the AND gate 15 and the signal DIR1 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 14 and the AND gate 16 respectively, and the output end of the OR gate 5 outputs a signal S5'; the two input ends of the AND gate 17 receive signals S6' and S5' respectively; the two input ends of the AND gate 18 receive signals S5' and PWM respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 17 and the AND gate 18 respectively; the output end of the OR gate 6 outputs a signal S5;

[0066] The S2 control logic module includes AND gates 19-26 and OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 7 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 7 outputs signal S2'; the two input ends of AND gate 25 receive signals S3' and S2' respectively; the two input ends of AND gate 26 receive signals S2' and PWM respectively; the two input ends of OR gate 8 are connected to the output ends of AND gate 25 and AND gate 26 respectively; the output end of OR gate 8 outputs signal S2;

[0067] The S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the output end of OR gate 9 outputs signal S4'; the two input ends of AND gate 33 receive signals S4' and S5' respectively; the two input ends of AND gate 34 receive signals S4' and PWM respectively; the two input ends of OR gate 10 are connected to the output ends of AND gate 33 and AND gate 34 respectively; the output end of OR gate 10 outputs signal S4;

[0068] The S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input ends of AND gate 35 receive signals HB and HC1 respectively, and the two input ends of AND gate 36 receive signals DIR1 and ST respectively; the two input ends of AND gate 37 are connected to the output ends of AND gate 35 and AND gate 36 respectively; the two input ends of AND gate 38 receive signals HB1 and HC respectively, and the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S1' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM respectively; the two input ends of OR gate 12 are connected to the input ends of AND gate 41 and AND gate 42 respectively, and the output end of OR gate 12 outputs signal S6; signal ST is 1.

[0069] Drive circuit such as Figure 3 As shown, it includes three IR2110 driver chips, each of which is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; after power-on, the SD pin of each IR2110 driver chip is connected to a low level. Figure 4 shown.

[0070] Example 2

[0071] A specific embodiment 2 of the present invention discloses a brushless DC motor control method based on PWM-ON control mode, the flow chart is as follows: Figure 5 As shown, the following steps are included:

[0072] Step S1: generating a commutation control logic signal adapted to a PWM-ON control mode based on a direction control signal, a PWM signal and a position Hall signal output by a brushless DC motor;

[0073] Step S2: Based on the commutation control logic signal, the power main circuit is controlled to execute the PWM-ON regulation process, and an input control signal for driving the DC motor to work is output.

[0074] Preferably, a step of driving and amplifying the commutation control logic signal may be included between steps S1 and S2, and the power main circuit generates the motor input control signal based on the driven and amplified commutation control logic signal.

[0075] The specific implementation process of the embodiment of the present method can refer to the above-mentioned circuit embodiment. For example, a phase-changing control logic signal is generated based on a phase-changing control logic circuit, the drive signal is generated based on a drive circuit, and an overcurrent protection signal is generated based on an overcurrent protection circuit. This embodiment will not be repeated here.

[0076] Since the principle of this embodiment is the same as that of the above circuit embodiment, the method also has the corresponding technical effects of the above circuit embodiment.

[0077] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0078] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A brushless DC motor control circuit based on PWM-ON control mode, characterized in that: include: A commutation control logic circuit generates a commutation control logic signal adapted to a PWM-ON control mode based on a direction control signal, a PWM signal and a position Hall signal output by a brushless DC motor; A power main circuit, based on the commutation control logic signal, controls the power main circuit to perform a PWM-ON control process and outputs a motor input control signal for driving the DC motor to work; The commutation control logic circuit includes: the commutation control logic circuit includes: S1-S6 control logic modules, logical NOT modules, each control logic module is composed of an AND gate and an OR gate; the logical NOT module includes NOT gates 1-4, which are used to perform logical NOT operations on HA, HB, HC and DIR respectively and then output signals HA1, HB1, HC1 and DIR1; wherein: The S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S2' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1; The S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 8 and AND gate 10 respectively, and the output end of OR gate 3 outputs signal S3'; the two input ends of AND gate 11 receive signals S3' and S4' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3; The S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 are connected to the output end of the AND gate 13 and the signal DIR respectively; the two input ends of the AND gate 15 receive signals HC1 and HA respectively, and the two input ends of the AND gate 16 are connected to the output end of the AND gate 15 and the signal DIR1 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 14 and the AND gate 16 respectively, and the output end of the OR gate 5 outputs a signal S5'; the two input ends of the AND gate 17 receive signals S6' and S5' respectively; the two input ends of the AND gate 18 receive signals S5' and PWM respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 17 and the AND gate 18 respectively; the output end of the OR gate 6 outputs a signal S5; The S2 control logic module includes AND gates 19-26 and OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 7 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 7 outputs signal S2'; the two input ends of AND gate 25 receive signals S3' and S2' respectively; the two input ends of AND gate 26 receive signals S2' and PWM respectively; the two input ends of OR gate 8 are connected to the output ends of AND gate 25 and AND gate 26 respectively; the output end of OR gate 8 outputs signal S2; The S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the output end of OR gate 9 outputs signal S4'; the two input ends of AND gate 33 receive signals S4' and S5' respectively; the two input ends of AND gate 34 receive signals S4' and PWM respectively; the two input ends of OR gate 10 are connected to the output ends of AND gate 33 and AND gate 34 respectively; the output end of OR gate 10 outputs signal S4; The S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input ends of AND gate 35 receive signals HB and HC1 respectively, and the two input ends of AND gate 36 receive signals DIR1 and ST respectively; the two input ends of AND gate 37 are connected to the output ends of AND gate 35 and AND gate 36 respectively; the two input ends of AND gate 38 receive signals HB1 and HC respectively, and the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S1' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM respectively; the two input ends of OR gate 12 are connected to the input ends of AND gate 41 and AND gate 42 respectively, and the output end of OR gate 12 outputs signal S6; The signal ST is 1.

2. The brushless DC motor control circuit based on PWM-ON control method according to claim 1, characterized in that: It also includes a driving circuit for driving and amplifying the phase-changing control logic signal, and the power main circuit generates the motor input control signal based on the phase-changing control logic signal after driving and amplifying.

3. The brushless DC motor control circuit based on PWM-ON control mode according to claim 1, characterized in that: It also includes a position sensor for collecting the position Hall signal.

4. The brushless DC motor control circuit based on PWM-ON control mode according to any one of claims 1 to 3, characterized in that: The position Hall signal includes an A-phase position Hall signal, a B-phase position Hall signal, and a C-phase position Hall signal.

5. The brushless DC motor control circuit based on PWM-ON control mode according to claim 4, characterized in that: The corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR and the commutation control logic signals S1-S6 is: If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is a PWM signal, signals S2, S3, S4, and S5 are low level, and signal S6 is high level; If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is at a high level, signals S3, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal; If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level; If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is at a high level, signals S1, S2, S5, and S6 are all at low levels, and signal S4 is a PWM signal; If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level; If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is at a high level, signals S1, S2, S3, and S4 are all at low levels, and signal S6 is a PWM signal; When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

6. The brushless DC motor control circuit based on PWM-ON control mode according to claim 5, characterized in that: The signals S1, S3, and S5 are respectively used to control the opening or closing of the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; the signals S2, S4, and S6 are respectively used to control the opening or closing of the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on one bridge arm, VT3 and VT6 are on one bridge arm, and VT5 and VT2 are on one bridge arm.

7. The brushless DC motor control circuit based on PWM-ON control mode according to claim 6, characterized in that: If the waveform of S1 is a PWM signal, signals S2, S3, S4, and S5 are all low levels, and signal S6 is high level, then the input control signal UA of the A-phase brushless DC motor is an alternating change between DC+ / 2 and 0: when the PWM signal is high level, it is DC+ / 2, and when the PWM signal is low level, it is 0; the input control signal UB of the B-phase brushless DC motor is 0; the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S1 is high level, signals S3, S4, S5, S6 are all low level, and signal S2 is a PWM signal, then UA is DC+ / 2; UC is the alternating change between DC+ / 2 and 0; UB is the linear increase from -DC+ / 2 to DC+ / 2; If the waveform of signal S3 is a PWM signal, signals S1, S4, S5, and S6 are all low level, and signal S2 is high level, then UB is an alternating change between DC+ / 2 and 0, UC is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S3 is high level, signals S1, S2, S5, and S6 are all low level, and signal S4 is a PWM signal, then UB is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2; If the waveform of signal S5 is a PWM signal, signals S1, S2, S3, and S6 are all low level, and signal S4 is high level, then UC is an alternating change between DC+ / 2 and 0, UA is 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2; If the waveform of signal S5 is high level, signals S1, S2, S3, and S4 are all low level, and signal S6 is a PWM signal, then UC is DC+ / 2, UB is an alternating change between DC+ / 2 and 0, and UA is a linear increase from -DC+ / 2 to DC+ / 2.

8. The brushless DC motor control circuit based on PWM-ON control mode according to claim 2, characterized in that: The driving circuit includes three IR2110 driving chips, and each IR2110 driving chip is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit.

9. A brushless DC motor control method based on PWM-ON control mode, characterized in that: The control method is implemented based on the brushless DC motor control circuit based on the PWM-ON control method according to any one of claims 1 to 8, and the control method comprises the following steps: Based on the direction control signal, PWM signal and the position Hall signal output by the brushless DC motor, a commutation control logic signal suitable for the PWM-ON control mode is generated; Based on the commutation control logic signal, the power main circuit is controlled to perform a PWM-ON regulation process, and a motor input control signal for driving the DC motor to work is output.

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