Brushless DC motor control circuit and method based on ON-PWM control mode

Abstract

The present invention relates to a brushless DC motor control circuit based on ON‑PWM control mode, which belongs to the field of brushless DC motor commutation technology and solves the problem of large switching loss and motor loss in the commutation control circuit in the prior art. The brushless DC motor control circuit based on ON‑PWM control mode includes: a position sensor for collecting the position Hall signal output by the brushless DC motor; a commutation control logic circuit for generating a commutation control logic signal adapted to the ON‑PWM control mode based on a direction control signal, a PWM signal, a position Hall signal, and a signal after a non-logical operation of the position Hall signal and the direction control signal; a drive circuit for driving the commutation control logic signal to generate a drive signal; the control mode selected by the power main circuit is the ON‑PWM control mode, which is used to generate a brushless DC motor input control signal based on the drive signal, and use the input control signal to drive the brushless DC motor to work.

Description

Technical Field

[0001] The present invention relates to the technical field of brushless DC motor commutation, and in particular to a brushless DC motor control circuit and method based on ON-PWM control mode. Background Art

[0002] Brushless DC motors have the advantages of simple structure, small size, high power density, high efficiency, etc., and are widely used in various fields of national economy such as national defense, aerospace, aviation, automobiles, and home appliances. With the emergence of permanent magnet materials and the rapid development of electronic components, permanent magnet brushless DC motors are more widely used, and small size and high reliability brushless DC motor drive circuits have become one of the key technologies in the development of brushless DC motors.

[0003] At present, there are mainly two methods for brushless DC motor control circuits. The first method is a method that adopts a position sensor, a bridge drive circuit and a processor chip to jointly implement the method. The processor chip collects the signal of the position sensor, and outputs a control signal to control the bridge drive circuit to realize the phase change of the motor according to the phase change control algorithm. The advantage of this method is mature technology and simple control algorithm, but the disadvantage is that due to the need for processor chips and peripheral circuits, the circuit is complex, large in size, and high in cost, which is limited when used in low-cost applications; the second method is a method without position sensors, which uses processor chips, control algorithms and detection circuits to jointly realize the phase change of the motor. The advantage of this method is that the position sensor is omitted and the motor leads are reduced, but the disadvantage is that the detection circuit and control algorithm are relatively complex, and the processor chip and control algorithm need to be combined, resulting in high cost, reduced reliability, and large switching loss and motor loss.

[0004] In addition, the prior art lacks a brushless DC motor control circuit for the ON-PWM control method. Summary of the invention

[0005] In view of the above analysis, the embodiments of the present invention aim to provide a brushless DC motor control circuit and method based on ON-PWM control method, so as to solve the problems of poor reliability, large size, high cost, large switching loss and motor loss of the existing motor commutation control circuit.

[0006] On the one hand, the present invention discloses a brushless DC motor control circuit based on ON-PWM control mode, comprising:

[0007] Position sensor, used to collect the position Hall signal output by the brushless DC motor;

[0008] A commutation control logic circuit generates a commutation control logic signal adapted to an ON-PWM control mode based on a direction control signal, a PWM signal, the position Hall signal, and a signal obtained by performing a negation logic operation on the position Hall signal and the direction control signal;

[0009] A driving circuit, used for driving the commutation control logic signal to generate a driving signal;

[0010] The control mode selected by the power main circuit is the ON-PWM control mode, which is used to generate a brushless DC motor input control signal based on the drive signal, and use the input control signal to drive the brushless DC motor to work.

[0011] On the basis of the above scheme, the present invention also makes the following improvements:

[0012] Further, the brushless DC motor is controlled to rotate forward or reverse based on the direction control signal;

[0013] The rotation speed of the brushless DC motor is controlled based on the duty cycle of the PWM signal.

[0014] Further, the position Hall signal includes an A-phase position Hall signal HA, a B-phase position Hall signal HB and a C-phase position Hall signal HC. The corresponding relationship between HA, HB, HC and the direction control signal DIR and the commutation control logic signals S1-S6 is:

[0015] If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is at a high level, signals S2, S3, S4, and S5 are at a low level, and signal S6 is a PWM signal;

[0016] If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level;

[0017] If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal;

[0018] If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level;

[0019] If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal;

[0020] If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low level, and signal S6 is high level;

[0021] When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

[0022] Further, if the signal S1 is at a high level, the signals S2, S3, S4, and S5 are all at low levels, and the signal S6 is a PWM signal, then the input control signal UA of the A-phase brushless DC motor is DC+ / 2, the input control signal UB of the B-phase brushless DC motor is an alternating change between DC+ / 2 and 0, and the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; the alternating change between DC+ / 2 and 0 is: when the PWM signal is at a high level, it is DC+ / 2, and when the PWM signal is at a low level, it is 0;

[0023] If signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level, then UA is an alternating change between DC+ / 2 and 0, UC is 0, and UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0024] If signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal, then UB is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0025] If signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level, then UB is an alternating change between DC+ / 2 and 0, UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0026] If signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal, then UC is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0027] If signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low levels, and signal S6 is high level, then UC is an alternating change between DC+ / 2 and 0, UB is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2.

[0028] Furthermore, the commutation control circuit also includes an overcurrent protection circuit.

[0029] When the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level;

[0030] The overcurrent protection signal is input to the commutation control logic circuit.

[0031] Furthermore, when the overcurrent protection signal is at a low level, the commutation control logic signals S2, S4 and S6 are pulled low.

[0032] Furthermore, the commutation control logic circuit includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signals of DIR after the logical negation operation are DIR1; wherein:

[0033] The S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S6' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1;

[0034] The S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 8 and AND gate 10 respectively, and the output end of OR gate 3 outputs signal S3'; the two input ends of AND gate 11 receive signal S3' and signal S2' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3;

[0035] The S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 are connected to the output end of the AND gate 13 and the signal DIR respectively; the two input ends of the AND gate 15 receive signals HC1 and HA respectively, and the two input ends of the AND gate 16 are connected to the output end of the AND gate 15 and the signal DIR1 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 14 and the AND gate 16 respectively, and the output end of the OR gate 5 outputs a signal S5'; the two input ends of the AND gate 17 receive signals S4' and S5' respectively; the two input ends of the AND gate 18 receive signals S5' and the PWM signal respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 17 and the AND gate 18 respectively; the output end of the OR gate 6 outputs a signal S5;

[0036] The S2 control logic module includes AND gates 19-26 and OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 7 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 7 outputs signal S2'; the two input ends of AND gate 25 receive signals S1' and S2' respectively; the two input ends of AND gate 26 receive signals S2' and PWM signals respectively; the two input ends of OR gate 8 are connected to the output ends of AND gate 25 and AND gate 26 respectively; and the output end of OR gate 8 outputs signal S2;

[0037] The S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the output end of OR gate 9 outputs signal S4'; the two input ends of AND gate 33 receive signals S3' and S4' respectively; the two input ends of AND gate 34 receive signals S4' and PWM signals respectively; the two input ends of OR gate 10 are connected to the output ends of AND gate 33 and AND gate 34 respectively; the output end of OR gate 10 outputs signal S4;

[0038] The S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input ends of AND gate 35 receive signals HB and HC1 respectively, and the two input ends of AND gate 36 receive signals DIR1 and ST respectively; the two input ends of AND gate 37 are connected to the output ends of AND gate 35 and AND gate 36 respectively; the two input ends of AND gate 38 receive signals HB1 and HC respectively, and the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S5' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM signals respectively; the input ends of OR gate 12 are connected to the output ends of AND gate 41 and AND gate 42 respectively; the output end of OR gate 12 outputs signal S6;

[0039] If the brushless DC motor control circuit based on the ON-PWM control method includes an overcurrent protection circuit, the signal ST is an overcurrent protection signal; otherwise, the signal ST is 1.

[0040] Furthermore, the circuit also includes a signal shaping circuit for performing the negation logic operation on the position Hall signal and the direction control signal.

[0041] On the other hand, the present invention also discloses a brushless DC motor control method based on ON-PWM control mode, comprising the following steps:

[0042] Collect the position Hall signal output by the brushless DC motor;

[0043] Based on the direction control signal, the PWM signal, the position Hall signal, and the signal after the position Hall signal and the direction control signal are subjected to a negation logic operation, a commutation control logic signal adapted to the ON-PWM control mode is generated;

[0044] driving the commutation control logic signal to generate a driving signal;

[0045] Based on the driving signal, the power main circuit is driven to generate a brushless DC motor input control signal, and the brushless DC motor is driven to work by using the input control signal;

[0046] Among them, the control mode selected by the power main circuit is the ON-PWM control mode.

[0047] Furthermore, the brushless DC motor is controlled to rotate forward or reverse based on the direction control signal; and the speed of the brushless DC motor is controlled based on the duty cycle of the PWM signal.

[0048] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:

[0049] The brushless DC motor control circuit and method based on ON-PWM control mode provided by the present invention can realize the commutation control of the brushless DC motor by adopting a commutation control logic circuit, and only one PWM signal and one square control signal are used. At this time, the power main circuit control mode adopts ON-PWM mode, which is beneficial to reduce switching loss and motor loss. The circuit has the advantages of high reliability, small size, low cost, etc.

[0050] In addition, the overcurrent protection circuit is used to protect against single instantaneous overcurrent faults and can automatically recover. No special controller chip is required, which simplifies the control system and improves system reliability.

[0051] In the present invention, the above-mentioned technical solutions can also be combined with each other to achieve more preferred combination solutions. Other features and advantages of the present invention will be described in the subsequent description, and some advantages can become obvious from the description, or can be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] The drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like components throughout the drawings.

[0053] Figure 1 The brushless DC motor control circuit based on ON-PWM control method in Embodiment 1 of the present invention;

[0054] Figure 2 The signal shaping circuit in Embodiment 1 of the present invention;

[0055] Figure 3 The phase-change control logic circuit in Embodiment 1 of the present invention;

[0056] Figure 4 The driving circuit in Embodiment 1 of the present invention;

[0057] Figure 5 The main power circuit in Embodiment 1 of the present invention;

[0058] Figure 6 The brushless DC motor control circuit based on ON-PWM control mode with overcurrent protection in Embodiment 2 of the present invention;

[0059] Figure 7 The overcurrent protection circuit in Embodiment 2 of the present invention;

[0060] Figure 8This is a flow chart of the brushless DC motor control method based on ON-PWM control mode in Example 3 of the present invention. DETAILED DESCRIPTION

[0061] The preferred embodiments of the present invention are described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, but are not used to limit the scope of the present invention.

[0062] Example 1

[0063] A specific embodiment 1 of the present invention discloses a brushless DC motor control circuit based on ON-PWM control mode, and the structural diagram is shown in FIG. Figure 1 As shown, it includes: a position sensor for collecting the position Hall signal output by the brushless DC motor; a commutation control logic circuit (adapted to the ON-PWM control mode), based on the direction control signal, the PWM signal, the position Hall signal, and the signal after the position Hall signal and the direction control signal are subjected to a non-logical operation, to generate a commutation control logic signal adapted to the ON-PWM control mode; a drive circuit for driving the commutation control logic signal to generate a drive signal; the control mode selected by the power main circuit (based on the ON-PWM control mode) is the ON-PWM control mode, which is used to generate a brushless DC motor input control signal based on the drive signal, and use the input control signal to drive the brushless DC motor to work.

[0064] Compared with the prior art, the brushless DC motor control circuit based on ON-PWM control method provided in this embodiment is designed in conjunction with the PWM modulation method of the power main circuit. The commutation control of the brushless DC motor can be achieved through only one PWM signal and one direction control signal. It has the advantages of simple circuit structure, high reliability, and small size. It is also beneficial to reduce switching loss and motor loss.

[0065] It should be noted that the direction control signal in this embodiment is used to indicate whether the brushless DC motor rotates forward or reversely. In this embodiment, when the motor is controlled to rotate forward, the direction control signal DIR is set to a high level; when the motor is controlled to rotate reversely, the direction control signal DIR is set to a low level; in addition, the PWM signal in this embodiment is used to adjust the speed of the brushless DC motor. Optionally, the frequency of the PWM signal can be set to 5k~20kz, and the duty cycle d of the PWM signal ranges from 0 to 1. The motor speed regulation can be achieved by changing the duty cycle of the PWM signal: the larger the duty cycle, the higher the corresponding motor speed; the smaller the duty cycle, the smaller the corresponding motor speed; a duty cycle of 1 corresponds to the highest adjustable speed, and a duty cycle of 0 corresponds to the lowest adjustable speed (i.e., 0 speed).

[0066] Exemplarily, the circuit further comprises a signal shaping circuit, such as Figure 2 As shown, it is used to perform negation logic operations on the position Hall signal and the direction control signal respectively.

[0067] like Figure 1 As shown, the position Hall signals output by the brushless DC motor include the A-phase position Hall signal HA, the B-phase position Hall signal HB, and the C-phase position Hall signal HC; the corresponding signals of the position Hall signals HA, HB, HC and the direction control signal DIR after the signal shaping circuit performs a negation logic operation are represented as HA1, HB1, HC1, and DIR1 respectively; the commutation control logic circuit processes the signals HA, HB, HC, DIR, HA1, HB1, HC1, DIR1 and the PWM signal, and outputs the commutation logic signals S1-S6; among which, the signals S1, S3, S5 is the switching control logic signal for the power tubes VT1, VT3, and VT5 in the upper bridge arm of the power main circuit; signals S2, S4, and S6 are the switching control logic signals for the power tubes VT4, VT6, and VT2 in the lower bridge arm of the power main circuit; in the power main circuit, VT1 and VT4 are on the same bridge arm, and the connection point of VT1 and VT4 outputs signal UA; VT3 and VT6 are on the same bridge arm, and the connection point of VT3 and VT6 outputs signal UB; VT5 and VT2 are on the same bridge arm, and the connection point of VT5 and VT2 outputs signal UC. After being driven by the driving circuit, signals S1-S6 output driving signals G1-G6, wherein signal S1 drives the amplified output signal G1, signal S2 drives the amplified output signal G2, signal S3 drives the amplified output signal G3, signal S4 drives the amplified output signal G4, signal S5 drives the amplified output signal G5, and signal S6 drives the amplified output signal G6. The power main circuit adjusts the opening or closing of the power tubes VT1-VT6 according to the drive signals G1-G6, and outputs the brushless DC motor input control signals UA, UB, UC, and uses UA, UB, UC to control the rotation of the brushless DC motor. Specifically, the signals G1, G2, G3, G4, G5, and G6 are constantly on for the first 60° of their respective 120° conduction cycles, and perform PWM chopping control for the last 60°, and are constantly off within the remaining 240° range. Therefore, when the power main circuit control mode adopts the ON-PWM mode, it is beneficial to reduce switching losses and motor losses.

[0068] When the motor rotates one circle, the position Hall signals HA, HB, and HC will have six states, namely "101", "100", "110", "010", "011", and "001". When DIR is 1, the motor rotates forward, and when it is 0, the motor rotates reversely. Assuming that the duty cycle of the PWM signal is d (the range of duty cycle d is 0 to 1), then when the PWM modulation mode is ON-PWM mode, the corresponding relationship between the position Hall signals HA, HB, HC and the direction control signal DIR in the commutation control logic circuit and the commutation control logic signals S1-S6 is:

[0069] If HA, HB, HC, and DIR are "1011" (i.e., the states of HA, HB, HC, and DIR are 1, 0, 1, and 1, respectively) or "0100", signal S1 is at a high level, signals S2, S3, S4, and S5 are at a low level, and signal S6 is a PWM signal; after passing through the drive circuit, G1 is at a high level, G2, G3, G4, and G5 are all at a low level, and the waveform of G6 is a PWM signal with a duty cycle of d. When passing through the power main circuit, VT1 of the power main circuit is turned on due to the high level of G1, and VT2, VT3, VT4 and VT5 are both turned off, and VT6 is modulated by the G6 signal and is in an alternating on-off action (when G6 is 1, VT6 is turned on, and when G1 is 0, VT6 is turned off). At this time, the A-phase brushless DC motor input control signal UA of the power main circuit is DC+ / 2, and the B-phase brushless DC motor input control signal UB is an alternating change between DC+ / 2 and 0: when the PWM signal is at a high level, it is DC+ / 2, and when the PWM signal is at a low level, it is 0. The C-phase brushless DC motor input control signal UC is a linear decrease from DC+ / 2 to -DC+ / 2;

[0070] If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low levels, and signal S2 is a high level; after passing through the driving circuit, the waveform of G1 is a PWM signal with a duty cycle of d, G3, G4, G5, and G6 are all low levels, and G2 is a high level. When passing through the power main circuit, VT1 of the power main circuit is modulated by the G1 signal and is in an alternating on-off action (when G1 is 1, VT1 is on, and when G1 is 0, VT1 is off), VT3, VT4, VT5, and VT6 of the power main circuit are all off, and VT2 is turned on due to the high level of G2. At this time, UA of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT1 is on, UA is DC+ / 2, and when VT1 is off, UA is 0), UC is 0, and UB is a linear increase from -DC+ / 2 to DC+ / 2;

[0071] If HA, HB, HC, DIR are "1101" or "0010", signal S3 is high, signals S1, S4, S5, S6 are all low, and signal S2 is a PWM signal; after passing through the drive circuit, G3 is high, G1, G4, G5, G6 are all low, and the waveform of G2 is a PWM signal with a duty cycle of d. When passing through the power main circuit, VT2 of the power main circuit is modulated by the G2 signal and is in an alternating on-off action (when G2 is 1, VT2 is on, and when G2 is 0, VT2 is off), VT1, VT4, VT5, VT6 of the power main circuit are all off, and VT3 is turned on due to the high level of G3. At this time, UB of the power main circuit is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2;

[0072] If HA, HB, HC, DIR are "0101" or "1010", signal S3 is a PWM signal, signals S1, S2, S5, S6 are all low level, and signal S4 is high level; after passing through the driving circuit, the waveform of G3 is a PWM signal with a duty cycle of d, G1, G2, G5, G6 are all low level, G4 is high level, when passing through the power main circuit, VT3 of the power main circuit is modulated by the G3 signal and is in an alternating on and off action (when G3 is 1, VT3 is on, when G3 is 0, VT3 is off), VT1, VT2, VT5, VT6 of the power main circuit are all off, VT4 is turned on due to the high level of G4, at this time UB of the power main circuit is an alternating change between DC+ / 2 and 0 (when VT3 is on, UB is -DC+ / 2, when VT3 is off, UB is 0), UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2;

[0073] If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is high, signals S1, S2, S3, and S6 are all low, and signal S4 is a PWM signal; after passing through the commutation circuit, S5 is high, S1, S2, S3, and S6 are all low, and the waveform of S4 is a PWM signal with a duty cycle of d. After passing through the drive circuit, G5 is high, G1, G2, G3, and G6 are all low, and the waveform of G4 is a PWM signal with a duty cycle of d. When passing through the power main circuit, the power VT4 of the power main circuit is modulated by the G4 signal and is in an alternating on-off action (when G4 is 1, VT4 is on, when G4 is 0, VT4 is off), VT1, VT2, VT3, and VT6 of the power main circuit are all off, and VT5 is turned on due to the high level of G5. At this time, UC of the power main circuit is DC+ / 2, UA is an alternating change between DC+ / 2 and 0 (when VT4 is on, UA is 0, when VT4 is off, UA is DC+ / 2), and UB is a linear decrease from DC+ / 2 to -DC+ / 2;

[0074] If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low levels, and signal S6 is a high level; after passing through the driving circuit, the waveform of G5 is a PWM signal with a duty cycle of d, G1, G2, G3, and G4 are all low levels, and G6 is a high level. When passing through the power main circuit, VT5 of the power main circuit is modulated by the G5 signal and is in an alternating on-off action (when G5 is 1, VT5 is on, and when G5 is 0, VT5 is off), VT1, VT2, VT3, and VT4 of the power main circuit are all off, and VT6 is turned on due to the high level of G6. At this time, UC of the power main circuit is an alternating change between DC+ / 2 and 0, UB is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2.

[0075] Preferably, the commutation control logic circuit is as follows Figure 3As shown, it includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the negation logic operation are HA1, HB1, and HC1 respectively, and the signal of DIR after the negation logic operation is DIR1; wherein: S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are respectively connected to the output end of AND gate 1 and the signal DIR; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are respectively connected to the output end of AND gate 3 and the signal DIR1; the two input ends of OR gate 1 are respectively connected to the output ends of AND gate 2 and AND gate 4, and the two input ends of OR gate 1 are respectively connected to the output ends of AND gate 2 and AND gate 4. The output end of AND gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S6' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1; S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to AND gate 8 respectively The output end of AND gate 10 and the output end of OR gate 3 output signal S3'; the two input ends of AND gate 11 receive signal S3' and signal S2' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3; S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of AND gate 13 receive signals HC and HA1 respectively, and the two input ends of AND gate 14 are connected to the output end of AND gate 13 and signal DIR respectively; the two input ends of AND gate 15 receive signals HC1 and HA respectively, and the two input ends of AND gate 16 are connected to the output end of AND gate 15 and signal DIR1; the two input ends of OR gate 5 are respectively connected to the output ends of AND gate 14 and AND gate 16, and the output end of OR gate 5 outputs signal S5'; the two input ends of AND gate 17 receive signals S4' and S5' respectively; the two input ends of AND gate 18 receive signal S5' and PWM signal respectively; the two input ends of OR gate 6 are respectively connected to the output ends of AND gate 17 and AND gate 18; the output end of OR gate 6 outputs signal S5; S2 control logic module includes AND gates 19-26, OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signal DIR1 and signal ST respectively; the two input ends of AND gate 21 are respectively connected to the output ends of AND gate 19 and AND gate 20;The two input ends of the AND gate 22 receive the signals HC1 and HA respectively, and the two input ends of the AND gate 23 receive the signals DIR and ST respectively; the two input ends of the AND gate 24 are connected to the output ends of the AND gate 22 and the AND gate 23 respectively; the two input ends of the OR gate 7 are connected to the output ends of the AND gate 21 and the AND gate 24 respectively, and the output end of the OR gate 7 outputs the signal S2'; the two input ends of the AND gate 25 receive the signals S1' and S2' respectively; the two input ends of the AND gate 26 receive the signals S2' and the PWM signal respectively; the two input ends of the OR gate 8 are connected to the output ends of the AND gate 25 and the AND gate 26 respectively; the output end of the OR gate 8 outputs the signal S2 ; S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively. The output terminal outputs signal S4'; the two input terminals of AND gate 33 receive signal S3' and signal S4' respectively; the two input terminals of AND gate 34 receive signal S4' and PWM signal respectively; the two input terminals of OR gate 10 are connected to the output terminals of AND gate 33 and AND gate 34 respectively; the output terminal of OR gate 10 outputs signal S4; S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input terminals of AND gate 35 receive signals HB and HC1 respectively, and the two input terminals of AND gate 36 receive signals DIR1 and ST respectively; the two input terminals of AND gate 37 are connected to the output terminals of AND gate 35 and AND gate 36 respectively; and the two input terminals of AND gate 37 are connected to the output terminals of AND gate 35 and AND gate 36 respectively. The two input ends of AND gate 38 receive signals HB1 and HC respectively, the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S5' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM signal respectively; the input ends of OR gate 12 are connected to the output ends of AND gate 41 and AND gate 42 respectively; the output end of OR gate 12 outputs signal S6. At this time, signal ST takes 1. ;

[0076] Drive circuit such as Figure 4 As shown, it includes three IR2110 driver chips, each of which is used to drive the upper and lower power tubes of the same bridge arm in the power main circuit; after power-on, the SD pin of each IR2110 driver chip is connected to a low level. Figure 5shown.

[0077] Example 2

[0078] A specific embodiment 2 of the present invention improves the brushless DC motor control circuit based on the ON-PWM control method in embodiment 1, adds an overcurrent protection circuit and a fault counting and latching circuit, and forms a Figure 6 The brushless DC motor control circuit with overcurrent protection based on ON-PWM control mode is shown to realize overcurrent protection in the commutation control process. Among them, when the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is low level; otherwise, the output overcurrent protection signal is high level; the overcurrent protection signal is input to the commutation control logic circuit, and when the overcurrent protection signal is low level, the commutation control logic signals S2, S4 and S6 are pulled down. The overcurrent protection circuit is used to realize protection against single instantaneous overcurrent faults and can automatically recover. No special controller chip is required, which simplifies the control system and improves system reliability.

[0079] like Figure 6 As shown, the overcurrent protection circuit receives the overcurrent signal OV output by the power main circuit. After the above judgment, the overcurrent protection circuit outputs the overcurrent protection signal ST, and inputs the signal ST to the phase-change control logic circuit. In the above-mentioned brushless DC motor control circuit with overcurrent protection based on ON-PWM control mode, if an instantaneous overcurrent occurs during the operation of the motor, the overcurrent protection circuit output signal ST will be low level, ST passes through the phase-change control logic circuit, and the drive signals S4, S6, and S2 are pulled down at the same time, thereby pulling down the lower bridge arm drive signals G4, G6, and G2 of the power main circuit, blocking the lower bridge arm to ensure the safety of the power main circuit. After the lower bridge arm is blocked, the current of the power main circuit will decrease, and the overcurrent protection circuit output signal ST will gradually become high level. ST passes through the phase-change control logic circuit, and the drive signals S4, S6, and S2 are released from the forced low state at the same time, thereby restoring the lower bridge arm drive signals G4, G6, and G2 of the power main circuit to normal. At this point, the power main circuit completes one overcurrent protection and recovery. The overcurrent protection circuit is as shown in FIG. Figure 7 shown.

[0080] Example 3

[0081] Embodiment 3 of the present invention discloses a brushless DC motor control method based on ON-PWM control mode, the flow chart is as follows: Figure 8 As shown, the following steps are included:

[0082] Step S1: collecting the position Hall signal output by the brushless DC motor;

[0083] Step S2: generating a commutation control logic signal adapted to the ON-PWM control mode based on the direction control signal, the PWM signal, the position Hall signal, and a signal obtained by performing a negation logic operation on the position Hall signal and the direction control signal;

[0084] Step S3: driving the commutation control logic signal to generate a driving signal;

[0085] Step S4: driving the power main circuit based on the driving signal to generate a brushless DC motor input control signal, and using the input control signal to drive the brushless DC motor to work;

[0086] Among them, the control mode selected by the said power main circuit is the said ON-PWM control mode.

[0087] The specific implementation process of the embodiment of the present invention can refer to the above circuit embodiment. For example, the commutation control logic signal is generated based on the commutation control logic circuit, the drive signal is generated based on the drive circuit, and the brushless DC motor input control signal is generated based on the power main circuit. This embodiment will not be repeated here. Since the principle of this embodiment is the same as that of the above circuit embodiment, the method also has the corresponding technical effects of the above circuit embodiment.

[0088] Those skilled in the art will appreciate that all or part of the processes of the above-mentioned embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, wherein the computer-readable storage medium is a disk, an optical disk, a read-only storage memory, or a random access memory, etc.

[0089] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by any technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A brushless DC motor control circuit based on ON-PWM control mode, characterized in that: include: Position sensor, used to collect the position Hall signal output by the brushless DC motor; A commutation control logic circuit generates a commutation control logic signal adapted to an ON-PWM control mode based on a direction control signal, a PWM signal, the position Hall signal, and a signal obtained by performing a negation logic operation on the position Hall signal and the direction control signal; A driving circuit, used for driving the commutation control logic signal to generate a driving signal; The control mode selected by the power main circuit is the ON-PWM control mode, which is used to generate a brushless DC motor input control signal based on the drive signal, and use the input control signal to drive the brushless DC motor to work; The commutation control logic circuit includes: S1-S6 control logic modules, each of which is composed of an AND gate and an OR gate, and the signals of HA, HB, and HC after the logical negation operation are HA1, HB1, and HC1 respectively, and the signals of DIR after the logical negation operation are DIR1; wherein: The S1 control logic module includes AND gates 1-6 and OR gates 1-2; the two input ends of AND gate 1 receive signals HA and HB1 respectively, and the two input ends of AND gate 2 are connected to the output end of AND gate 1 and signal DIR respectively; the two input ends of AND gate 3 receive signals HA1 and HB respectively, and the two input ends of AND gate 4 are connected to the output end of AND gate 3 and signal DIR1 respectively; the two input ends of OR gate 1 are connected to the output ends of AND gate 2 and AND gate 4 respectively, and the output end of OR gate 1 outputs signal S1'; the two input ends of AND gate 5 receive signal S1' and signal S6' respectively; the two input ends of AND gate 6 receive signal S1' and PWM signal respectively; the two input ends of OR gate 2 are connected to the output ends of AND gate 5 and AND gate 6 respectively; the output end of OR gate 2 outputs signal S1; The S3 control logic module includes AND gates 7-12 and OR gates 3-4; the two input ends of AND gate 7 receive signals HB and HC1 respectively, and the two input ends of AND gate 8 are connected to the output end of AND gate 7 and signal DIR respectively; the two input ends of AND gate 9 receive signals HB1 and HC respectively, and the two input ends of AND gate 10 are connected to the output end of AND gate 9 and signal DIR1 respectively; the two input ends of OR gate 3 are connected to the output ends of AND gate 8 and AND gate 10 respectively, and the output end of OR gate 3 outputs signal S3'; the two input ends of AND gate 11 receive signal S3' and signal S2' respectively; the two input ends of AND gate 12 receive signal S3' and PWM signal respectively; the two input ends of OR gate 4 are connected to the output ends of AND gate 11 and AND gate 12 respectively; the output end of OR gate 4 outputs signal S3; The S5 control logic module includes AND gates 13-18 and OR gates 5-6; the two input ends of the AND gate 13 receive signals HC and HA1 respectively, and the two input ends of the AND gate 14 are connected to the output end of the AND gate 13 and the signal DIR respectively; the two input ends of the AND gate 15 receive signals HC1 and HA respectively, and the two input ends of the AND gate 16 are connected to the output end of the AND gate 15 and the signal DIR1 respectively; the two input ends of the OR gate 5 are connected to the output ends of the AND gate 14 and the AND gate 16 respectively, and the output end of the OR gate 5 outputs a signal S5'; the two input ends of the AND gate 17 receive signals S4' and S5' respectively; the two input ends of the AND gate 18 receive signals S5' and the PWM signal respectively; the two input ends of the OR gate 6 are connected to the output ends of the AND gate 17 and the AND gate 18 respectively; the output end of the OR gate 6 outputs a signal S5; The S2 control logic module includes AND gates 19-26 and OR gates 7-8; the two input ends of AND gate 19 receive signals HC and HA1 respectively, and the two input ends of AND gate 20 receive signals DIR1 and ST respectively; the two input ends of AND gate 21 are connected to the output ends of AND gate 19 and AND gate 20 respectively; the two input ends of AND gate 22 receive signals HC1 and HA respectively, and the two input ends of AND gate 23 receive signals DIR and ST respectively; the two input ends of AND gate 24 are connected to the output ends of AND gate 22 and AND gate 23 respectively; the two input ends of OR gate 7 are connected to the output ends of AND gate 21 and AND gate 24 respectively, and the output end of OR gate 7 outputs signal S2'; the two input ends of AND gate 25 receive signals S1' and S2' respectively; the two input ends of AND gate 26 receive signals S2' and PWM signals respectively; the two input ends of OR gate 8 are connected to the output ends of AND gate 25 and AND gate 26 respectively; and the output end of OR gate 8 outputs signal S2; The S4 control logic module includes AND gates 27-34 and OR gates 9-10; the two input ends of AND gate 27 receive signals HA and HB1 respectively, and the two input ends of AND gate 28 receive signals DIR1 and ST respectively; the two input ends of AND gate 29 are connected to the output ends of AND gate 27 and AND gate 28 respectively; the two input ends of AND gate 30 receive signals HA1 and HB respectively, and the two input ends of AND gate 31 receive signals DIR and ST respectively; the two input ends of AND gate 32 are connected to the output ends of AND gate 30 and AND gate 31 respectively; the two input ends of OR gate 9 are connected to the output ends of AND gate 29 and AND gate 32 respectively, and the output end of OR gate 9 outputs signal S4'; the two input ends of AND gate 33 receive signals S3' and S4' respectively; the two input ends of AND gate 34 receive signals S4' and PWM signals respectively; the two input ends of OR gate 10 are connected to the output ends of AND gate 33 and AND gate 34 respectively; the output end of OR gate 10 outputs signal S4; The S6 control logic module includes AND gates 35-42 and OR gates 11-12; the two input ends of AND gate 35 receive signals HB and HC1 respectively, and the two input ends of AND gate 36 receive signals DIR1 and ST respectively; the two input ends of AND gate 37 are connected to the output ends of AND gate 35 and AND gate 36 respectively; the two input ends of AND gate 38 receive signals HB1 and HC respectively, and the two input ends of AND gate 39 receive signals DIR and ST respectively; the two input ends of AND gate 40 are connected to the output ends of AND gate 38 and AND gate 39 respectively; the two input ends of OR gate 11 are connected to the output ends of AND gate 37 and AND gate 40 respectively, and the output end of OR gate 11 outputs signal S6'; the two input ends of AND gate 41 receive signals S5' and S6' respectively; the two input ends of AND gate 42 receive signals S6' and PWM signals respectively; the input ends of OR gate 12 are connected to the output ends of AND gate 41 and AND gate 42 respectively; the output end of OR gate 12 outputs signal S6; If the brushless DC motor control circuit based on the ON-PWM control method includes an overcurrent protection circuit, the signal ST is an overcurrent protection signal; otherwise, the signal ST is 1.

2. The brushless DC motor control circuit based on ON-PWM control method according to claim 1, characterized in that: Controlling the brushless DC motor to rotate forward or reverse based on the direction control signal; The rotation speed of the brushless DC motor is controlled based on the duty cycle of the PWM signal.

3. The brushless DC motor control circuit based on ON-PWM control mode according to claim 1 or 2, characterized in that: The position Hall signal includes the A-phase position Hall signal HA, the B-phase position Hall signal HB and the C-phase position Hall signal HC. The corresponding relationship between HA, HB, HC and the direction control signal DIR and the commutation control logic signals S1-S6 is: If HA, HB, HC, and DIR are "1011" or "0100", signal S1 is high level, signals S2, S3, S4, and S5 are low level, and signal S6 is a PWM signal; If HA, HB, HC, and DIR are "1001" or "0110", signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level; If HA, HB, HC, and DIR are "1101" or "0010", signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal; If HA, HB, HC, and DIR are "0101" or "1010", signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level; If HA, HB, HC, and DIR are "0111" or "1000", signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal; If HA, HB, HC, and DIR are "0011" or "1100", signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low level, and signal S6 is high level; When DIR is 1, the motor rotates forward, and when DIR is 0, the motor rotates reversely.

4. The brushless DC motor control circuit based on ON-PWM control method according to claim 3 is characterized in that: If the signal S1 is at a high level, the signals S2, S3, S4, and S5 are all at low levels, and the signal S6 is a PWM signal, then the input control signal UA of the A-phase brushless DC motor is DC+ / 2, the input control signal UB of the B-phase brushless DC motor is an alternating change between DC+ / 2 and 0, and the input control signal UC of the C-phase brushless DC motor is a linear decrease from DC+ / 2 to -DC+ / 2; the alternating change between DC+ / 2 and 0 is: when the PWM signal is at a high level, it is DC+ / 2, and when the PWM signal is at a low level, it is 0; If signal S1 is a PWM signal, signals S3, S4, S5, and S6 are all low level, and signal S2 is high level, then UA is an alternating change between DC+ / 2 and 0, UC is 0, and UB is a linear increase from -DC+ / 2 to DC+ / 2; If signal S3 is at a high level, signals S1, S4, S5, and S6 are all at low levels, and signal S2 is a PWM signal, then UB is DC+ / 2, UC is an alternating change between DC+ / 2 and 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2; If signal S3 is a PWM signal, signals S1, S2, S5, and S6 are all low level, and signal S4 is high level, then UB is an alternating change between DC+ / 2 and 0, UA is 0, and UC is a linear increase from -DC+ / 2 to DC+ / 2; If signal S5 is at a high level, signals S1, S2, S3, and S6 are all at low levels, and signal S4 is a PWM signal, then UC is DC+ / 2, UA is an alternating change between DC+ / 2 and 0, and UB is a linear decrease from DC+ / 2 to -DC+ / 2; If signal S5 is a PWM signal, signals S1, S2, S3, and S4 are all low levels, and signal S6 is high level, then UC is an alternating change between DC+ / 2 and 0, UB is 0, and UA is a linear decrease from DC+ / 2 to -DC+ / 2.

5. The brushless DC motor control circuit based on ON-PWM control method according to claim 4, characterized in that: The commutation control logic circuit also includes an overcurrent protection circuit, When the overcurrent protection circuit receives the overcurrent signal output by the power main circuit, the overcurrent protection signal output by the overcurrent protection circuit is a low level; otherwise, the output overcurrent protection signal is a high level; The overcurrent protection signal is input to the commutation control logic circuit.

6. The brushless DC motor control circuit based on ON-PWM control method according to claim 5, characterized in that: When the overcurrent protection signal is at a low level, the switching control logic signals S2, S4 and S6 are pulled low.

7. The brushless DC motor control circuit based on ON-PWM control method according to claim 1, characterized in that: The circuit further comprises a signal shaping circuit for performing the negation logic operation on the position Hall signal and the direction control signal.

8. A brushless DC motor control method based on ON-PWM control mode, characterized in that: The control method is implemented based on the brushless DC motor control circuit based on ON-PWM control mode according to any one of claims 1 to 7, and the control method comprises the following steps: Collect the position Hall signal output by the brushless DC motor; Based on the direction control signal, the PWM signal, the position Hall signal, and the signal after the position Hall signal and the direction control signal are subjected to a negation logic operation, a commutation control logic signal adapted to the ON-PWM control mode is generated; driving the commutation control logic signal to generate a driving signal; Based on the driving signal, the power main circuit is driven to generate a brushless DC motor input control signal, and the brushless DC motor is driven to work by using the input control signal; Among them, the control mode selected by the power main circuit is the ON-PWM control mode.

9. The brushless DC motor control method based on ON-PWM control mode according to claim 8, characterized in that: The brushless DC motor is controlled to rotate forward or reverse based on the direction control signal; and the speed of the brushless DC motor is controlled based on the duty cycle of the PWM signal.

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