Semiconductor structure and preparation method thereof, and memory

Abstract

The disclosed embodiments provide a semiconductor structure and a method for preparing the same, and a memory, and relate to the field of semiconductor technology, and are used to solve the technical problem that the preparation of the semiconductor structure is difficult. The method for preparing the semiconductor structure includes providing a substrate; forming a plurality of stacked structures spaced along a first direction on the substrate, and each stacked structure includes a plurality of first sacrificial layers and active layers alternately stacked. The disclosed embodiments remove part of the first sacrificial layer to form a first groove and a second groove, and expose part of the active layer through the first groove and the second groove. After that, the exposed active layer can be doped by an ion doping process to form a first doping region and a second doping region. In this way, while reducing the difficulty of preparing the semiconductor structure, the yield of the semiconductor structure is also improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and a memory. Background Art

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed. It is widely used in data storage devices or apparatuses. Dynamic random access memory is composed of multiple repeated storage cells, each of which usually includes a capacitor and a transistor. The capacitor stores data information, and the transistor controls the reading of data information in the capacitor.

[0003] In order to increase the storage capacity of semiconductor structures, semiconductor structures have developed from two-dimensional structures to three-dimensional structures. However, when forming three-dimensional semiconductor structures, it is difficult to dope the active region of the semiconductor structure, which increases the difficulty of preparing the semiconductor structure and reduces the yield of the semiconductor structure. Summary of the invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a memory, which are used to reduce the difficulty of manufacturing an active layer.

[0005] A first aspect of an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0006] providing a substrate;

[0007] Forming a plurality of columns of stacked structures spaced apart along a first direction on the substrate, each column of the stacked structures comprising a plurality of first sacrificial layers and active layers alternately stacked;

[0008] Removing a portion of the first sacrificial layer to form a first groove and a second groove spaced apart along a second direction, wherein a portion of the surface of each of the active layers is exposed in the first groove and the second groove; wherein the second direction intersects with the first direction, and the first direction and the second direction are both parallel to the surface of the substrate;

[0009] The exposed active layers are ion-doped to form a first doping region and a second doping region that are spaced apart in each of the active layers, and the active layer between the first doping region and the second doping region constitutes a channel region.

[0010] Compared with the prior art, the method for preparing a semiconductor structure provided by the embodiment of the present disclosure has the following advantages:

[0011] A first groove and a second groove are formed by removing a portion of the first sacrificial layer, and a portion of the active layer is exposed through the first groove and the second groove. Thereafter, the exposed active layer can be doped through an ion doping process to form a first doping region and a second doping region. In this way, the difficulty of preparing the semiconductor structure is reduced and the yield of the semiconductor structure is improved.

[0012] In some embodiments, the step of removing part of the first sacrificial layer includes:

[0013] forming a second sacrificial layer, wherein the second sacrificial layer fills up the area between any adjacent stacked structures and covers the top surface of the stacked structure;

[0014] A portion of the second sacrificial layer is removed, and a plurality of etching holes are formed in a direction perpendicular to the substrate, each of the etching holes is located between adjacent stacked structures and exposes a side surface of the stacked structure, and a portion of the first sacrificial layer is removed along the etching holes.

[0015] In some embodiments, the etched holes include a first etched hole and a second etched hole, the first etched hole corresponds to the first doped region, and the second etched hole corresponds to the second doped region.

[0016] In some embodiments, the step of forming a plurality of stacked structures spaced apart along a first direction on the substrate comprises:

[0017] forming a first initial sacrificial layer and an initial active layer stacked and alternately arranged on the substrate;

[0018] forming a mask layer on the initial active layer, and patterning the mask layer to form a plurality of openings spaced apart along a first direction in the mask layer;

[0019] The first initial sacrificial layer and the initial active layer exposed in the opening are removed, and the retained first initial sacrificial layer and the initial active layer form a multi-column stacking structure, and a third groove extending along the second direction is formed between any two adjacent columns of the stacking structure.

[0020] In some embodiments, a bottom of the third trench is located in the substrate.

[0021] In some embodiments, after forming the first doping region and the second doping region, the preparation method further includes:

[0022] forming a third etched hole in the second sacrificial layer between any two adjacent columns of stacked structures, wherein the third etched hole corresponds to the channel region, is located between the first etched hole and the second etched hole, and does not expose the side surface of the stacked structure;

[0023] A first supporting structure is formed in the third etched hole, and a second supporting structure is formed in the first trench and the second trench.

[0024] In some embodiments, after forming the first supporting structure and the second supporting structure, the preparation method further includes:

[0025] removing the remaining second sacrificial layer and the first sacrificial layer to form a filling area;

[0026] forming a dielectric layer in the filling region, and removing a portion of the dielectric layer to expose the channel region;

[0027] A gate oxide layer and a conductive layer are sequentially formed on the surface of the channel region of the active layer.

[0028] In some embodiments, the step of removing the remaining second sacrificial layer and the first sacrificial layer comprises:

[0029] The second sacrificial layer between any adjacent stacked structures is wet-etched, and the first sacrificial layer in each column of the stacked structures is wet-etched to form the filling area.

[0030] In some embodiments, after forming the conductive layer, the preparation method further comprises:

[0031] An insulating layer is formed, where the insulating layer covers the dielectric layer and is connected to the first supporting structure and the second supporting structure.

[0032] In some embodiments, the insulating layer, the first supporting structure, and the second supporting structure are made of the same material.

[0033] In some embodiments, the first doping region, the second doping region, and the channel region have the same doping ion type, and a concentration of doping ions in the channel region is less than a concentration of doping ions in the first doping region and the second doping region.

[0034] In some embodiments, the step of forming a stacked and alternately arranged first initial sacrificial layer and an initial doping layer on the substrate includes:

[0035] A first initial sacrificial layer and an initial doping layer are alternately stacked and formed on the substrate by an epitaxial growth process, wherein the first initial sacrificial layer comprises silicon germanium, silicon phosphide or silicon nitride.

[0036] A second aspect of an embodiment of the present disclosure provides a semiconductor structure, which is manufactured by the method for manufacturing the semiconductor structure provided by the first aspect.

[0037] A third aspect of an embodiment of the present disclosure provides a memory, comprising the semiconductor structure provided in the second aspect, and further comprising a storage structure and a bit line structure, wherein the storage structure is electrically connected to one of the first doping region or the second doping region, and the bit line structure is electrically connected to the other of the first doping region or the second doping region.

[0038] In some embodiments, the bit line structure includes a plurality of bit lines arranged in parallel and spaced apart, and the plurality of bit lines are arranged in a stepped manner in a direction perpendicular to the substrate. In addition to the technical problems solved by the embodiments of the present disclosure, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the semiconductor structure and its preparation method, and other technical problems that can be solved by the memory provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0041] Figure 2 A schematic diagram of a structure for forming a first initial sacrificial layer and an initial active layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 3 For along Figure 2 Sectional view in the AA direction;

[0043] Figure 4 A schematic diagram of a structure for forming a mask layer in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0044] Figure 5 For along Figure 4 Sectional view in the AA direction;

[0045] Figure 6 A schematic diagram of a structure in which a stacked structure is formed in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0046] Figure 7 For along Figure 6 Sectional view in the AA direction;

[0047] Figure 8 A cross-sectional view in the AA direction after forming a second sacrificial layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0048] Fig. 9 A cross-sectional view in the BB direction after forming a second sacrificial layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0049] Fig.10 A schematic diagram of a structure for forming a second photoresist layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0050] Fig.11 A schematic diagram of a structure for forming an etching hole in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0051] Fig.12 A cross-sectional view in the AA direction after an etching hole is formed in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0052] Fig.13 A cross-sectional view in the BB direction after an etching hole is formed in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0053] Fig.14 A schematic diagram of a structure for forming a first doping region and a second doping region in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0054] Fig.15 A schematic diagram of a structure for forming a third etched hole in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0055] Fig.16 A cross-sectional view of a support structure formed in the AA direction in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0056] Fig.17 A cross-sectional view of a support structure formed in the BB direction in the method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0057] Fig.18 A cross-sectional view in the AA direction after removing the remaining second sacrificial layer in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0058] Fig.19 A cross-sectional view in the BB direction after removing the remaining second sacrificial layer in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0059] Fig. 20A cross-sectional view in the AA direction after removing the remaining first sacrificial layer in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0060] Fig.21 A cross-sectional view in the BB direction after removing the remaining first sacrificial layer in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0061] Fig. 22 A cross-sectional view in the AA direction after a dielectric layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0062] Fig.23 A cross-sectional view in the BB direction after a dielectric layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0063] Fig.24 A cross-sectional view in the AA direction after a portion of the dielectric layer is removed in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0064] Fig.25 A cross-sectional view in the BB direction after a portion of the dielectric layer is removed in the method for preparing the semiconductor structure provided by the embodiment of the present disclosure;

[0065] Fig.26 A cross-sectional view in the AA direction after a gate oxide layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0066] Fig. 27 A cross-sectional view in the BB direction after a gate oxide layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0067] Fig.28 A cross-sectional view in the AA direction after a conductive layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0068] Fig.29 A cross-sectional view in the BB direction after a conductive layer is formed in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0069] Fig.30 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 1 ;

[0070] Fig.31 Schematic diagram of a memory provided in an embodiment of the present disclosure Figure 2 .

[0071] Reference numerals:

[0072] 10: substrate; 11: first region; 12: second region; 13: third region; 20: stacked structure; 21: first sacrificial layer; 211: first trench; 212: second trench; 22: active layer; 221: first doped region; 222: second doped region; 223: channel region; 23: first initial sacrificial layer; 24: initial active layer; 25: third trench; 30: mask layer; 31: first opening; 40: second sacrificial layer; 50: etched hole; 51: first etched Hole; 52: second etching hole; 60: second photoresist layer; 70: third etching hole; 80: first supporting structure; 90: second supporting structure; 100: filling area; 100a: first filling area; 100b: second filling area; 110: dielectric layer; 111: fourth trench; 120: gate oxide layer; 130: conductive layer; 140: fifth trench; 150: insulating layer; 160: storage structure; 170: bit line structure; 180: isolation layer; 190: word line structure. DETAILED DESCRIPTION

[0073] As described in the background art, in the related art, when preparing a semiconductor structure with a three-dimensional structure, it is difficult to perform ion doping on the active layer to form a source-drain region because multiple active layers overlap in the vertical direction, which reduces the yield of the semiconductor structure. Based on this, in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure, a portion of the first sacrificial layer is removed to form a first groove and a second groove, and a portion of the active layer is exposed through the first groove and the second groove. After that, the exposed active layer can be doped by an ion doping process to form a first doping region and a second doping region. In this way, while reducing the difficulty of preparing the semiconductor structure, the yield of the semiconductor structure is also improved.

[0074] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0075] The present embodiment does not limit the semiconductor structure. The semiconductor structure will be described below by taking a dynamic random access memory (DRAM) as an example, but the present embodiment is not limited thereto. The semiconductor structure in the present embodiment may also be other structures.

[0076] Please refer to Figure 1 The method for preparing a semiconductor structure provided by the embodiment of the present disclosure comprises the following steps:

[0077] Step S100: providing a substrate.

[0078] refer to Figure 2 and Figure 3 The substrate 10 provides support for supporting the film layer thereon. The substrate 10 may be a semiconductor substrate. Exemplarily, the substrate 10 may be a silicon substrate, a germanium substrate, a silicon carbide (SiC) substrate, a silicon germanium (SiGe) substrate, a germanium on insulator (GOI) substrate, or a silicon on insulator (SOI) substrate.

[0079] Step S200: forming a plurality of stacked structures spaced apart along a first direction on a substrate, each stacked structure comprising a plurality of first sacrificial layers and active layers alternately stacked.

[0080] Exemplarily, stacked and alternately arranged first initial sacrificial layers 23 and initial active layers 24 are formed on the substrate 10, that is, multiple layers of initial active layers 24 and multiple layers of first initial sacrificial layers 23 are formed on the substrate 10, the multiple layers of initial active layers 24 and the multiple layers of first initial sacrificial layers 23 are sequentially stacked and alternately arranged in a direction perpendicular to the substrate 10, and the first initial sacrificial layer 23 is arranged on the substrate 10. The number of initial active layers 24 and first initial sacrificial layers 23 can be set according to actual needs.

[0081] In some possible implementations, the initial active layer 24 and the first initial sacrificial layer 23 may be formed by a deposition process, wherein the deposition process may include chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0082] In some other possible implementations, the first initial sacrificial layer 23 is formed by an epitaxial growth process (Epitaxy, abbreviated as EPI). In this way, the problem of lattice mismatch between the first initial sacrificial layer 23 and the initial active layer 24 and the substrate 10 can be avoided, the stress generated between the first initial sacrificial layer 23 and the substrate 10, and between the first initial sacrificial layer 23 and the initial active layer 24 interface can be reduced, and the stability of the subsequently formed semiconductor structure can be improved.

[0083] The material of the first initial sacrificial layer 23 includes silicon germanium or silicon phosphide, so that the first initial sacrificial layer 23 and the initial active layer 24 can have a larger etching selectivity, so that the first sacrificial layer can be selectively removed in the subsequent process, the etching of the active layer can be reduced, and the yield of the semiconductor structure can be improved.

[0084] In this embodiment, a silicon layer of a certain thickness may be formed on the first initial sacrificial layer by a deposition process, and then the silicon layer may be ion doped to form the initial active layer 24. In one example, N-type ions (group V element ions such as phosphorus P or arsenic As) may be implanted into the silicon layer to form the N-type initial active layer 24. In another example, P-type ions (group III element ions such as boron B or gallium Ga) may be implanted into the silicon layer to form the P-type initial active layer 24.

[0085] Please refer to Figure 4 and Figure 5 After the first initial sacrificial layer 23 and the initial active layer 24 are formed, a mask layer 30 is formed on the initial active layer, and the mask layer 30 is patterned to form a plurality of openings 31 spaced apart along the first direction Y in the mask layer 30, wherein each opening 31 extends along the second direction. The second direction is Figure 4 The X direction in .

[0086] In a feasible implementation, a first photoresist layer (not shown in the figure) can be formed on the mask layer 30. For example, the first photoresist layer can be formed on the mask layer 30 by a coating process, and then a first mask pattern is formed in the first photoresist layer by exposure, development or etching. The first mask pattern includes a plurality of first protrusions and a first opening area between adjacent first protrusions. The plurality of first protrusions are arranged at intervals along a first direction, and each first protrusion extends along a second direction, and the second direction is perpendicular to the first direction. The first direction is Figure 4 in the Y direction.

[0087] Afterwards, the mask layer 30 exposed in the opening area is removed by dry etching or wet etching to form a plurality of openings 31 spaced apart in the first direction in the mask layer 30 .

[0088] Afterwards, please refer to Figure 6 and Figure 7 , continue to remove the first initial sacrificial layer 23 and the initial active layer 24 exposed in the opening 31 through dry etching or wet etching, and the retained first initial sacrificial layer 23 and the initial active layer 24 constitute a multi-column stacking structure 20, and a third groove 25 extending along the second direction is formed between any two adjacent columns of the stacking structure 20.

[0089] Each column of stacked structures 20 includes a plurality of first sacrificial layers 21 and active layers 22 that are alternately stacked, and the first sacrificial layers 21 are disposed on the substrate 10 .

[0090] It should be noted that, in this example, a portion of the thickness of the substrate 10 may be further removed so that the bottom of the third groove 25 is located within the substrate 10 . This can facilitate subsequent removal of the first sacrificial layer 21 and ensure the integrity of the formed active layer 22 .

[0091] The first direction is Figure 6 The Y direction in the second direction is Figure 6 In the X direction, it can be ensured that the extension direction of the active layer is parallel to the substrate, thereby forming a three-dimensional stacked storage unit. Compared with the two-dimensional storage unit in the related art, more storage units can be arranged in an effective area, thereby improving the storage capacity of the semiconductor structure.

[0092] It should be noted that, in the present embodiment, the mask layer 30 may be a single film layer or a laminated structure. When the mask layer 30 is a laminated structure, the mask layer 30 may include a first mask layer and a second mask layer, wherein the first mask layer is disposed on the initial active layer 24, and the second mask layer is disposed on the first mask layer, so that the mask pattern may be first transferred from the first photoresist layer to the second mask layer, and then the second mask layer having the mask pattern is used as a mask to etch the first mask layer to transfer the mask pattern to the first mask layer, and finally, the first mask layer having the mask pattern is used as a mask to etch the multi-layer first initial sacrificial layer 23 and the initial active layer 24. In this way, the accuracy of the mask pattern transfer process may be improved, the preparation accuracy of the semiconductor structure may be improved, and the yield of the semiconductor structure may be improved.

[0093] The material of the first mask layer may include silicon oxide, but is not limited thereto. The material of the second mask layer may include silicon nitride, but is not limited thereto.

[0094] Step S300: removing part of the first sacrificial layer to form first and second grooves spaced apart along a second direction, wherein a portion of the surface of each active layer is exposed in the first and second grooves; wherein the second direction intersects with the first direction, and both the first and second directions are parallel to the surface of the substrate.

[0095] For example, please refer to Figure 8 and Fig. 9 , forming a second sacrificial layer 40 , the second sacrificial layer 40 fills the area between any adjacent stacked structures 20 and covers the top surface of the stacked structure 20 .

[0096] The second sacrificial layer 40 is deposited in the third trench by physical vapor deposition or chemical vapor deposition, and extends outside the third trench 25 and covers the top surface of the stacked structure 20. The second sacrificial layer 40 is made of silicon oxide, but is not limited thereto.

[0097] It should be noted that after the second sacrificial layer 40 is formed, the second sacrificial layer 40 can be planarized using a chemical mechanical polishing (CMP) process to ensure that the top surface of the second sacrificial layer 40 is a flat top surface. This makes it easier to subsequently prepare other film layers on the second sacrificial layer 40, thereby improving the preparation accuracy of the semiconductor structure.

[0098] Afterwards, part of the second sacrificial layer 40 is removed, and a plurality of etching holes 50 are formed in a direction perpendicular to the substrate 10 , each etching hole 50 is located between adjacent stacked structures 20 and exposes the side of the stacked structure 20 , and part of the first sacrificial layer 20 is removed along the etching holes 50 .

[0099] For example, please refer to Fig.10 A second photoresist layer 60 can be formed on the second sacrificial layer 40 by a coating process, and then a second mask pattern is formed in the second photoresist layer 60 by exposure, development or etching. The second mask pattern includes a plurality of second protrusions and a second opening area between adjacent second protrusions, the plurality of second protrusions are arranged at intervals along the second direction X, and each second protrusion extends along the first direction Y.

[0100] Please refer to Fig.11 , using the second photoresist layer 60 as a mask, remove the second sacrificial layer 40 exposed in the second opening area to form a plurality of etched holes 50 in the second sacrificial layer 40, wherein the depth direction of the etched holes 50 is perpendicular to the substrate 10, and the etched holes 50 expose the top surface of the substrate 10.

[0101] In the first direction Y, the sidewalls of each etched hole 50 are opposite surfaces of the adjacent columns of stacked structures 20. Fig.11 Taking the orientation shown as an example, each etching hole 50 exposes the front surface and the rear surface of one of the stacked structures 20. In this way, each etching hole can expose a portion of the first sacrificial layer, so that a portion of the first sacrificial layer can be selectively removed later, ensuring the normal preparation process of the semiconductor structure.

[0102] In this embodiment, the plurality of etching holes 50 may be arranged in a plurality of rows and two columns, and each row of etching holes 50 is located between adjacent stacked structures 20. The etching holes 50 may include a first etching hole 51 and a second etching hole 52, wherein the active layer 22 exposed by the first etching hole 51 is used to form one of the subsequent first doping region 221 and the second doping region 222, and the active layer 22 exposed by the second etching hole 52 is used to form the other of the subsequent first doping region 221 and the second doping region 222.

[0103] Afterwards, refer to Fig.12 and Fig.13 , continue to use dry etching or wet etching to remove the first sacrificial layer 21 exposed in the etched hole 50 to form a first groove 211 and a second groove 212 in each first sacrificial layer 21, and the depth direction of the first groove 211 and the second groove 212 is the same as the first direction Y, and penetrates the first sacrificial layer 21 in the first direction Y.

[0104] It should be noted that, in the second direction X, the lengths of the first trench 211 and the second trench 212 may be the same or different. In one example, when the lengths of the first trench 211 and the second trench 212 are the same, the areas of the first doped region 221 and the second doped region 222 formed subsequently are approximately the same. In another example, when the lengths of the first trench 211 and the second trench 212 are different, the areas of the first doped region 221 and the second doped region 222 formed subsequently are different. In this way, the performance of the semiconductor structure can be controlled in a targeted manner, thereby improving the usability of the semiconductor structure.

[0105] Step S400: performing ion doping on the exposed active layer to form a first doping region and a second doping region spaced apart in each active layer, wherein the active layer between the first doping region and the second doping region constitutes a channel region.

[0106] Please refer to Fig.14 The first doping region 221 and the second doping region 222 may be formed by ion diffusion or a plasma doping process (Plasma doping system, PALD for short).

[0107] The active layer 22 located between the first doping region 221 and the second doping region 222 is a channel region 223 , wherein the types of doping ions in the first doping region 221 and the second doping region 222 may be the same, and the types of doping ions in the first doping region 221 and the channel region 223 may be the same or different.

[0108] In one example, the type of doping ions in the first doping region 221 and the type of doping ions in the channel region 223 may be the same. When the doping ions in the active layer 22 are N-type ions, the active layer exposed in the first trench and the second trench may be doped with N-type ions by a plasma doping process to increase the concentration of N-type ions in the active layer 22 exposed in the first trench 211 and the second trench 212, thereby making the concentration of doping ions in the channel region 223 less than the concentration of doping ions in the first doping region 221 and the second doping region 222. It should be noted that when the doping ions in the active layer 22 are P-type ions, the formation of the first doping region 221 and the second doping region 222 is the same as described above, and this embodiment will not be described in detail.

[0109] In another example, the type of doping ions in the first doping region 221 and the type of doping ions in the channel region 223 may be different. When the doping ions in the active layer 22 are N-type ions, the active layer 22 exposed in the first trench 211 and the second trench 212 may be doped with P-type ions through a plasma doping process, so that the active layer 22 forms a PNP structure. When the doping ions in the active layer 22 are P-type ions, the active layer 22 exposed in the first trench 211 and the second trench 212 may be doped with N-type ions through a plasma doping process, so that the active layer 22 forms an NPN structure.

[0110] In this embodiment, a portion of the first sacrificial layer is removed to form a first groove and a second groove, and a portion of the active layer is exposed through the first groove and the second groove. Thereafter, the exposed active layer can be doped through an ion doping process to form a first doping region and a second doping region. In this way, the difficulty of preparing the semiconductor structure is reduced and the yield of the semiconductor structure is improved.

[0111] In some embodiments, after forming the first doping region and the second doping region, the method for preparing the semiconductor structure includes:

[0112] Please refer to Fig.15 and Fig.16 A third etched hole 70 is formed in the second sacrificial layer 40 between any two adjacent columns of stacked structures 20, that is, a third etched hole 70 is formed in the second sacrificial layer 40 in the third groove 25, and the third etched hole 70 is located between the first etched hole 51 and the second etched hole 52, and corresponds to the channel region 223. In other words, the projection of the third etched hole 70 on the stacked structure at least covers the channel region 223.

[0113] Among them, the third etched hole 70 does not expose the side of the stacked structure 20, that is, in the first direction Y, the width of the third etched hole 70 is smaller than the width of the third groove 25. In this way, it can be ensured that there is a gap between the subsequently formed first supporting structure and the active layer, which is convenient for the formation of other film layers of the transistor.

[0114] After the third etching hole 70 is formed, please refer to Fig.16 and Fig.17 , a first supporting structure 80 is formed in the third etched hole, and a second supporting structure 90 is formed in the first trench 211 and the second trench 212 .

[0115] For example, the insulating material may be formed by a physical vapor deposition process or a chemical vapor deposition process, the insulating material in the third etched hole 70 constitutes the first support structure 80, and the insulating material in the first trench 211 and the second trench 212 constitutes the second support structure 90. The materials of the first support structure 80 and the second support structure 90 include silicon nitride, but are not limited thereto.

[0116] The second supporting structure 90 is used to support any two active layers 22 in the vertical direction to prevent the active layers 22 from tilting or collapsing, thereby improving the yield of the semiconductor structure.

[0117] In some embodiments, after the steps of forming the first support structure and the second support structure, the method for preparing the semiconductor structure further includes:

[0118] Please refer to Figures 18 to 21 , removing the remaining second sacrificial layer and the first sacrificial layer, and the remaining second sacrificial layer and the remaining first sacrificial layer area constitute a filling area.

[0119] For example, continue to refer to Fig.18 and Fig.19 As shown, the second sacrificial layer 40 between any adjacent stack structures 20 may be wet-etched to expose the side surfaces of each column of the stack structures 20 .

[0120] Afterwards, please refer to Fig. 20 and Fig.21 , wet-etching the first sacrificial layer 21 in each column of the stacked structure 20 to form a filling area 100. The filling area 100 may include a first filling area 100a and a second filling area 100b that are interconnected, the first filling area 100a being the area where the remaining second sacrificial layer 40 is located, and the second filling area 100b being the area where the remaining first sacrificial layer 21 is located.

[0121] After the filling area 100 is formed, please refer to Fig. 22 and Fig.23 , a dielectric layer 110 is formed in the filling region 100 , and a portion of the dielectric layer 110 is removed to expose the channel region 223 of the active layer 22 .

[0122] For example, a dielectric layer 110 that fills the filling area 100 may be formed by a deposition process. Fig.24 and Fig.25 , patterning the dielectric layer 110 , removing a portion of the dielectric layer 110 to form a fourth trench 111 in the dielectric layer 110 , wherein the fourth trench 111 exposes the channel region 223 of the active layer 22 .

[0123] Afterwards, please refer to Figure 26 to Figure 29A gate oxide layer 120 and a conductive layer 130 are sequentially formed on the surface of the channel region 223 of the active layer 22 , and the gate oxide layer 120 and the conductive layer 130 constitute a word line structure 190 .

[0124] In one possible implementation, the gate oxide layer 120 may be formed by a selective deposition process. For example, the gate oxide layer 120 may be selectively formed only on the surface of the channel region 223 of each active layer 22 by an ALD process. In this way, the material forming the gate oxide layer 120 may be prevented from filling the fourth groove, and the etching process may be avoided to remove part of the material forming the gate oxide layer 120. This may simplify the preparation process of the gate oxide layer 120, thereby reducing the production cost of the preparation process of the semiconductor structure.

[0125] In this embodiment, the gate oxide layer 120 has a high dielectric constant, which can increase the charge storage capacity of the gate oxide layer, prevent electrons generated by the conductive layer or a small number of carriers from entering the drain through the gate oxide layer, reduce gate-induced drain leakage current, and improve the performance of the semiconductor structure.

[0126] Among them, materials with high-k dielectric constants may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO2), lanthanum oxide (LaO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTiO3), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO), lead zinc niobate (PbZnNbO3) or a combination thereof.

[0127] After the gate oxide layer 120 is formed, the gate oxide layer 120 surrounds the fifth trench 140 in the fourth trench. Fig.28 and Fig.29 , a deposition process is used to form a conductive layer 130 that fills the fifth trench 140 , wherein the material of the conductive layer 130 includes tungsten, but is not limited thereto.

[0128] In some embodiments, after forming the conductive layer, the method for preparing the semiconductor structure further includes: forming an insulating layer 150 , the insulating layer 150 covers the dielectric layer 110 and is connected to the first support structure 80 and the second support structure 90 to achieve an insulating setting between adjacent conductive layers 130 .

[0129] The insulating layer 150 , the first supporting structure 80 and the second supporting structure 90 are made of the same material, which may include silicon nitride.

[0130] The disclosed embodiment further provides a semiconductor structure, which is obtained by the preparation method in the above embodiment. Therefore, the semiconductor structure also has the beneficial effects in the above embodiment, and this embodiment will not be described in detail here.

[0131] Please refer to Fig.30 The embodiment of the present disclosure further provides a memory, which includes the semiconductor structure, the storage structure 160 and the bit line structure 170 in the above embodiment.

[0132] The semiconductor structure, storage structure and bit line structure are all arranged on the substrate 10, wherein the semiconductor structure may include an active layer 22, a gate oxide layer 120 and a conductive layer 130, and the gate oxide layer 120 and the conductive layer 130 constitute a word line structure 190. Among them, the gate oxide layer 120 surrounds the channel region of the active layer 22; the conductive layer 130 extends in a direction perpendicular to the substrate 10, and the conductive layer 130 is used to connect all active layers 22 located in the same column, and the conductive layer 130 wraps the portion of the channel region of the active layer 22 to form a transistor with the active layer 22, forming a gate all-around field effect transistor (Gate All-Around, referred to as GAA).

[0133] Exemplarily, the substrate 10 may include a first region 11 , a second region 12 and a third region 13 connected in sequence, wherein the bit line structure 170 is disposed on the first region 11 , the semiconductor structure may be disposed on the second region 12 , and the storage structure 160 may be disposed on the third region 13 .

[0134] The memory structure 160 is electrically connected to one of the first doping region 221 or the second doping region 222, and the bit line structure 170 is electrically connected to the other of the first doping region 221 or the second doping region 222. In one example, the memory structure 160 may be connected to the first doping region 221, and the bit line structure 170 may be connected to the second doping region 222. In another example, the memory structure 160 may be connected to the second doping region 222, and the bit line structure 170 may be connected to the first doping region.

[0135] In this embodiment, the extension direction of the storage structure 160 is parallel to the substrate 10, so that a plurality of stacked storage structures can be formed under the same equivalent area, thereby increasing the storage capacity of the storage structure and thus improving the storage capacity of the memory.

[0136] The memory in this embodiment includes a plurality of silicon pillars (not shown in the figure) arranged on the third area, the plurality of silicon pillars are arranged in a one-to-one correspondence with the plurality of active layers 22, and a silicon pillar and an active layer are located on the same layer, the storage structure 160 can be a plurality of capacitor structures, and each capacitor structure can include a first electrode layer, a dielectric layer, and a second electrode layer sequentially surrounding the silicon pillar.

[0137] The first electrode layer and the second electrode layer are made of the same material, and the dielectric layer also has a high dielectric constant, so that the storage capacity of the storage structure can be improved.

[0138] In some embodiments, the bit line structure 170 includes a plurality of bit lines, the plurality of bit lines are spaced apart along the second direction, and the plurality of bit lines extend parallel to each other along the first direction, and each bit line is used to connect the first doped regions of all active layers on the same layer, or to connect the second doped regions of all active layers on the same layer.

[0139] The plurality of bit lines are arranged in a step-like manner in a direction perpendicular to the substrate 10, such as Fig.31 As shown, in a direction perpendicular to the substrate 10, the bit lines are arranged in a stepped manner from bottom to top, so as to facilitate electrical contact connection of multiple bit lines in a three-dimensional structure.

[0140] In this embodiment, any two bit lines are staggered up and down, so that the preparation of the remaining data lines can be facilitated, and the spacing between these data lines is increased to prevent interference of transmission signals. In addition, the parasitic capacitance between the bit lines of the upper and lower layers can be reduced to improve the performance of the memory.

[0141] The memory further includes an isolation layer 180, which wraps each bit line to prevent electrical connection between each bit line. The isolation layer is made of silicon oxide or silicon nitride.

[0142] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0143] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0144] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The steps include: providing a substrate; Forming a plurality of columns of stacked structures spaced apart along a first direction on the substrate, each column of the stacked structures comprising a plurality of first sacrificial layers and active layers alternately stacked; Removing a portion of the first sacrificial layer to form a first groove and a second groove spaced apart along a second direction, wherein a portion of the surface of each of the active layers is exposed in the first groove and the second groove; wherein the second direction intersects with the first direction, and the first direction and the second direction are both parallel to the surface of the substrate; Performing ion doping on the exposed active layers to form a first doping region and a second doping region spaced apart in each of the active layers, wherein the active layer between the first doping region and the second doping region constitutes a channel region; The step of removing part of the first sacrificial layer comprises: forming a second sacrificial layer, wherein the second sacrificial layer fills up the area between any adjacent stacked structures and covers the top surface of the stacked structure; A portion of the second sacrificial layer is removed, and a plurality of etching holes are formed in a direction perpendicular to the substrate, each of the etching holes is located between adjacent stacked structures and exposes a side surface of the stacked structure, and a portion of the first sacrificial layer is removed along the etching holes.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: The etched holes include a first etched hole and a second etched hole, the first etched hole corresponds to the first doped region, and the second etched hole corresponds to the second doped region.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The step of forming a plurality of stacked structures spaced apart along a first direction on the substrate comprises: forming a first initial sacrificial layer and an initial active layer stacked and alternately arranged on the substrate; forming a mask layer on the initial active layer, and patterning the mask layer to form a plurality of openings spaced apart along a first direction in the mask layer; The first initial sacrificial layer and the initial active layer exposed in the opening are removed, and the retained first initial sacrificial layer and the initial active layer form a multi-column stacking structure, and a third groove extending along the second direction is formed between any two adjacent columns of the stacking structure.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The bottom of the third groove is located in the substrate.

5. The method for preparing a semiconductor structure according to claim 4, characterized in that: After forming the first doping region and the second doping region, the preparation method further includes: forming a third etched hole in the second sacrificial layer between any two adjacent columns of stacked structures, wherein the third etched hole corresponds to the channel region, is located between the first etched hole and the second etched hole, and does not expose the side surface of the stacked structure; A first supporting structure is formed in the third etched hole, and a second supporting structure is formed in the first trench and the second trench.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: After forming the first supporting structure and the second supporting structure, the preparation method further includes: removing the remaining second sacrificial layer and the first sacrificial layer to form a filling area; forming a dielectric layer in the filling region, and removing a portion of the dielectric layer to expose the channel region; A gate oxide layer and a conductive layer are sequentially formed on the surface of the channel region of the active layer.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The step of removing the remaining second sacrificial layer and the first sacrificial layer comprises: The second sacrificial layer between any adjacent stacked structures is wet-etched, and the first sacrificial layer in each column of the stacked structures is wet-etched to form the filling area.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: After forming the conductive layer, the preparation method further comprises: An insulating layer is formed, where the insulating layer covers the dielectric layer and is connected to the first supporting structure and the second supporting structure.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: The insulating layer, the first supporting structure and the second supporting structure are made of the same material.

10. The method for preparing a semiconductor structure according to any one of claims 1 to 2, characterized in that: The first doping region, the second doping region and the channel region have the same doping ion type, and the concentration of the doping ions in the channel region is lower than the concentration of the doping ions in the first doping region and the second doping region.

11. The method for preparing a semiconductor structure according to any one of claims 1 to 2, characterized in that: The step of forming a first initial sacrificial layer and an initial doping layer stacked and alternately arranged on the substrate comprises: A first initial sacrificial layer and an initial doping layer are alternately stacked and formed on the substrate by an epitaxial growth process, wherein the first initial sacrificial layer comprises silicon germanium, silicon phosphide or silicon nitride.

12. A semiconductor structure, characterized in that: The semiconductor structure is manufactured by the method for manufacturing a semiconductor structure according to any one of claims 1 to 11.

13. A memory, characterized in that: The memory includes the semiconductor structure as described in claim 12, and the memory also includes a storage structure and a bit line structure, the storage structure is electrically connected to one of the first doping region or the second doping region, and the bit line structure is electrically connected to the other of the first doping region or the second doping region.

14. The memory according to claim 13, characterized in that: The bit line structure includes a plurality of bit lines arranged in parallel and at intervals, and the plurality of bit lines are arranged in a step-like manner in a direction perpendicular to the substrate.

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