An active current compensation output circuit based on Gm-C integrator

Abstract

The present invention belongs to the field of medical electronic technology, and specifically provides an active current compensation output circuit based on a Gm-C integrator, including: a voltage divider circuit, an active charge balancing circuit and a stacked output driver circuit; the stimulation electrode voltage and the reference electrode voltage are converted into low-voltage signals Vip and Vin through the voltage divider circuit, and input into the active charge balancing circuit; the active charge balancing circuit outputs the compensation current Iin and the output switch signal SW to the stacked output driver circuit, SW=1, the stacked output driver circuit generates a negative compensation current to discharge the stimulation electrode, SW=0, the stacked output driver circuit generates a positive compensation current to charge the stimulation electrode. The present invention adopts a compensation current output structure of a single-phase power supply and a single stimulation electrode, which ensures the normal two-phase output of the compensation current, reduces the design complexity, saves chip area, saves device consumption, and is conducive to on-chip integration.

Description

Technical Field

[0001] The invention belongs to the field of medical electronic technology, and specifically provides an active current compensation output circuit based on a Gm-C integrator. Background Art

[0002] With the continuous cross-integration of biomedicine and integrated circuits, neural stimulators can be used to interact with the contacting neural tissue, read the impedance and potential information at that point, and deliver stimulation current to achieve the purpose of changing the cell potential and thus treating the human body. Neural electrical stimulation has the advantages of being implantable, not causing human rejection, being able to work as an independent module, low power consumption, low volume, fast feedback, and high-speed response; however, factors such as the mismatch of the circuit itself, non-ideal factors of the layout, and deviations caused by the manufacturing process will lead to mismatch in the output current of the neural stimulator, which in turn leads to mismatch between the neural electrode and the reference electrode or ground potential, and ultimately leads to irreversible damage to the electrode and even the neural tissue.

[0003] In order to ensure that there is no excessive residual charge on the electrode after the completion of neural electrical stimulation, researchers have proposed a variety of charge balancing schemes. Active charge balancing based on potential detection is a relatively common method. When a neural electrical stimulation scheme with a single stimulation electrode is used, the voltage of the neural electrode and the reference electrode is detected to determine whether the neural electrode voltage is within the safety window. If not, active charge balancing is performed based on the neural electrode voltage at this time, that is, compensating current is sent to the electrode to bring the neural electrode voltage back to the safety window. Figure 1 As shown in the figure, after the sensing module detects the potential of the neural electrode and the reference electrode in the high voltage domain, it performs level shifting to the comparator in the low voltage domain; because the subtractor in the control module can only perform the operation of subtracting a small voltage from a large voltage, the comparator must first determine the size of the two, and then perform a difference operation based on the result; after obtaining the difference result, the comparator in the output module determines the active charge balancing circuit to charge or discharge the stimulation electrode based on the polarity of the difference, so that the voltage difference between the stimulation electrode and the reference electrode is within the safety window, achieving active charge balance; the curve of the residual charge changing with the stimulation current is shown in Figure 2As shown, it can be seen from the figure that after the nerve electrical stimulation is completed with stimulation currents of different amplitudes, the remaining charge of the nerve electrode after charge balancing is greatly reduced, ensuring the safety of the nerve electrical stimulation. However, there are still many drawbacks in the existing active charge balancing circuits: 1) When the active charge balancing circuit outputs at full amplitude, the equivalent resistance of the stimulation electrode is very large. After the biphasic current flows through the stimulation electrode, a large voltage difference is generated on the stimulation electrode, making it inevitable to use a high-voltage process for the device. The high-voltage process greatly increases the complexity of circuit design and limits the application of the circuit; 2) Currently, the mainstream nerve stimulators adopt the structure of a single stimulation electrode and a biphasic voltage source (i.e., using a negative voltage source) or a single-phase voltage source and a dual-stimulation electrode. The corresponding active charge balancing circuit for the former also needs to be designed in the negative voltage domain, and the corresponding dual-stimulation electrodes for the latter will cause waste in terms of area, cost, power consumption, etc.; 3) In the active charge balancing circuit in a low-frequency signal processing environment, an integration operation is required to integrate the remaining electrode voltage after multiple stimulation pulses to achieve a long-term charge balance state. However, the integrator used for the integration operation requires a time constant in the millisecond level, which requires a large RC value. The too large RC value will bring about a large waste of chip area and a large power consumption. Summary of the Invention

[0004] The purpose of the present invention is to provide an active current compensation output circuit based on a Gm-C integrator to solve the above-mentioned many problems existing in the existing active charge balancing circuits.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] An active current compensation output circuit based on a Gm-C integrator includes: a voltage division circuit, an active charge balancing circuit, and a stacked output driving stage circuit; characterized in that the stimulation electrode voltage VE and the reference electrode voltage VCM are converted into low-voltage signals Vip and Vin through the voltage division circuit and input to the active charge balancing circuit; the active charge balancing circuit includes: a Gm-C integrator, a voltage-to-current circuit, and a comparator. The low-voltage signals Vip and Vin are input to the Gm-C integrator. After the Gm-C integrator completes the integration operation, it outputs the corresponding voltage signals Voutp and Voutn to the voltage-to-current circuit, and the voltage-to-current circuit outputs a compensation current Iin to the stacked output driving stage circuit; at the same time, the low-voltage signals Vip and Vin are input to the comparator. After the comparator compares Vip and Vin, it outputs a switch signal SW to the stacked output driving stage circuit. When Vip>Vin, then SW = 1, and the stacked output driving stage circuit generates a negative compensation current to discharge the stimulation electrode. When Vip<Vin, then SW = 0, and the stacked output driving stage circuit generates a positive compensation current to charge the stimulation electrode.

[0007] Further, the Gm-C integrator includes: a Gm-C circuit and a differential differential amplifier, the input end of the Gm-C circuit is connected to the input end of the Gm-C integrator, and the output end of the Gm-C circuit is connected to the output end of the Gm-C integrator; the differential differential amplifier includes: deep n-well MOS tubes M5 and M6, transconductance amplifiers OTA1 and OTA2, MOS tubes M7 and M8, zero adjustment resistor R1, and compensation capacitor C2; the gates of M5 and M6 are connected to the bias voltage Ubias, the drain of M5 is connected to the first output end of the Gm-C integrator, the output voltage signal Voutp, and the drain of M6 is connected to the output voltage signal Voutp. The drain is connected to the second output terminal of the Gm-C integrator and the output voltage signal Voutn, the source of M5 is connected to the drain of M7, the source of M6 is connected to the drain of M8, the sources of M7 and M8 are grounded, the gates of M7 and M8 are connected and connected to the output terminals of OTA1 and OTA2, the negative input terminals of OTA1 and OTA2 are connected to the bias voltage Ucmout, the positive input terminal of OTA1 is connected to the voltage signal Voutp, and the positive input terminal of OTA2 is connected to the voltage signal Voutn; after R1 and C2 are connected in series, one end is the output terminal of OTA1 and OTA2, and the other end is grounded.

[0008] Furthermore, the stacked output driver circuit includes: MOS tubes M9, M10, M19 and M20, operational amplifiers A1 and A2, a first stacking module and a second stacking module, switch tubes M17 and M18; the sources of M9 and M10 are connected to a high voltage source, the gates of M9 and M10 are connected to the output end of A1, the drain of M9 is connected to the positive input end of A1 and the first port of the first stacking module, and the drain of M10 is connected to the negative input end of A1 and the first port of the second stacking module; the first stacking module The third port of the second stacked module is connected to the source of M17, the gate of M17 is connected to the switching signal SW, and the drain of M17 is connected to the positive input terminal of A2 and the drain of M19; the third port of the second stacked module is connected to the source of M18, the gate of M18 is connected to the switching signal SW, and the drain of M18 is connected to the negative input terminal of A2 and the drain of M20; the gates of M19 and M20 are connected to the output terminal of A2, and the sources of M19 and M20 are connected to the compensation current Iin; the second port of the second stacked module is connected to the stimulation electrode.

[0009] Furthermore, the first stacking module and the second stacking module adopt the same structure, including: MOS tubes M11~M15, the source of M11 serves as the first port of the stacking module, the gate of M11 is connected to the drain of M12, the drain of M11 is connected to the gate of M12 and the source of M13, the source of M12, the gate of M13, the gate of M14, and the source of M15 are all connected to the bias voltage VB1, the drain of M13 is connected to the drain of M14 and serves as the second port of the stacking module, the source of M14 is connected to the gate of M15 and the drain of M16, the drain of M15 is connected to the gate of M16, and the source of M16 serves as the third port of the stacking module.

[0010] Based on the above technical solution, the beneficial effect of the present invention is to provide an active current compensation output circuit based on a Gm-C integrator, which has the following advantages:

[0011] 1. The present invention adopts a compensation current output structure of a single-phase power supply and a single stimulation electrode. Compared with the traditional dual-phase power supply and a single stimulation electrode or a single-phase power supply and a dual stimulation electrode structure, it ensures the normal dual-phase output of the compensation current while reducing the design complexity and saving device consumption;

[0012] 2. The present invention uses a MOS tube stacking structure in the output driver stage, which can send the compensation current to a high-voltage environment, avoiding the use of high-voltage devices and effectively reducing the complexity of the compensation circuit design;

[0013] 3. The present invention selects to use the Gm-C circuit in the integrator, realizes a large resistance value with a small number of simple devices, obtains a large integration constant, completes the integration of the electrode residual voltage after several stimulation cycles, and effectively saves chip area, which is conducive to on-chip integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 The schematic diagram of the circuit of the existing active charge balance based on potential detection is shown in FIG.

[0015] Figure 2 for Figure 1 The graph showing the residual charge of active charge balance changes with stimulation current.

[0016] Figure 3 It is a schematic diagram of the principle of the active current compensation output circuit based on the Gm-C integrator in the present invention.

[0017] Figure 4 It is a structural schematic diagram of the active current compensation output circuit based on the Gm-C integrator in the present invention.

[0018] Figure 5 It is a schematic diagram of the structure of the Gm-C integrator in the present invention.

[0019] Figure 6 It is a schematic diagram of the structure of the stacked output driver stage circuit in the present invention.

[0020] Figure 7 It is a curve diagram showing the change of the output current of the active current compensation output circuit based on the Gm-C integrator according to the present invention as a function of the input voltage difference. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and beneficial effects of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0022] This embodiment provides an active current compensation output circuit based on a Gm-C integrator, adopting a single-phase power supply and a single-stimulating electrode structure. As Figure 3 shown, where C dl , R F , R S constitute a stimulating electrode model, I E represents the stimulating current, V E represents the stimulating electrode voltage, V CM represents the reference electrode voltage. The positive and negative compensation currents respectively charge and discharge the stimulating electrode; the core innovation lies in: 1) Designing the active charge balance circuit in the low-voltage domain, and outputting the compensation current through the corresponding stacked output stage, avoiding the use of high-voltage devices; 2) Based on the active charge balance circuit in the low-voltage domain, cooperating with the design of the stacked output driver stage, it can complete the charging and discharging operations of the stimulating electrode in the high-voltage domain, thereby realizing the stimulating operation of a single-phase power supply and a single-stimulating electrode, avoiding the use of a double-stimulating electrode; 3) Designing a Gm-C circuit, replacing a high-value resistor through an extremely low transconductance. At this time, the capacitance value can be very small, avoiding the waste of chip area.

[0023] The active current compensation output circuit based on the Gm-C integrator in this embodiment is as Figure 4 shown, including: a voltage division circuit, an active charge balance circuit, and a stacked output driver stage circuit (Output Driver); among them, the stimulating electrode voltage VE and the reference electrode voltage VCM in the high-voltage domain are converted into low-voltage signals Vip and Vin through the voltage division circuit and input to the active charge balance circuit; the active charge balance circuit includes: a Gm-C integrator, a voltage-to-current circuit, and a comparator. The low-voltage signals Vip and Vin are input to the Gm-C integrator. After the Gm-C integrator completes the integration operation, it outputs the corresponding voltage signals Voutp and Voutn to the voltage-to-current circuit. The voltage-to-current circuit outputs a compensation current Iin corresponding to the difference between Vip and Vin to the stacked output driver stage circuit; at the same time, the above low-voltage signals Vip and Vin are input to the comparator. After the comparator compares Vip and Vin, it outputs a switch signal SW to the stacked output driver stage circuit to judge whether the stimulating electrode needs to be charged or discharged at this time: when Vip>Vin, then SW = 1; when Vip<Vin, then SW = 0; in summary, the compensation current Iin serves as the current source of the stacked output driver stage circuit. When SW = 1, the stacked output driver stage circuit generates a negative compensation current to discharge the stimulating electrode. When SW = 0, the stacked output driver stage circuit generates a positive compensation current to charge the stimulating electrode.

[0024] Furthermore, the Gm-C integrator is composed of a Gm-C circuit, as Figure 5As shown, it includes: a Gm-C circuit and a differential differential amplifier (DDA); the differential differential amplifier (DDA) includes: deep n-well MOS tubes M5 and M6, transconductance amplifiers OTA1 and OTA2, MOS tubes M7 and M8, a zero adjustment resistor R1, and a compensation capacitor C2; the gates of the deep n-well MOS tubes M5 and M6 are connected to a bias voltage Ubias, the drain of the deep n-well MOS tube M5 is connected to a first output terminal of the Gm-C integrator and an output voltage signal Voutp, the drain of the deep n-well MOS tube M6 is connected to a second output terminal of the Gm-C integrator and an output voltage signal Voutn, and the deep n-well MOS tube M6 is connected to a second output terminal of the Gm-C integrator and an output voltage signal Voutn. The source of the S transistor M5 is connected to the drain of the MOS transistor M7, the source of the deep n-well MOS transistor M6 is connected to the drain of the MOS transistor M8, the sources of the MOS transistors M7 and M8 are grounded (AVSS), the gates of the MOS transistors M7 and M8 are connected, and are connected to the output ends of OTA1 and OTA2, the negative input ends of OTA1 and OTA2 are connected to the bias voltage Ucmout, the positive input end of OTA1 is connected to the voltage signal Voutp, and the positive input end of OTA2 is connected to the voltage signal Voutn; the zero adjustment resistor R1 and the compensation capacitor C2 are connected in series, one end of which is the output end of OTA1 and OTA2, and the other end is grounded;

[0025] In the Gm-C circuit, the sources of the MOS transistors I1 and I2 are connected to a voltage source (AVDD, 2.5V), and the gates are respectively connected to the bias voltage provided by the front-stage bias circuit; the drain of the MOS transistor I1 is connected to the sources of the MOS transistors M1a and M1b, and the drain of the MOS transistor I2 is connected to the sources of the MOS transistors M2a and M2b; the gates of the MOS transistors M1a and M2a are connected to the first input terminal of the Gm-C integrator and the input low-voltage signal Vip, and the gates of the MOS transistors M1b and M2b are connected to the second input terminal of the Gm-C integrator and the input low-voltage signal Vip. A low voltage signal Vin is input, the drains of the MOS tubes M1a and M2b are connected to the source of the MOS tube M3a, and the drains of the MOS tubes M1b and M2a are connected to the source of the MOS tube M3b; the gates of the MOS tubes M3 and M4 are connected to the bias voltage Ucmout, the drain of the MOS tube M3 is connected to the first output terminal of the Gm-C integrator and the output voltage signal Voutp, the drain of the MOS tube M4 is connected to the second output terminal of the Gm-C integrator and the output voltage signal Voutn, and the capacitor C1 is connected between the drains of the MOS tubes M3 and M4;

[0026] It should be noted that: the substrates of all MOS tubes are short-circuited with the source, which is not shown in the figure; in the Gm-C integrator, in order to ensure the effect of the ideal integrator as much as possible, M3 and M5, M4 and M6 are respectively used as folded common source and common gate stages to improve the output impedance of the integrator; the bias voltage Ucmout ensures the common mode level of the output voltages Voutp and Voutn through DDA, and is biased to the gates of M3 and M4, limiting the maximum value of the output voltages Voutp and Voutn; the bias voltage Ubias is used to provide bias for M5 and M6, and also limits the minimum value of the output voltages Voutp and Voutn; in addition, in order to ensure the stability of the loop, Miller compensation (R1 and C2) is added to the DDA output; M7 and M8 are used to cooperate with DDA to realize feedback control of the circuit.

[0027] Further, the stacked output driver stage circuit is as follows Figure 6 As shown, it includes: MOS tubes M9, M10, M19 and M20, operational amplifiers A1 and A2, a first stacking module and a second stacking module, and switch tubes M17 and M18; the source of the MOS tube M9 and the MOS tube M10 are connected to the high voltage source (AVDD_High), the gate of the MOS tube M9 and the MOS tube M10 are connected to the output end of the operational amplifier A1, the drain of the MOS tube M9 is connected to the positive input end of the operational amplifier A1 and the first port of the first stacking module, and the drain of the MOS tube M10 is connected to the negative input end of the operational amplifier A1 and the first port of the second stacking module; the third port of the first stacking module is connected to the switch The source of the switch tube M17, the gate of the switch tube M17 is connected to the switching signal SW, the drain of the switch tube M17 is connected to the positive input terminal of the operational amplifier A2 and the drain of the MOS tube M19; the third port of the second stacked module is connected to the source of the switch tube M18, the gate of the switch tube M18 is connected to the switching signal SW, the drain of the switch tube M18 is connected to the negative input terminal of the operational amplifier A2 and the drain of the MOS tube M20; the gates of the MOS tubes M19 and M20 are connected to the output terminal of the operational amplifier A2, and the sources of the MOS tubes M19 and M20 are connected to the compensation current Iin; the second port of the second stacked module is connected to the stimulation electrode;

[0028] The first stacking module and the second stacking module adopt the same structure, including: MOS tubes M11 to M15, the source of M11 is used as the first port of the stacking module, the gate of M11 is connected to the drain of M12, the drain of M11 is connected to the gate of M12 and the source of M13, the source of M12, the gate of M13, the gate of M14, and the source of M15 are all connected to the bias voltage VB1, the drain of M13 is connected to the drain of M14 and serves as the second port of the stacking module, the source of M14 is connected to the gate of M15 and the drain of M16, the drain of M15 is connected to the gate of M16, and the source of M16 serves as the third port of the stacking module;

[0029] The stimulation electrode is represented by an electrode model, where R f is the Faradaic resistance, which is a time-varying resistance controlled by the diffusion of reactants to the electrode in the charge transfer reaction and is in the MΩ level; C dl is a double-layer capacitor, which is generated by the aggregation of ions tightly adsorbed on the electrode surface and relatively discrete ions in its diffusion layer, and its size is nF level; Rs is the solution diffusion resistance, which is mainly determined by the type of ions in the solution at the contact surface between the electrode and the tissue, and its size is KΩ level; Cdl is connected in parallel with Rs, and one end is connected to the second port of the second stacking module, and the other end is connected to RS to the positive electrode of the reference voltage source VCM, and the negative electrode of the reference voltage source is grounded;

[0030] It should be noted that: the substrates of all MOS tubes are short-circuited with the source, which is not shown in the figure; in the stacked output driver stage circuit, operational amplifiers A1 and A2 perform a clamping operation on the circuit (the outputs of the operational amplifiers are respectively added to the gates of the M9 tube and the M10 tube and the gates of the M19 tube and the M20 tube to achieve feedback control), two identical stacked modules bear the voltage drop of the stack (the bias voltage VB1 ensures that the stacked MOS tube works normally), and the switch tubes M17 and M18 respectively control the current flow direction in the driver stage circuit; the output of the driver stage circuit is located at the drain of the M13 tube and the M14 tube in the second stack structure, and is output in the form of current; and in the present invention, the operational amplifiers A1 and A2 use single-stage folded common source and common gate tubes, the gain can meet the requirements, and will not cause loop instability.

[0031] In terms of working principle:

[0032] (1) Stacked output driver stage circuit

[0033] The stacked output driver circuit transfers the stimulation current and compensation current from the low voltage domain to the high voltage domain and outputs them to the stimulation electrode through stacked MOS tubes. The stacked output stage cooperates with the corresponding clock pulse and switch to achieve the purpose of outputting positive compensation current and negative compensation current to the electrode respectively. Figure 6As shown, the compensation current Iin in the low-voltage domain is output to the stimulation electrode through the stacked structure; the switch signal SW is generated by the comparator in the active charge balance circuit in the low-voltage domain, and it determines whether to discharge or compensate the voltage according to the magnitude of the voltage on the stimulation electrode, and at the same time obtains the value of SW; if the stimulation electrode voltage is greater than the reference electrode voltage, charge discharge is performed, at this time SW = 1, and a current is drawn from the stimulation electrode to reduce the stimulation electrode voltage to within the safety window near the reference electrode voltage; if the stimulation electrode voltage is less than the reference electrode voltage, charge compensation is performed, at this time SW = 0, and a current is injected into the stimulation electrode to raise the stimulation electrode voltage to within the safety window near the reference electrode voltage. AVDD_High is the power supply voltage in the high-voltage domain, and the biasing of each voltage source in the circuit is related to AVDD_High; since the driving stage only provides a path for current output, that is, only changes the direction of current flow, therefore, the positive and negative compensation currents output to the stimulation electrode are themselves matched (essentially both are the compensation current Iin), and coupled with the operational amplifier clamping the MOS transistor, the current replication is more accurate, so the driving stage circuit will not cause additional errors.

[0034] (2) Active charge balance circuit

[0035] The active charge balance circuit can generate a biphasic compensation current according to the voltage difference on the electrode. The magnitude and polarity of the compensation current are related to the stimulation electrode voltage: if the stimulation electrode voltage is less than the reference electrode voltage, a positive compensation current for the compensation voltage is output to raise the stimulation electrode voltage to within the safety window (±100 mV) close to the reference electrode voltage; if the stimulation electrode voltage is greater than the reference electrode voltage, a negative compensation current for the discharge voltage is output to lower the stimulation electrode voltage to within the safety window (±100 mV) close to the reference electrode voltage. As Figure 4 shown, the stimulation electrode voltage and the reference electrode voltage are divided and sent to the active charge balance circuit in the low-voltage domain, respectively represented as Vip and Vin. These two voltages are input to the integrator composed of the Gm-C circuit, and the two output voltages generated are used as inputs to the voltage-to-current (V-I) circuit. The voltage-to-current circuit generates a proportional compensation current Iin according to the magnitude of the input voltage difference and sends it to the driving stage; at the same time, Vip and Vin are input to the comparator. If Vip > Vin, that is, the stimulation electrode voltage is greater than the reference electrode voltage, the compensation current Iin output by the circuit should be used to discharge the stimulation electrode voltage, and at this time the switch signal SW = 1; if Vip < Vin, that is, the stimulation electrode voltage is less than the reference electrode voltage, the compensation current Iin output by the circuit should be used to charge the stimulation electrode voltage, and at this time the switch signal SW = 0.

[0036] (3) Gm-C integrator

[0037] The active charge balancing circuit can integrate the residual electrode voltage after several stimulation cycles to achieve a long-term stable charge balance state, and the integration result is used to measure the mismatch degree of the positive and negative stimulation currents under these stimulation cycles. In the traditional sense, integrators that realize large integral constants require very large resistance and capacitance values, which leads to a great consumption of chip area and is not conducive to on-chip integration. In response to this problem, the present invention designs an operational amplifier of a Gm-C circuit with a feedback function as an integrator to integrate the mismatch of the stimulation current for several cycles; wherein, the large resistance is realized by the inverse of the transconductance of the MOS tube, and the transconductance is realized by a cross-coupled MOS tube, so that a very small transconductance, that is, a very large resistance, can be obtained, which reduces the consumption of capacitance value and capacitance area and facilitates on-chip integration. In the actual circuit, it is necessary to adjust the circuit structure and use MOS tubes to realize large resistance to save area. For example Figure 5 As shown, M1 and M2 can realize large resistance. The transconductance Gm provided by the Gm-C circuit in the dotted box is Gm=g m1 -g m2 , g m1 is the transconductance of M1 tube, g m2 is the transconductance of the M2 tube. By adjusting the sizes of the M1 tube and the M2 tube, the total transconductance Gm of the nS level can be obtained to replace the large resistance resistor. Furthermore, Vip and Vin come from the low-voltage signal after the previous reference electrode voltage and the stimulation electrode voltage are divided by resistors. Therefore, the Gm-C circuit all uses devices with standard processes instead of high-voltage devices. In addition, in order to reduce the complexity of the circuit, the present invention does not use DDA (differential differential amplifier), but selects two simple five-tube OTAs; does not use adjustable CMOS resistors to reduce the size of the time constant and reduce the startup time of the circuit; does not add a DAC current source and a bias current source at the bottom, but chooses to add Voutp and Voutn to the voltage-to-current circuit (VI) of the subsequent stage, so that a compensation current proportional to the input voltage difference can be linearly generated.

[0038] In this embodiment, the comparator (Com) circuit uses a Strong-Arm comparator, and the voltage-to-current (VI) circuit uses a simple current source. The output current is proportional to the input voltage. The input voltage difference is defined as the difference between the stimulation electrode voltage and the reference electrode voltage. Under different process angles, the output current of the active current compensation output circuit based on the Gm-C integrator in the present invention changes with the input voltage difference. Figure 7 As shown in the figure, it can be seen that for different voltage differences between the stimulation electrode voltage and the reference electrode voltage, the active charge balancing circuit can output a compensation current that is proportional to the voltage difference, and the current polarity meets the requirement of reducing the voltage difference, thereby achieving active charge balance.

[0039] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. An active current compensation output circuit based on a Gm-C integrator, comprising: Voltage dividing circuit, active charge balancing circuit and stacked output driving stage circuit; characterized in that the stimulating electrode voltage VE and the reference electrode voltage VCM are converted into voltage signals Vip and Vin through the voltage dividing circuit and input to the active charge balancing circuit; the active charge balancing circuit includes: a Gm-C integrator, a voltage-to-current circuit and a comparator. The voltage signals Vip and Vin are input to the Gm-C integrator. After the Gm-C integrator completes the integration operation, it outputs the corresponding voltage signals Voutp and Voutn to the voltage-to-current circuit. The voltage-to-current circuit outputs a compensation current Iin to the stacked output driving stage circuit; at the same time, the voltage signals Vip and Vin are input to the comparator. After the comparator compares Vip and Vin, it outputs a switching signal SW to the stacked output driving stage circuit. When Vip>Vin, then SW = 1, and the stacked output driving stage circuit generates a negative compensation current to discharge the stimulating electrode. When Vip<Vin, then SW = 0, and the stacked output driving stage circuit generates a positive compensation current to charge the stimulating electrode; The Gm-C integrator includes: a Gm-C circuit and a differential difference amplifier. The input end of the Gm-C circuit is connected to the input end of the Gm-C integrator, and the output end of the Gm-C circuit is connected to the output end of the Gm-C integrator; the differential difference amplifier includes: deep n-well MOS transistors M5 and M6, transconductance amplifiers OTA1 and OTA2, MOS transistors M7 and M8, a zero-adjusting resistor R1, and a compensation capacitor C2; the gates of M5 and M6 are connected to the bias voltage Ubias. The drain of M5 is connected to the first output end of the Gm-C integrator to output the voltage signal Voutp. The drain of M6 is connected to the second output end of the Gm-C integrator to output the voltage signal Voutn. The source of M5 is connected to the drain of M7. The source of M6 is connected to the drain of M8. The sources of M7 and M8 are grounded. The gates of M7 and M8 are connected and connected to the output ends of OTA1 and OTA2. The negative input ends of OTA1 and OTA2 are connected to the bias voltage Ucmout. The positive input end of OTA1 is connected to the voltage signal Voutp. The positive input end of OTA2 is connected to the voltage signal Voutn; one end of R1 and C2 in series is connected to the output ends of OTA1 and OTA2, and the other end is grounded; The stacked output drive stage circuit includes: MOS tubes M9, M10, M19 and M20, operational amplifiers A1 and A2, a first stacking module and a second stacking module, switch tubes M17 and M18; the source of M9 and M10 is connected to a voltage source, the gate of M9 and M10 is connected to the output end of A1, the drain of M9 is connected to the positive input end of A1 and the first port of the first stacking module, and the drain of M10 is connected to the negative input end of A1 and the first port of the second stacking module; the third end of the first stacking module The first port of the second stacked module is connected to the source of M17, the gate of M17 is connected to the switching signal SW, and the drain of M17 is connected to the positive input terminal of A2 and the drain of M19; the third port of the second stacked module is connected to the source of M18, the gate of M18 is connected to the switching signal SW, and the drain of M18 is connected to the negative input terminal of A2 and the drain of M20; the gates of M19 and M20 are connected to the output terminal of A2, and the sources of M19 and M20 are connected to the compensation current Iin; the second port of the second stacked module is connected to the stimulation electrode.

2. The active current compensation output circuit based on the Gm-C integrator according to claim 1, characterized in that: The first stacking module and the second stacking module adopt the same structure, including: MOS tubes M11~M15, the source of M11 serves as the first port of the stacking module, the gate of M11 is connected to the drain of M12, the drain of M11 is connected to the gate of M12 and the source of M13, the source of M12, the gate of M13, the gate of M14, and the source of M15 are all connected to the bias voltage VB1, the drain of M13 is connected to the drain of M14 and serves as the second port of the stacking module, the source of M14 is connected to the gate of M15 and the drain of M16, the drain of M15 is connected to the gate of M16, and the source of M16 serves as the third port of the stacking module.

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