A MOSFET test circuit

Abstract

The present application provides a MOS tube test circuit, which includes a trigger module, a sampling module and an amplification module. The driving signal generated by the trigger module controls the working state of the sampling module through the driving signal. When the sampling module is enabled and started, the MOS tube to be tested is sampled through multiple sampling resistors inside the sampling module to obtain a sampling voltage; the sampling voltage is amplified by the amplification module to obtain a target voltage. The present application samples and amplifies the parameters of the MOS tube by means of multiple sampling resistors, which not only avoids dependence on current probes, reduces test costs, but also improves the precision and accuracy of testing MOS tubes.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, and in particular to a MOS tube testing circuit. Background Art

[0002] With the rapid development of electronic devices, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is an important component in electronic devices, and the performance test of Metal-Oxide-Semiconductor Field-Effect Transistor is particularly important. Metal-Oxide-Semiconductor Field-Effect Transistor is referred to as MOS tube. The traditional MOS tube test method usually uses a high-precision current probe for sampling to complete the test of MOS tube. On the one hand, during the test process, the current probe will resonate with the junction capacitance of the MOS tube. When the resonance is too large, the accuracy of the test result of the MOS tube is reduced. On the other hand, the price of the current probe is expensive, which increases the test cost.

[0003] Therefore, how to provide a low-cost and high-precision MOS tube testing solution is a technical problem that urgently needs to be solved. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a MOS tube test circuit to solve at least one of the above-mentioned technical problems.

[0005] In order to achieve the above-mentioned purpose and other related purposes, the technical solution provided by this application is as follows.

[0006] According to the present application, a MOS tube test circuit is provided, comprising:

[0007] A trigger module, connected to a first power supply voltage and a pulse signal, wherein the first power supply voltage provides a working power supply for the trigger module, so that the trigger module generates a driving signal according to the pulse signal;

[0008] A sampling module is connected to a second power supply voltage, the trigger module and the MOS tube to be tested, wherein the second power supply voltage provides a working power supply for the sampling module, and the working state of the sampling module is controlled by the driving signal. When the sampling module is enabled and started, the MOS tube to be tested is sampled through a plurality of sampling resistors inside the sampling module to obtain a sampling voltage;

[0009] The amplification module is connected to the sampled voltage and amplifies the sampled voltage to obtain a target voltage.

[0010] In one embodiment of the present invention, the trigger module includes a first input interface, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor and a first chip, the first end of the first input interface is connected to the first input end of the first chip via the first resistor connected in series, the second end of the first input port is connected to the first end of the first capacitor, the first end of the first capacitor is also connected to the first analog ground end, the first input end of the first chip is also connected to the second end of the first capacitor, the ground end of the first chip is also connected to the first end of the first capacitor, the power supply end of the first chip is connected to the ground end of the first chip via the second capacitor connected in series, the first output end of the first chip is connected to the first end of the third resistor via the second resistor connected in series, the second end of the third resistor is also connected to the first end of the first capacitor, the third capacitor is connected in parallel with the third resistor, wherein the power supply end of the first chip is connected to the positive electrode of the first power supply voltage, the second end of the first input interface is connected to the negative electrode of the first power supply voltage, the first end of the first input interface is connected to the pulse signal, and the first end of the third resistor is connected to output the drive signal externally.

[0011] In one embodiment of the present invention, the sampling module includes a current sampling unit and a voltage sampling unit. The current sampling unit is connected to the MOS tube to be tested, the second power supply voltage and the trigger module. The second power supply voltage provides a working power supply for the current sampling unit. Under the control of the driving signal, the current sampling unit samples the MOS tube to be tested to obtain a sampling current. The voltage sampling unit is connected in series to the current sampling unit, and performs non-inductive current-voltage conversion on the sampling current through multiple sampling resistors to obtain the sampling voltage.

[0012] In one embodiment of the present invention, the current sampling unit includes a second input interface, a fuse, a fourth resistor, a fifth resistor, a switch tube, a first inductor and a fourth capacitor, the first end of the fuse is connected to the second analog ground via the fourth capacitor connected in series, the first end of the fifth resistor is connected to the second analog ground, the first end of the fuse is also connected to the first end of the first inductor, the first end of the first inductor is also connected to the second end of the second input interface, the second end of the first inductor is connected to the third end of the second input interface, the first end of the second input interface is connected to the third end of the second input interface via the fourth resistor connected in series, the third end of the second input interface is connected to the input end of the switch tube, and the output end of the switch tube is connected to the second end of the third resistor, wherein the second end of the fuse is connected to the positive electrode of the second power supply voltage, the second end of the fifth resistor is connected to the negative electrode of the second power supply voltage, the first end of the second input interface is connected to the gate of the MOS tube to be tested, the second end of the second input interface is connected to the drain of the MOS tube to be tested, the third end of the second input interface is connected to the source of the MOS tube to be tested, and the output end of the switch tube is connected to the second analog ground via the voltage sampling unit.

[0013] In one embodiment of the present invention, the voltage sampling unit includes 2N sampling resistors, the first end of the i-th sampling resistor is connected to the output end of the switch tube, the second end of the i-th sampling resistor is connected to the second analog ground, and the first end of the i-th sampling resistor outputs the sampling voltage to the outside, wherein i and N are positive integers, and 1≤i≤2N.

[0014] In one embodiment of the present invention, 2N sampling resistors are non-inductively arranged on a circuit board, and N sampling resistors are respectively arranged on the front and back of the circuit board. The flow direction of the sampling current on the N sampling resistors on the front of the circuit board is a first direction, and the flow direction of the sampling current on the N sampling resistors on the back of the circuit board is a second direction, and the first direction is opposite to the second direction.

[0015] In one embodiment of the present invention, the amplification module includes an operational amplifier, a sixth resistor, a seventh resistor and an eighth resistor, the inverting input terminal of the operational amplifier is connected to the second analog ground via the sixth resistor connected in series, the inverting input terminal of the operational amplifier is also connected to the output terminal of the operational amplifier via the seventh resistor connected in series, and the output terminal of the operational amplifier is connected to the second analog ground via the eighth resistor connected in series, wherein the non-inverting input terminal of the operational amplifier is connected to the sampling voltage, and the output terminal of the operational amplifier outputs the target voltage to the outside.

[0016] In one embodiment of the present invention, the MOS tube test circuit further includes a power supply module and a voltage stabilizing module. The power supply module is connected to a third power supply voltage, and filters and steps down the third power supply voltage to obtain a transition voltage. The voltage stabilizing module is connected to the transition voltage, and stabilizes the transition voltage to output a power supply voltage to the outside. The power supply voltage is used to power the operational amplifier.

[0017] In one embodiment of the present invention, the power supply module includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a second chip, the input end of the second chip is connected to the first ground end of the second chip after being connected in series with the fifth capacitor, the clock end of the second chip is connected to the first ground end of the second chip, the first ground end of the second chip is also connected to the first analog ground, the positive phase output end of the second chip is connected to the second ground end of the second chip after being connected in series with the sixth capacitor, the seventh capacitor is connected in parallel with the sixth capacitor, the negative phase output end of the second chip is connected to the second ground end of the second chip after being connected in series with the eighth capacitor, the second ground end of the second chip is connected to the second analog ground, and the ninth capacitor is connected in parallel with the eighth capacitor, wherein the input end of the second chip is connected to the positive electrode of the third power supply voltage, the first ground end of the second chip is connected to the negative electrode of the third power supply voltage, the positive phase output end of the second chip is the positive electrode of the transition voltage, and the negative phase output end of the second chip is the negative electrode of the transition voltage.

[0018] In one embodiment of the present invention, the voltage stabilizing module includes a first voltage stabilizer, a second voltage stabilizer, a tenth capacitor, an eleventh capacitor, a twelfth capacitor and a thirteenth capacitor, the output of the first voltage stabilizer is connected to the ground terminal of the first voltage stabilizer via the tenth capacitor connected in series, the eleventh capacitor is connected in parallel with the tenth capacitor, the ground terminal of the first voltage stabilizer is connected to the second analog ground, the output terminal of the second voltage stabilizer is connected to the ground terminal of the second voltage stabilizer via the twelfth capacitor connected in series, the thirteenth capacitor is connected in parallel with the twelfth capacitor, and the ground terminal of the second voltage stabilizer is connected to the second analog ground, wherein the input terminal of the first voltage stabilizer is connected to the positive electrode of the transition voltage, the output terminal of the first voltage stabilizer is the positive electrode of the power supply voltage, the input terminal of the second voltage stabilizer is the negative electrode of the transition voltage, and the output terminal of the second voltage stabilizer is the negative electrode of the power supply voltage.

[0019] The present application provides a MOS tube test circuit, which includes a trigger module, a sampling module and an amplification module. The driving signal generated by the trigger module controls the working state of the sampling module through the driving signal. When the sampling module is enabled and started, the MOS tube to be tested is sampled through multiple sampling resistors inside the sampling module to obtain a sampling voltage; the sampling voltage is amplified by the amplification module to obtain a target voltage. The present application samples and amplifies the parameters of the MOS tube by means of multiple sampling resistors, which not only avoids dependence on current probes, reduces test costs, but also improves the precision and accuracy of testing MOS tubes.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present invention, and together with the specification, are used to explain the principles of the present invention. Obviously, the drawings described below are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0022] Figure 1 is a block diagram of a MOS tube test circuit shown in an exemplary embodiment of the present invention;

[0023] Figure 2 is a specific structural diagram of a MOS tube test circuit shown in an exemplary embodiment of the present invention;

[0024] Figure 3 is a schematic diagram of a current flow direction of a voltage sampling unit shown in an exemplary embodiment of the present invention;

[0025] Figure 4 It is a specific structural diagram of a power supply module and a voltage stabilizing module shown in an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

[0027] It should be noted that the illustrations provided in the following embodiments are only used to illustrate the basic concept of the present invention in a schematic manner, and thus the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0028] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it is obvious to those skilled in the art that the embodiments of the present invention can be implemented without these specific details. In other embodiments, well-known structures and devices are shown in the form of block diagrams rather than in detail to avoid making the embodiments of the present invention difficult to understand.

[0029] With the rapid development of electronic devices, Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is an important component in electronic devices, and the performance test of Metal-Oxide-Semiconductor Field-Effect Transistor is particularly important. Metal-Oxide-Semiconductor Field-Effect Transistor is referred to as MOS tube. The traditional MOS tube test method usually uses a high-precision current probe for sampling to complete the test of MOS tube. On the one hand, during the test process, the current probe will resonate with the junction capacitance of the MOS tube. When the resonance is too large, the accuracy of the test result of the MOS tube is reduced. On the other hand, the price of the current probe is expensive, which increases the test cost.

[0030] See also Figure 1 , Figure 1 It is a block diagram of a MOS tube test circuit shown in an exemplary embodiment of the present invention.

[0031] like Figure 1 As shown, in an exemplary embodiment, a MOS tube test circuit includes:

[0032] The trigger module is connected to the first power supply voltage V1 and the pulse signal K CP The first power supply voltage V1 provides working power for the trigger module, so that the trigger module is triggered according to the pulse signal K CP Generate driving signal K D ;

[0033] Sampling module, connected to the second power supply voltage V2, drive signal K D The second power supply voltage V2 provides working power for the sampling module, and the driving signal K DControl the working state of the sampling module. When the sampling module is enabled, the MOS tube to be tested is sampled through multiple sampling resistors inside the sampling module to obtain a sampling voltage V0;

[0034] The amplification module receives the sampling voltage V0 and amplifies the sampling voltage V0 to obtain the target voltage V T .

[0035] See also Figure 2 , Figure 2 It is a specific structural diagram of a MOS tube test circuit shown in an exemplary embodiment of the present invention.

[0036] In detail, Figure 2 As shown, the trigger module includes a first input interface H1, a first resistor R1, a second resistor R2, a third resistor R3, a first capacitor C1, a second capacitor C2, a third capacitor C3 and a first chip U1. The first end of the first input interface H1 is connected to the first input end of the first chip U1 via the first resistor R1 connected in series. The second end of the first input port is connected to the first end of the first capacitor C1. The first end of the first capacitor C1 is also connected to the first analog ground end. The first input end of the first chip U1 is also connected to the second end of the first capacitor C1. The ground end of the first chip U1 is connected to the first end of the first capacitor C1. The power supply end of the chip U1 is connected to the ground end of the first chip U1 through the second capacitor C2 connected in series, the first output end of the first chip U1 is connected to the first end of the third resistor R3 through the second resistor R2 connected in series, the second end of the third resistor R3 is also connected to the first end of the first capacitor C1, the third capacitor C3 and the third resistor R3 are connected in parallel, wherein the power supply end of the first chip U1 is connected to the positive electrode V1+ of the first power supply voltage, the second end of the first input interface H1 is connected to the negative electrode V1- of the first power supply voltage, the first end of the first input interface H1 is connected to the pulse signal, and the first end of the third resistor R3 outputs the driving signal K to the outside. D .

[0037] In detail, the sampling module includes a current sampling unit and a voltage sampling unit. The current sampling unit receives the MOS tube to be measured, a second power supply voltage and a driving signal. The second power supply voltage provides a working power supply for the current sampling unit. Under the control of the driving signal, the current sampling unit samples the MOS tube to be measured to obtain a sampling current; the voltage sampling unit is connected in series in the current sampling unit, and performs non-inductive current-voltage conversion on the sampling current through multiple sampling resistors to obtain a sampling voltage.

[0038] In more detail, Figure 2As shown, the current sampling unit includes a second input interface H2, a fuse F1, a fourth resistor R4, a fifth resistor R5, a switch tube Q1, a first inductor L1 and a fourth capacitor C4. The first end of the fuse F1 is connected to the second analog ground via the fourth capacitor C4 connected in series, the first end of the fifth resistor R5 is connected to the second analog ground, the first end of the fuse F1 is also connected to the first end of the first inductor L1, the first end of the first inductor L1 is also connected to the second end of the second input interface H2, the second end of the first inductor L1 is connected to the third end of the second input interface H2, the first end of the second input interface H2 is connected to the second input interface H2 via the fourth resistor R4 connected in series. 2, the third end of the second input interface H2 is connected to the input end of the switch tube Q1, the output end of the switch tube Q1 is connected to the second end of the third resistor R3, wherein the second end of the fuse F1 is connected to the positive electrode V2+ of the second power supply voltage, the second end of the fifth resistor R5 is connected to the negative electrode V2- of the second power supply voltage, the first end of the second input interface H2 is connected to the gate of the MOS tube to be measured, the second end of the second input interface H2 is connected to the drain of the MOS tube to be measured, the third end of the second input interface H2 is connected to the source of the MOS tube to be measured, the output end of the switch tube is connected to the second analog ground after passing through the voltage sampling unit, and the output end of the switch tube outputs the sampling current to the outside.

[0039] It should be emphasized that the switch tube Q1 can be a NOMS tube or a PMOS tube, such as Figure 2 As shown, the switch tube is an NMOS tube, and can also be changed to a PMOS tube, which is not limited here. In actual situations, the first analog ground and the second analog ground select corresponding values ​​according to actual situations.

[0040] In more detail, Figure 2 As shown, the voltage sampling unit includes 2N sampling resistors, the first end of the i-th sampling resistor is connected to the output end of the switch tube, the second end of the i-th sampling resistor is connected to the second analog ground, and the first end of the i-th sampling resistor outputs the sampling voltage to the outside, wherein i and N are positive integers, and 1≤i≤2N. Specifically, the voltage sampling unit includes 4 sampling resistors, namely: a first sampling resistor R6, a second sampling resistor R7, a third sampling resistor R8 and a fourth sampling resistor R9, the first end of the first sampling resistor R6 is connected to the first end of the second sampling resistor R7, the second end of the first sampling resistor R6 is connected to the second end of the second sampling resistor R7, the second end of the first sampling resistor R6 is also connected to the second analog ground, the third sampling resistor R8 is connected in parallel with the first sampling resistor R6, and the fourth sampling resistor R9 is connected in parallel with the first sampling resistor R6, wherein the first end of the first sampling resistor R6 is connected to the output end of the switch tube Q1, and the first end of the first sampling resistor R6 outputs the sampling voltage V0 to the outside.

[0041] See also Figure 3 , Figure 3is a schematic diagram showing the current flow direction of a voltage sampling unit according to an exemplary embodiment of the present invention.

[0042] In more detail, 2N sampling resistors are arranged on the circuit board without inductance, and N sampling resistors are arranged on the front and back of the circuit board respectively. The flow direction of the sampling current on the N sampling resistors on the front of the circuit board is a first direction, and the flow direction of the sampling current on the N sampling resistors on the back of the circuit board is a second direction, and the first direction is opposite to the second direction. It should be noted that, if Figure 3 As shown, when N is 2, four sampling resistors are non-inductively arranged on the circuit board, two sampling resistors are arranged on the front and back of the circuit board respectively, and the positions of the input end and the output end of the sampling current on the front of the circuit board are opposite to the positions of the input end and the output end of the sampling current on the back of the circuit board, that is, the flow direction of the sampling current on the N sampling resistors on the front of the circuit board is a first direction, and the flow direction of the sampling current on the N sampling resistors on the back of the circuit board is a second direction, and the first direction is opposite to the second direction, so as to offset the coupling force generated by the sampling current flowing through multiple sampling resistors to avoid affecting the test results.

[0043] In detail, Figure 2 As shown, the amplification module includes an operational amplifier AMP, a sixth resistor R10, a seventh resistor R11 and an eighth resistor R12, the inverting input terminal of the operational amplifier AMP is connected to the second analog ground via the sixth resistor R10 connected in series, the inverting input terminal of the operational amplifier AMP is also connected to the output terminal of the operational amplifier AMP via the seventh resistor R11 connected in series, the output terminal of the operational amplifier AMP is connected to the second analog ground via the eighth resistor R12 connected in series, wherein the non-inverting input terminal of the operational amplifier AMP is connected to the sampling voltage V0, and the output terminal of the operational amplifier AMP outputs the target voltage V T .

[0044] See also Figure 4 , Figure 4 It is a specific structural diagram of a power supply module and a voltage stabilizing module shown in an exemplary embodiment of the present invention.

[0045] In detail, Figure 4 As shown, the MOS tube test circuit also includes a power supply module and a voltage stabilizing module. The power supply module is connected to the third power supply voltage, and filters and steps down the third power supply voltage to obtain a transition voltage. The voltage stabilizing module is connected to the transition voltage, and stabilizes the transition voltage to output a power supply voltage to the outside. The power supply voltage is used to power the operational amplifier.

[0046] In more detail, Figure 4As shown, the power supply module includes a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a second chip U2. The input end of the second chip U2 is connected to the first analog ground of the second chip U2 after the fifth capacitor C5 is connected in series. The clock end of the second chip U2 is connected to the first ground end of the second chip U2. The first ground end of the second chip U2 is also connected to the same potential. The positive phase output end of the second chip U2 is connected to the second ground end of the second chip U2 after the sixth capacitor C6 is connected in series. The seventh capacitor C7 In parallel with the sixth capacitor C6, the inverting output terminal of the second chip U2 is connected to the second ground terminal of the second chip U2 via the eighth capacitor C8 connected in series, the second ground terminal of the second chip U2 is connected to the second analog ground, the ninth capacitor C9 is connected to the eighth capacitor C8 in parallel, wherein the input terminal of the second chip U2 is connected to the positive electrode V3+ of the third power supply voltage, the first ground terminal of the second chip U2 is connected to the negative electrode V3- of the third power supply voltage, the positive phase output terminal of the second chip U2 is the positive electrode of the transition voltage, and the inverting output terminal of the second chip U2 is the negative electrode of the transition voltage.

[0047] In more detail, Figure 4 As shown, the voltage stabilizing module includes a first voltage stabilizer U3, a second voltage stabilizer U4, a tenth capacitor C10, an eleventh capacitor C11, a twelfth capacitor C12 and a thirteenth capacitor C13. The output of the first voltage stabilizer U3 is connected to the ground terminal of the first voltage stabilizer U3 via the tenth capacitor C10 connected in series. The eleventh capacitor C11 is connected in parallel with the tenth capacitor C10. The ground terminal of the first voltage stabilizer U3 is connected to the second analog ground. The output terminal of the second voltage stabilizer U4 is connected to the ground terminal of the second voltage stabilizer U4 via the twelfth capacitor C12 connected in series. The thirteenth capacitor C13 is connected in parallel with the twelfth capacitor C12. The ground terminal of the second voltage stabilizer U4 is connected to the second analog ground. The input terminal of the first voltage stabilizer U3 is connected to the positive electrode of the transition voltage, the output terminal of the first voltage stabilizer U3 is the positive electrode of the power supply voltage, the input terminal of the second voltage stabilizer U4 is connected to the negative electrode of the transition voltage, and the output terminal of the second voltage stabilizer U4 is the negative electrode of the power supply voltage V.

[0048] See also Figures 1 to 4 The working principle of a MOS tube test circuit provided in this application is as follows:

[0049] The power supply module is connected to the third voltage V3, and the third voltage V3 is stepped down and filtered by the power supply module to obtain a transition voltage, and the transition voltage is input into the voltage stabilizing module, and the transition voltage is stabilized by the voltage stabilizing module to obtain a power supply voltage, the positive electrode of the power supply voltage is connected to the positive power input terminal of the operational amplifier AMP, and the negative electrode of the power supply voltage is connected to the negative power input terminal of the operational amplifier AMP, and the operational amplifier AMP is powered by the supply voltage.

[0050] Pulse signal K CP Through the first input interface, the trigger module is triggered according to the pulse signal K CPGenerate driving signal K D The drive signal K can be adjusted by the second resistor R2 according to the actual usage. D The waveform of the driving signal K D The switch tube Q1 is turned on, and the first inductor L1 performs current detection on the gate and drain of the MOS tube to be tested to obtain a sampling current. The sampling current flows through the switch tube Q1 and then flows into the voltage sampling unit. The four sampling resistors in the voltage sampling unit perform non-inductive current-voltage conversion on the sampling current to obtain a sampling voltage V0. The amplification module is connected to the sampling voltage V0 and amplifies the sampling voltage V0 to obtain a target voltage V T , and improve the testing precision and accuracy of MOS tubes.

[0051] The present application provides a MOS tube test circuit, which includes a trigger module, a sampling module and an amplification module. The driving signal generated by the trigger module controls the working state of the sampling module through the driving signal. When the sampling module is enabled and started, the MOS tube to be tested is sampled through multiple sampling resistors inside the sampling module to obtain a sampling voltage; the sampling voltage is amplified by the amplification module to obtain a target voltage. The present application samples and amplifies the parameters of the MOS tube by means of multiple sampling resistors, which not only avoids dependence on current probes, reduces test costs, but also improves the precision and accuracy of testing MOS tubes.

[0052] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A MOS tube test circuit, characterized in that: include: A trigger module, connected to a first power supply voltage and a pulse signal, wherein the first power supply voltage provides a working power supply for the trigger module, so that the trigger module generates a driving signal according to the pulse signal; A sampling module is connected to a second power supply voltage, the trigger module and the MOS tube to be tested, wherein the second power supply voltage provides a working power supply for the sampling module, and the working state of the sampling module is controlled by the driving signal. When the sampling module is enabled and started, the MOS tube to be tested is sampled through a plurality of sampling resistors inside the sampling module to obtain a sampling voltage; an amplification module, connected to the sampled voltage, amplifying the sampled voltage to obtain a target voltage; The trigger module includes a first input interface, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor and a first chip, wherein the first end of the first input interface is connected to the first input end of the first chip via the first resistor connected in series, the second end of the first input port is connected to the first end of the first capacitor, the first end of the first capacitor is also connected to the first analog ground end, the first input end of the first chip is also connected to the second end of the first capacitor, the ground end of the first chip is connected to the first end of the first capacitor, the power supply end of the first chip is connected to the ground end of the first chip via the second capacitor connected in series, the first output end of the first chip is connected to the first end of the third resistor via the second resistor connected in series, the second end of the third resistor is also connected to the first end of the first capacitor, the third capacitor is connected in parallel with the third resistor, wherein the power supply end of the first chip is connected to the positive electrode of the first power supply voltage, the second end of the first input interface is connected to the negative electrode of the first power supply voltage, the first end of the first input interface is connected to the pulse signal, and the first end of the third resistor outputs the driving signal to the outside; The sampling module includes a current sampling unit and a voltage sampling unit. The current sampling unit is connected to the MOS tube to be tested, the second power supply voltage and the trigger module. The second power supply voltage provides a working power supply for the current sampling unit. Under the control of the driving signal, the current sampling unit samples the MOS tube to be tested to obtain a sampling current. The voltage sampling unit is connected in series to the current sampling unit, and performs non-inductive current-voltage conversion on the sampling current through a plurality of sampling resistors to obtain the sampling voltage. The current sampling unit includes a second input interface, a fuse, a fourth resistor, a fifth resistor, a switch tube, a first inductor and a fourth capacitor. The first end of the fuse is connected to the second analog ground via the fourth capacitor connected in series, the first end of the fifth resistor is connected to the second analog ground, the first end of the fuse is also connected to the first end of the first inductor, the first end of the first inductor is also connected to the second end of the second input interface, the second end of the first inductor is connected to the third end of the second input interface, the first end of the second input interface is connected to the third end of the second input interface via the fourth resistor connected in series, the third end of the second input interface is connected to the input end of the switch tube, and the output end of the switch tube is connected to the second end of the third resistor, wherein the second end of the fuse is connected to the positive electrode of the second power supply voltage, the second end of the fifth resistor is connected to the negative electrode of the second power supply voltage, the first end of the second input interface is connected to the gate of the MOS tube to be tested, the second end of the second input interface is connected to the drain of the MOS tube to be tested, the third end of the second input interface is connected to the source of the MOS tube to be tested, and the output end of the switch tube is connected to the voltage sampling unit.

2. The MOS tube test circuit according to claim 1, characterized in that: The voltage sampling unit includes 2N sampling resistors, the first end of the i-th sampling resistor is connected to the output end of the switch tube, the second end of the i-th sampling resistor is connected to the second analog ground, and the first end of the i-th sampling resistor outputs the sampling voltage to the outside, wherein i and N are positive integers, 1≤i≤2N.

3. The MOS tube test circuit according to claim 2, characterized in that: 2N sampling resistors are non-inductively arranged on a circuit board, and N sampling resistors are respectively arranged on the front and back of the circuit board. The flow direction of the sampling current on the N sampling resistors on the front of the circuit board is a first direction, and the flow direction of the sampling current on the N sampling resistors on the back of the circuit board is a second direction, and the first direction is opposite to the second direction.

4. The MOS tube test circuit according to claim 1, characterized in that: The amplification module includes an operational amplifier, a sixth resistor, a seventh resistor and an eighth resistor. The inverting input terminal of the operational amplifier is connected to the second analog ground via the sixth resistor connected in series. The inverting input terminal of the operational amplifier is also connected to the output terminal of the operational amplifier via the seventh resistor connected in series. The output terminal of the operational amplifier is connected to the second analog ground via the eighth resistor connected in series. The non-inverting input terminal of the operational amplifier is connected to the sampling voltage, and the output terminal of the operational amplifier outputs the target voltage to the outside.

5. The MOS tube test circuit according to claim 4, characterized in that: The MOS tube test circuit also includes a power supply module and a voltage stabilizing module. The power supply module is connected to a third power supply voltage, and filters and reduces the third power supply voltage to obtain a transition voltage. The voltage stabilizing module is connected to the transition voltage, and stabilizes the transition voltage to output a power supply voltage to the outside. The power supply voltage is used to power the operational amplifier.

6. The MOS tube test circuit according to claim 5, characterized in that: The power supply module includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor and a second chip, the input end of the second chip is connected to the first ground end of the second chip after being connected in series with the fifth capacitor, the clock end of the second chip is connected to the first ground end of the second chip, the first ground end of the second chip is also connected to the first analog ground, the positive phase output end of the second chip is connected to the second ground end of the second chip after being connected in series with the sixth capacitor, the seventh capacitor is connected in parallel with the sixth capacitor, the negative phase output end of the second chip is connected to the second ground end of the second chip after being connected in series with the eighth capacitor, the second ground end of the second chip is connected to the second analog ground, and the ninth capacitor is connected in parallel with the eighth capacitor, wherein the input end of the second chip is connected to the positive electrode of the third power supply voltage, the first ground end of the second chip is connected to the negative electrode of the third power supply voltage, the positive phase output end of the second chip is the positive electrode of the transition voltage, and the negative phase output end of the second chip is the negative electrode of the transition voltage.

7. The MOS tube test circuit according to claim 5, characterized in that: The voltage stabilizing module includes a first voltage stabilizer, a second voltage stabilizer, a tenth capacitor, an eleventh capacitor, a twelfth capacitor and a thirteenth capacitor. The output of the first voltage stabilizer is connected to the ground terminal of the first voltage stabilizer via the tenth capacitor connected in series, the eleventh capacitor is connected in parallel with the tenth capacitor, the ground terminal of the first voltage stabilizer is connected to a second analog ground, the output terminal of the second voltage stabilizer is connected to the ground terminal of the second voltage stabilizer via the twelfth capacitor connected in series, the thirteenth capacitor is connected in parallel with the twelfth capacitor, and the ground terminal of the second voltage stabilizer is a second analog ground, wherein the input terminal of the first voltage stabilizer is connected to the positive electrode of the transition voltage, the output terminal of the first voltage stabilizer is the positive electrode of the power supply voltage, the input terminal of the second voltage stabilizer is connected to the negative electrode of the transition voltage, and the output terminal of the second voltage stabilizer is the negative electrode of the power supply voltage.

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