Three-transistor memory with buried gate and composite dielectric gate structure and its read and write method, storage and computing array
By adopting a three-transistor memory with buried gate and composite dielectric gate structure in the memory device, the problems of large area and low storage density of traditional SRAM and eDRAM devices are solved, and storage with small size, high dynamic range and strong weight retention capabilities are realized Effects, suitable for caching requirements in neural network algorithms.
Patent Information
- Application Number
- CN202411088060.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-09
- Publication Date
- 2025-01-03
- Estimated Expiration
- 2044-08-09
AI Technical Summary
In the prior art, the area of traditional SRAM single-bit data is large, resulting in low storage density, which is difficult to meet the needs of a large number of cache arrays in neural network algorithms, and the destructive readout and capacitance of eDRAM devices are small per unit area. Limits its application in memory devices and caches.
A three-transistor memory with buried gate and composite dielectric gate structure is adopted to store and read charge information through the charge coupling principle, and a shared gate is separated by a shallow trough isolation structure to form an electron write tube, an electron collecting tube and an electron readout The tube can achieve small size, high dynamic range and strong weight retention capabilities, with an area of up to 16F2.
It realizes high-density cache storage, reduces the device area, and is suitable for scenarios where a large number of cache arrays are needed. It also has the function of integrated storage and computing, improving energy efficiency ratio and integration.
Smart Images
Figure CN118629456B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a three-transistor memory with a buried gate and a composite dielectric gate structure, a read-out and write-in method thereof, and a memory-calculation array, and belongs to the field of semiconductor technology. Background Art
[0002] As the cornerstone of the computer field, the von Neumann architecture has made great contributions to the development of this field. However, its architectural feature of separate storage units and computing units causes great delays and power waste in the interaction between storage and computing units when processing a type of algorithm represented by neural network algorithms and CT algorithms, because the network weights need to be called repeatedly. At the same time, a series of algorithms represented by neural network algorithms require a large number of matrix-vector multiplication operations, and the scale of traditional multipliers is often tens of thousands of transistors, which greatly affects the energy efficiency and integration of traditional computing when processing such algorithms.
[0003] In order to overcome this limitation, people have proposed a memory-computing integrated device and an in-memory computing solution. The characteristic of this solution is that it can realize local calculation of weights in the memory-computing array composed of memory-computing devices, effectively solving the problem of memory wall. A memory-computing integrated chip that can realize general neural network calculation usually needs to deploy multiple arrays on the chip, and caches matching the scale of neural networks need to be deployed between these arrays to store the flow of interaction between layers. The area of single-bit data of SRAM used is usually 120-150F. 2 , the storage density is low; as the scale of neural networks increases, the low storage density cache array will greatly increase the area resources occupied in the chip. For the above reasons, today's storage and computing field requires both high-performance storage and computing devices and higher-density on-chip cache.
[0004] The properties of eDRAM devices in the prior art determine that they can be used as storage and computing devices, and can also replace on-chip SRAM as a cache. However, the current commercial 1C1T-DRAM process is complex, and due to its destructive readout characteristics, it is difficult to use it as a storage and computing device; although common eDRAM devices have the characteristics of non-destructive readout, the device structure uses a gate capacitor with a small unit area capacitance to store device weights, which requires sacrificing area in exchange for weight maintenance capabilities, and the area is often 40F. 2 The above is not suitable for scenarios that require a large cache array. Summary of the invention
[0005] In order to solve the existing problems, the present invention provides a three-transistor memory with a buried gate and a composite dielectric gate structure to replace the SRAM device in the on-chip cache, save the cache area, and can also be used directly as a storage device. This application adds a buried gate structure to form a three-transistor structure based on the composite dielectric gate dual-transistor photosensitive detector disclosed in the Chinese invention patent with publication number CN102938409A. The buried gate structure controls the erase weight to the storage device, and uses the charge coupling principle to realize the storage and readout of charge information. It inherits the characteristics of the composite dielectric gate dual-transistor photosensitive detector with small size, high dynamic range, and strong weight retention ability. Its area can be as small as 16 F 2 , thus making it possible for applications in some scenarios that require a large number of cache arrays.
[0006] The first object of the present application is to provide a three-transistor memory with a buried gate and a composite dielectric gate structure, the memory is composed of an electron write tube, an electron collection tube and an electron readout tube, and its structure includes from bottom to top: a substrate, a bottom dielectric layer and a gate structure, the gate structure includes from bottom to top a composite dielectric gate, a top dielectric layer and a first control gate, under the gate structure, two electron tubes with a common gate are separated by a shallow trench isolation structure, namely an electron readout tube and an electron collection tube; a buried gate structure is arranged inside the substrate on one side of the electron collection tube, a write drain terminal is arranged above the inside of the substrate on the side where the buried gate structure is arranged, and the buried gate structure and the write drain terminal constitute the electron write tube.
[0007] Optionally, the electron readout tube is used to read out the electron quantity information in the electron collecting tube, and a readout source terminal and a readout drain terminal are respectively provided on the substrate and on both sides of the gate structure; the electron collecting tube is used to collect electrons written from the write source terminal of the electron writing tube, and no source terminal and drain terminal are provided in the substrate; the other side of the buried gate structure is the collection area below the electron collecting tube, and also serves as the write source terminal of the electron writing tube.
[0008] Optionally, the buried gate structure consists of a buried gate dielectric layer and a second control gate.
[0009] Optionally, the buried gate dielectric layer is silicon dioxide or silicon nitride, and the second control gate is polysilicon.
[0010] The second object of the present application is to provide a storage and computing array, which is composed of m×n three-transistor memories mentioned above, the write drain and write source of the three-transistor memories in the same column are respectively connected to form a bit line and a source line, the second control gates of the three-transistor memories in the same row are connected to form a write word line, and the first control gates of the three-transistor memories in the same row are connected to form a read word line.
[0011] The third object of the present application is to provide a storage and computing array realized by a common buried gate connection relationship, wherein the basic storage and computing unit of the storage and computing array is composed of two of the above-mentioned three-transistor memories, and the two three-transistor memories are respectively recorded as device one and device two. A common buried gate is used between device one and device two, and shallow trench isolation is provided in other directions to avoid crosstalk. The read drain terminal of device one serves as the write drain terminal of device two, and the read drain terminal of device two serves as the write drain terminal of device one.
[0012] Optionally, the basic storage and computing unit has two first control gates, a common second control gate, two read source terminals and two respectively common drain terminals; the basic storage and computing units constitute a storage and computing array of size m×n, the second control gates of the basic storage and computing units in the same row are connected to form a write word line WWL, the two first control gates of the basic storage and computing units in the same row are respectively connected to form two read word lines RWL1 and RWL2, the source terminals of the basic storage and computing units in the same column are all connected to form a source line SL, and the two drain terminals in the same column are respectively connected to form two bit lines BL1 and BL2.
[0013] The fourth object of the present application is to provide a reading and writing method for the above-mentioned three-transistor memory, wherein the method applies a positive bias voltage between the first control gate and the substrate to form a depletion region in the substrate below the electron collecting tube, and applies voltage through the drain end of the electron writing tube to regulate the potential barrier to charge or extract electrons into or out of the depletion region, thereby affecting the threshold voltage of the electron reading tube.
[0014] The beneficial effects of the present invention are:
[0015] The memory provided in the present application utilizes the charge coupling mechanism brought about by the common composite dielectric gate structure to perform weight judgment, and can be used as both a storage device and a storage and computing device. It has the characteristics of small size, high dynamic range, and strong weight retention capability. The memory can realize the interconnection relationship of co-write transistors, forming a storage array while further reducing the device area. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0017] Figure 1 is a structural diagram of a three-transistor memory with a buried gate and a composite dielectric gate structure provided in the first embodiment of the present invention;
[0018] Figure 2This is a topological structure diagram of a three-transistor memory with a buried gate and a composite dielectric gate structure provided in the first embodiment of the present invention;
[0019] Figure 3 It is a cross-sectional view from the electron writing tube to the electron collecting tube when writing electrons into the electron collecting tube of the three-transistor memory with buried gate and composite dielectric gate structure provided by the first embodiment of the present invention;
[0020] Figure 4 is a structural diagram of the connection relationship of the devices of the common buried gate described in the second embodiment of the present invention;
[0021] Figure 5 It is a schematic diagram of a storage or storage-computation array implemented according to a common buried gate connection relationship described in the second embodiment of the present invention;
[0022] Figure 6 This is a structural diagram of a 4×4 storage or storage-computation array implemented by the common buried gate connection relationship described in the second embodiment of the present invention;
[0023] Figure 7 It is a writing timing diagram showing the writing of array weights by the storage or storage-computation array described in the second embodiment of the present invention. DETAILED DESCRIPTION
[0024] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.
[0025] Embodiment 1
[0026] This embodiment provides a three-transistor memory with a buried gate and a composite dielectric gate structure. Figure 1 The three-transistor memory is composed of an electron writing tube, an electron collecting tube and an electron reading tube. The structure includes from bottom to top: a substrate, a bottom dielectric layer and a gate structure. The gate structure includes from bottom to top a composite dielectric gate, a top dielectric layer and a first control gate (the side walls surrounding the gate structure are not in the Figure 1 As shown in the figure, under the gate structure, a shallow trench isolation structure is used to separate two electron tubes with a common gate, namely an electron readout tube and an electron collecting tube; a buried gate structure is arranged inside the substrate on one side of the electron collecting tube, and a write drain terminal is arranged above the inside of the substrate on the side where the buried gate structure is arranged, and the buried gate structure and the write drain terminal constitute an electron writing tube.
[0027] refer to Figure 2 The corresponding topological structure diagram is shown in Figure 1. The electronic writing tube and the electronic reading tube are in Figure 2 The diagrams in the figure are all transistor patterns. Since the electron collector has no source and drain terminals in the substrate, Figure 2 The middle is the capacitor pattern, and the collection area of the electron collection tube is Figure 2The X node in the figure, the capacitance pattern below the X node is essentially the depletion region capacitance formed after applying a gate-substrate bias between the first control gate and the substrate, the two capacitance patterns above the X node represent the bottom dielectric layer capacitance and the top dielectric layer capacitance respectively, and the Y node is a composite dielectric gate.
[0028] Figure 3 The schematic cross-sectional view from the electron writing tube to the electron collecting tube when the three-transistor memory provided by the present invention writes electrons into the electron collecting tube shows that the electrons flow from the writing drain end to the collecting area of the electron collecting tube.
[0029] When in standby mode, a negative voltage, such as -3V, is first applied to the substrate of the semiconductor device of the present invention, 0V is applied to the first control gate, 0V is applied to all source and drain terminals, and 0V is applied to the second control gate. At this time, a large depletion region is formed in the substrate area below the electron collection tube of the semiconductor device, and the depletion region is used to collect electrons, also called the collection region.
[0030] When writing, a positive voltage, such as 3V, is applied to the second control gate to turn on the electron writing tube, and -3V or 0V is applied to the writing drain terminal. If -3V is applied to the drain terminal, since the electron writing tube is turned on, the writing drain terminal to the depletion region below the electron collecting tube can be regarded as short-circuited together, and electrons will flow from the writing drain terminal to the depletion region through the buried gate structure, such as Figure 3 As shown, until the depletion region is full of wells, the potential in the depletion region will be close to -3V, and then the voltage applied to the second control gate will be changed to 0V to turn off the electron write tube, and the writing is completed; if 0V is added to the drain end, since the electron write tube is turned on, electrons will flow from the depletion region to the write drain end until the depletion region is empty. At this time, the potential in the depletion region will be close to 0V, and then the voltage applied to the second control gate will be changed to 0V to turn off the electron write tube, and the writing is completed.
[0031] During readout, a positive voltage, such as 3V, is applied to the first control gate, 0.5V is applied to the readout drain, and 0V is applied to the readout source. If the depletion region of the electron collection tube is a full well, the potential is -3V. At this time, the potential on the composite dielectric gate, that is, the Y node potential, will be smaller due to the voltage division of the bottom dielectric layer capacitance and the top dielectric layer capacitance. For example, when the ratio of the bottom dielectric layer capacitance to the top dielectric layer capacitance is 1:1, the Y node potential is 0V. At this time, the electron readout tube cannot be turned on, and there is basically no current between the source and drain ends. If the depletion region of the write collection tube is an empty well, the potential is 0V. At this time, the Y node potential will be larger due to the voltage division of the bottom dielectric layer capacitance and the first top dielectric layer capacitance. For example, when the ratio of the bottom dielectric layer capacitance to the top dielectric layer capacitance is 1:1, the Y node potential is 1.5V, the electron readout tube is turned on, and there is a large current between the readout source and the readout drain. The current size of the current between the source and the drain can be used to determine the weight previously written into the device.
[0032] It should be mentioned that the write voltage of the write drain is not limited to -3V and 0V, it can be set to multiple values to achieve high-bit width storage. For example, if you want to store a 2-bit weight, you can set the write voltage of the write drain to 0V, -1V, -2V, -3V. Correspondingly, the potential of the Y node during reading is 1.5V, 1V, 0.5V, and 0V, respectively. Obviously, the threshold voltage of the entire three-transistor memory is proportional to the write voltage of the write drain.
[0033] In actual application scenarios, the three-transistor memory with buried gate and composite dielectric gate structure provided in this embodiment is configured as a memory in the form of an array. For example, in an m×n array, the write drain and write source of the three-transistor memories in the same column are respectively connected to form a bit line and a source line, the second control gates of the three-transistor memories in the same row are connected to form a write word line, and the first control gates of the three-transistor memories in the same row are connected to form a read word line.
[0034] Embodiment 2
[0035] This embodiment provides a solution for the three-transistor memory to form a memory array. The basic memory cell of the memory array is composed of two three-transistor memories provided in the first embodiment, such as Figure 4 As shown, the two three-transistor memories are connected in parallel in opposite directions head to tail. The two three-transistor memories are respectively called device one and device two. Device one and device two share a buried gate, and shallow trench isolation is provided in other directions to avoid crosstalk. The read drain terminal of device one serves as the write drain terminal of device two, and the read drain terminal of device two serves as the write drain terminal of device one. This connection method saves the area of the write drain terminal of each device.
[0036] The two devices connected in this way are regarded as a basic storage unit. A basic storage unit has two first control gates, a shared second control gate, two read source terminals and two shared write drain terminals or read drain terminals. The basic storage units can be connected to form an m×n array in the following way: Figure 5 As shown, the second control gates of the basic storage cells in the same row are connected to form a write word line WWL (Write Word Line); the two first control gates of the basic storage cells in the same row are connected respectively to form two read word lines RWL1 and RWL2 (Read Word Line); the source ends of the basic storage cells in the same column are all connected to form a source line SL (Source Line), which is not shown in the figure; the two drain ends in the same column are connected respectively to form two bit lines BL1 and BL2 (Bit Line). Figure 6 This is a structural diagram of a 4×4 storage array, in which the devices in the second and third rows are isolated by shallow trench isolation.
[0037] The following is a detailed description of the array's operating timing, please refer to Figure 7 :
[0038] In standby mode, the substrate is connected to -3V and all other ports are connected to 0V;
[0039] When writing, first set the WWL of the first line <1> Raise to 3V, so that the electronic write tubes of the 2×m three-transistor memories in the first row are turned on, and at the same time control the potential of BL1<1:m> and BL2<1:m>, a total of 2×m BLs, to 0V or -3V, which is determined by the weight to be written into the device. BL1<1:m> is responsible for controlling the writing of the weight to the device 1 of the first row of basic storage units, and BL2<1:m> is responsible for controlling the writing of the weight to the device 2 of the first row of basic storage units. After completion, close WWL <1> , and turn on WWL <2> The second row is written, and the weights of the 2m×n three-transistor memories in the entire array are written after n rounds of writing.
[0040] When reading, keep WWL<1:n> off, add 0.5V to both BL1<1:m> and BL2<1:m>, and turn on RWL1 <1> and RWL2 <1> At this time, the weight results of 2m three-transistor memories can be read out by the current on BL1<1:m> and BL2<1:m>. After the readout is completed, RWL1 is closed. <1> and RWL2 <1> , and turn on RWL1 <2> and RWL2 <2> , read out row by row in sequence, and after n rounds of readout, the weight readout of the entire array of 2m×n three-transistor memories is completed.
[0041] Embodiment 3
[0042] This embodiment provides a solution for forming a storage and calculation array with the three-transistor memory. The basic storage and calculation unit of the storage and calculation array is also composed of the three-transistor memories provided in the two embodiments. Figure 4 As shown, the two three-transistor memories are connected in parallel in opposite directions head to tail. The two three-transistor memories are respectively called device one and device two. Device one and device two share a buried gate, and shallow trench isolation is provided in other directions to avoid crosstalk. The read drain terminal of device one serves as the write drain terminal of device two, and the read drain terminal of device two serves as the write drain terminal of device one. This connection method saves the area of the write drain terminal of each device.
[0043] The two devices connected in this way are regarded as a basic storage unit. A basic storage unit has two first control gates, a shared second control gate, two read source terminals and two shared write drain terminals or read drain terminals. The basic storage units can be connected to form an array of size m×n in the following way: Figure 5As shown, the second control gates of the basic storage and computing units in the same row are connected to form a write word line WWL; the two first control gates of the basic storage and computing units in the same row are connected respectively to form two read word lines RWL1 and RWL2; the source ends of the basic storage and computing units in the same column are all connected to form a source line SL, which is not shown in the figure; the two drain ends in the same column are connected respectively to form two bit lines BL1 and BL2.
[0044] The following describes its working sequence when used as a storage and calculation array:
[0045] In standby mode, the substrate is connected to -3V and all other ports are connected to 0V;
[0046] When writing, first set the WWL of the first line <1> Raise to 3V, so that the electronic write tubes of the 2×m three-transistor memories in the first row are turned on, and at the same time control the potential of BL1<1:m> and BL2<1:m>, a total of 2×m BLs, to 0V or -3V, which is determined by the weight to be written into the device. BL1<1:m> is responsible for controlling the writing of the weight to the device 1 of the first row of basic storage units, and BL2<1:m> is responsible for controlling the writing of the weight to the device 2 of the first row of basic storage units. After completion, close WWL <1> , and turn on WWL <2> The second row is written, and the weights of the 2m×n three-transistor memories in the entire array are written after n rounds of writing.
[0047] During inference, keep WWL<1:n> closed, add 0.5V to BL1<1:m> and BL2<1:m>, select several rows in RWL<1:n> according to the excitation vector, and according to Kirchhoff's law, the current value on each bit line in BL1<1:m> and BL2<1:m> is the result of multiplying and accumulating the weights of all three-transistor memories on the bit line and the corresponding excitation. The 1×2m current accumulation results are the matrix-vector multiplication results of this inference.
[0048] Some steps in the embodiments of the present invention may be implemented using software, and the corresponding software program may be stored in a readable storage medium, such as a CD or a hard disk.
[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A three-transistor memory with a buried gate and a composite dielectric gate structure, characterized in that: The memory is composed of an electron writing tube, an electron collecting tube and an electron reading tube, and its structure includes from bottom to top: a substrate, a bottom dielectric layer and a gate structure, the gate structure includes from bottom to top a composite dielectric gate, a top dielectric layer and a first control gate, and two electron tubes with a common gate are separated by a shallow trench isolation structure under the gate structure, which are an electron reading tube and an electron collecting tube; a buried gate structure is arranged inside the substrate on one side of the electron collecting tube, and a write drain terminal is arranged above the inside of the substrate on the side where the buried gate structure is arranged, and the buried gate structure and the write drain terminal constitute the electron writing tube; The electron readout tube is used to read out the electron quantity information in the electron collecting tube, and a readout source terminal and a readout drain terminal are respectively provided on the substrate and on both sides of the gate structure; the electron collecting tube is used to collect electrons written from the write source terminal of the electron writing tube, and no source terminal and drain terminal are provided in the substrate; the other side of the buried gate structure is the collection area below the electron collecting tube, and also serves as the write source terminal of the electron writing tube.
2. The three-transistor memory according to claim 1, characterized in that: The buried gate structure consists of a buried gate dielectric layer and a second control gate.
3. The three-transistor memory according to claim 2, characterized in that: The buried gate dielectric layer is made of silicon dioxide or silicon nitride, and the second control gate is made of polysilicon.
4. A storage and computing array, characterized in that: The storage and computing array is composed of m×n three-transistor memories described in any one of claims 1 to 3, the write drain and write source of the three-transistor memories in the same column are respectively connected to form a bit line and a source line, the second control gates of the three-transistor memories in the same row are connected to form a write word line, and the first control gates of the three-transistor memories in the same row are connected to form a read word line.
5. A storage and computing array implemented by a common buried gate connection relationship, characterized in that: The basic storage and computing unit of the storage and computing array is composed of two three-transistor memories described in any one of claims 1 to 3, and the two three-transistor memories are respectively recorded as device one and device two. Device one and device two share a buried gate, and shallow trench isolation is provided in other directions to avoid crosstalk. The read drain terminal of device one serves as the write drain terminal of device two, and the read drain terminal of device two serves as the write drain terminal of device one.
6. The storage and computing array according to claim 5, characterized in that: The basic storage and computing unit has two first control gates, a common second control gate, two read source terminals and two respectively common drain terminals; the basic storage and computing unit constitutes an m×n storage and computing array, the second control gates of the basic storage and computing units in the same row are connected to form a write word line WWL, the two first control gates of the basic storage and computing units in the same row are respectively connected to form two read word lines RWL1 and RWL2, the source terminals of the basic storage and computing units in the same column are all connected to form a source line SL, and the two drain terminals in the same column are respectively connected to form two bit lines BL1 and BL2.
7. A method for reading and writing a three-transistor memory according to any one of claims 1 to 3, characterized in that: The method adds a positive bias voltage between the first control grid and the substrate to form a depletion region in the substrate below the electron collecting tube, applies pressure to the drain end of the electron writing tube to adjust the potential barrier to charge or extract electrons into the depletion region, thereby affecting the threshold voltage of the electron reading tube.