Test fixture, test system and test method

Abstract

The present invention provides a test fixture, a test system and a test method, which relate to the field of electronic digital data processing. The test fixture comprises: a target number of first PCIE signal ports, a target number of second PCIE signal ports and a clock module; the first PCIE signal port corresponds to the second PCIE signal port one by one. The test fixture, the test system and the test method provided by the present invention can perform more accurate and efficient functional testing on the PCIE signal port in the electronic device, the test environment and the test operation are simpler, and the reliability during the test process is high. The test fixture provided by the present invention has a high degree of standardization, which can greatly reduce the design workload of the electronic device, can be widely applied to the functional testing of the PCIE signal ports of different electronic devices, has stronger reusability, and has a broader market application prospect.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic digital data processing, and in particular to a test fixture, a test system and a test method. Background Art

[0002] PCIE (Peripheral Component Interconnect Express) signal port is a high-speed serial interface technology used for computer peripheral devices. Functional Circuit Test (FCT) of PCIE signal ports in electronic devices such as computers and servers is of great significance to ensure the performance, stability and compatibility of the above electronic devices.

[0003] In the related art, the FCT test can be performed on the PCIE signal port in the server using traditional testing equipment, and the above-mentioned traditional testing equipment includes expansion (RISER) cards, network cards, graphics cards, hard disk backplanes, hard disks, cables and other materials.

[0004] However, when using traditional test equipment to perform FCT testing on the PCIE signal port in the server, there are problems such as a large number of traditional test equipment to be connected, a complex and cumbersome test environment, and a lack of test standardization, which makes it difficult to accurately and efficiently perform functional testing on the PCIE signal port in the server in the related technology. Therefore, how to perform more accurate and efficient functional testing on the PCIE signal port in the server is a technical problem that needs to be solved in this field. Summary of the invention

[0005] The present invention provides a test fixture, a test system and a test method, which are used to solve the defect in the prior art that it is difficult to accurately and efficiently perform functional tests on PCIE signal ports in a server, and to achieve more accurate and efficient functional tests on PCIE signal ports in the server.

[0006] The present invention provides a test fixture, comprising: a target number of first PCIE signal ports, a target number of second PCIE signal ports, and a clock module; the first PCIE signal ports correspond one to one with the second PCIE signal ports;

[0007] The first end of the first PCIE signal port is connected to the PCIE signal port to be tested in the electronic device to be tested; the second end of each first PCIE signal port is connected to the first end of the second PCIE signal port corresponding to each first PCIE signal port; the third end of each first PCIE signal port is connected to the first end of the clock module, and the second end of the clock module is connected to the second end of each second PCIE signal port; the third end of each second PCIE signal port is connected to the input end of a PCIE card;

[0008] Any first PCIE signal port is used to send the PCIE signal to a second PCIE signal port corresponding to any first PCIE signal port when receiving a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port;

[0009] The clock module is used to obtain a clock source signal corresponding to the PCIE signal when it is determined that any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, and then send the obtained clock source signal to each of the second PCIE signal ports;

[0010] Any second PCIE signal port is used to send the PCIE signal and the clock source signal sent by the clock module most recently received to the PCIE card connected to any second PCIE signal port when receiving the PCIE signal sent by the first PCIE signal port corresponding to the any second PCIE signal port, so that the PCIE card can respond to the PCIE signal and the clock source signal, and then obtain the test result of the PCIE signal port to be tested connected to the first PCIE signal port corresponding to the any second PCIE signal port based on the response status of the PCIE card.

[0011] A test fixture provided according to the present invention further includes: the target number of retimer chips; the first PCIE signal port, the retimer chip and the second PCIE signal port correspond one to one;

[0012] The second end of each first PCIE signal port is connected to the first end of the second PCIE signal port corresponding to each first PCIE signal port through the retimer chip corresponding to each first PCIE signal port.

[0013] According to a test fixture provided by the present invention, the clock module comprises: a clock multiplexer; the third end of each of the first PCIE signal ports is connected to the first end of the clock multiplexer, and the second end of the clock multiplexer is connected to the second end of each of the second PCIE signal ports;

[0014] The clock multiplexer is used to obtain a clock source signal corresponding to the PCIE signal through the PCIE signal port to be tested connected to any of the first PCIE signal ports when it is determined that any of the first PCIE signal ports receives a PCIE signal sent by the PCIE signal port to be tested connected to any of the first PCIE signal ports, and then send the obtained clock source signal to each of the second PCIE signal ports.

[0015] According to a test fixture provided by the present invention, the clock module comprises: a clock expansion module;

[0016] The second end of the clock multiplexer is connected to the second end of each of the second PCIE signal ports through the clock expansion module;

[0017] The clock multiplexer is further configured to, when any of the first PCIE signal ports receives a PCIE signal sent by a PCIE signal port to be tested connected to any of the first PCIE signal ports, send a target instruction to the clock expansion module if a clock source signal corresponding to the PCIE signal is not obtained through the PCIE signal port to be tested connected to any of the first PCIE signal ports;

[0018] The clock expansion module is used to generate a clock source signal as the clock source signal corresponding to the PCIE signal when receiving the target instruction, and then copy the clock source signal corresponding to the PCIE signal, and after obtaining the clock source signals corresponding to the target number of PCIE signals, send the clock source signal corresponding to each PCIE signal to each of the second PCIE signal ports.

[0019] A test fixture provided according to the present invention further includes: a data bus test module and an indication module;

[0020] The first end of the data bus test module is respectively connected to the first end of each of the first PCIE signal ports, and the second end of the data bus test module is connected to the indication module;

[0021] Any second PCIE signal port is further used to send the data bus signal to the first PCIE signal port corresponding to any second PCIE signal port when receiving the data bus signal sent by the PCIE signal port to be tested connected to the any second PCIE signal port;

[0022] Any first PCIE signal port is further used to send the data bus signal to the data bus test module when receiving a data bus signal sent by a second PCIE signal port corresponding to any first PCIE signal port;

[0023] The data bus test module is used to perform a communication link test corresponding to any first PCIE signal port in response to a data bus signal sent by any first PCIE signal port, and then, when it is determined that there is no abnormality in the communication link corresponding to any first PCIE signal port, control the indication module to send an indication signal indicating that there is no abnormality in the communication link corresponding to any first PCIE signal port.

[0024] A test fixture provided according to the present invention further includes: the data bus port;

[0025] The third end of the data bus test module is connected to the first end of the data bus port, and the second end of the data bus port is connected to the data bus port to be tested in the electronic device to be tested;

[0026] The data bus port is used to send the data bus signal to the data bus test module when receiving the data bus signal sent by the data bus port to be tested;

[0027] The data bus test module is used for testing the data bus port to be tested in response to a data bus signal sent by the data bus port.

[0028] A test fixture provided according to the present invention further includes: a virtual pin interface and a controller; the indication module includes: an indicator light;

[0029] The first end of the virtual pin interface is connected to the virtual pin interface to be tested in the electronic device to be tested, the second end of the virtual pin interface is connected to the first end of the controller, the second end of the controller is connected to the clock multiplexer and the clock expansion module respectively, and the third end of the controller is connected to the indication module;

[0030] The virtual pin interface is used to send the virtual pin signal to the controller when receiving the virtual pin signal sent by the virtual pin interface to be tested;

[0031] The controller is used to obtain the clock source signal corresponding to the virtual pin signal from the clock multiplexer or the clock expansion module, and then perform a lighting test on the virtual pin interface to be tested based on the virtual pin signal and the clock source signal corresponding to the virtual pin signal.

[0032] According to a test fixture provided by the present invention, any second PCIE signal port is further used to send the response status information to the first PCIE signal port corresponding to any second PCIE signal port when receiving the response status information returned by the PCIE signal port to be tested connected to the any second PCIE signal port, wherein the response status information is used to indicate the response status of the PCIE signal port to be tested connected to the any second PCIE signal port after responding to the PCIE signal sent by the any second PCIE signal port and the clock source information corresponding to the PCIE signal;

[0033] When any first PCIE signal port receives response status information sent by the second PCIE signal port corresponding to the any first PCIE signal port, the response status information is sent to the PCIE signal port to be tested connected to the any first PCIE signal port, so that the PCIE signal port to be tested connected to the any first PCIE signal port sends the response status information to the processor in the electronic device to be tested, so that the processor obtains the test result of the PCIE signal port to be tested connected to the any first PCIE signal port based on the response status information.

[0034] According to a test fixture provided by the present invention, the data bus port is an I2C data bus port.

[0035] According to a test fixture provided by the present invention, the number of the PCIE signal ports to be tested connected to the first PCIE signal port is determined based on the number of data channels of the first PCIE signal port and the number of data channels of the PCIE signal port to be tested.

[0036] A test fixture provided according to the present invention also includes: a power supply interface and a power supply conversion module;

[0037] The input end of the power supply interface is connected to the power supply, and the output end of the power supply interface is connected to the power supply conversion module.

[0038] According to a test fixture provided by the present invention, the first end of the first PCIE signal port is plug-connected with the PCIE signal port to be tested, and the third end of each of the second PCIE signal ports is plug-connected with a PCIE card.

[0039] The present invention also provides a test system, comprising: a test fixture as described above and a plurality of PCIE cards; the number of the test fixtures is determined based on the number of PCIE signal ports to be tested in the electronic device to be tested; and the third end of each second PCIE signal port in the test fixture is connected to one of the PCIE cards.

[0040] A test system provided according to the present invention further includes: a processor; the processor is connected to each of the PCIE cards;

[0041] The processor is used to obtain a response state of the PCIE card after responding to the PCIE signal and the clock source signal sent by the test fixture, and then obtain a test result of the PCIE signal port to be tested based on the response state.

[0042] The present invention also provides a test method implemented based on the test system as described above, characterized in that when a PCIE signal port to be tested in the electronic device to be tested is connected to a test fixture in the test system, the method comprises:

[0043] Controlling the electronic device to be tested to output a PCIE signal through the PCIE signal port to be tested, so that the test fixture sends the PCIE signal to a PCIE card in the electronic device to be tested when receiving the PCIE signal;

[0044] Obtaining the operating status of the PCIE card;

[0045] Based on the running status, a test result of the PCIE signal port to be tested is obtained.

[0046] The test fixture, test system and test method provided by the present invention include a target number of first PCIE signal ports, a target number of second PCIE signal ports and a clock module. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the PCIE signal is sent to a second PCIE signal port corresponding to any first PCIE signal port. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. When any second PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. In the case of a PCIE signal sent, the PCIE signal and the clock source signal sent by the clock module that was most recently received are sent to a PCIE card connected to any second PCIE signal port, so that the PCIE card responds to the PCIE signal and the clock source signal, and then based on the response state of the PCIE card, a test result of the PCIE signal port to be tested connected to the first PCIE signal port corresponding to any second PCIE signal port is obtained. The test fixture provided by the present invention can be used to perform more accurate and efficient functional tests on the PCIE signal ports in electronic devices, the test environment and test operations are simpler, and the reliability during the test process is high. The test fixture provided by the present invention has a high degree of standardization, which can greatly reduce the design workload of electronic devices, can be widely used in functional tests of PCIE signal ports of different electronic devices, has stronger reusability, and has broader market application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 It is a simulation schematic diagram of using traditional testing equipment to perform functional testing on the PCIE signal port in the server in the related art.

[0049] Figure 2 This is one of the structural schematic diagrams of the test fixture provided by the present invention.

[0050] Figure 3 This is the second structural schematic diagram of the test fixture provided by the present invention.

[0051] Figure 4 This is the third structural schematic diagram of the test fixture provided by the present invention.

[0052] Figure 5 This is the fourth structural schematic diagram of the test fixture provided by the present invention.

[0053] Figure 6 This is the fifth structural schematic diagram of the test fixture provided by the present invention.

[0054] Figure 7 This is the sixth structural schematic diagram of the test fixture provided by the present invention.

[0055] Figure 8 This is the seventh structural schematic diagram of the test fixture provided by the present invention.

[0056] Fig. 9 This is one of the design drawings of the test fixture provided by the present invention.

[0057] Fig.10 This is the second design drawing of the test fixture provided by the present invention.

[0058] Fig.11 It is a schematic diagram of the flow chart of the testing method provided by the present invention.

[0059] Reference numerals:

[0060] 201: test fixture; 202: first PCIE signal port; 203: second PCIE signal port; 204: clock module; 205: electronic device to be tested; 206: PCIE signal port to be tested; 207: PCIE card; 301: retimer chip; 401: clock multiplexer; 501: clock extension module; 601: data bus test module; 602: indication module; 701: data bus port; 702: data bus port to be tested; 801: virtual pin interface; 802: controller; 803: virtual pin interface to be tested; 804: power supply interface; 805: power supply conversion module. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] In the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are usually a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, in the description of the present application, "and / or" represents at least one of the connected objects, and the character " / " generally represents that the front and back associated objects are in an "or" relationship.

[0063] It should be noted that with the rapid development of computing power and the widespread application of big data, servers have gradually become popular. Compared with personal computers (PCs), servers have the characteristics of fast running speed, high load bearing, strong central processing unit (CPU) computing power, long-term stable operation and high reliability, and also have strong I / O external data throughput and better scalability.

[0064] The excellent performance and complex hardware environment of the server, in addition to the support of excellent product design, also require server testing and verification, such as circuit testing, aging testing, automatic online testing (In-Circuit Test, ICT) testing, benchmark server index (Benchmark Server Index, BSI) testing and functional testing (FCT) testing. Among them, functional testing is an important server testing link. Functional testing is a functional test of the server board, that is, simulating the operation of the server board in a fully configured state to test whether the function of the server board is stable.

[0065] The most important and most involved test in functional testing is the test of PCIE signal ports in the server. Since the server motherboard has strong I / O expandability, the server has a lot of PCIE signal ports, including at least more than ten PCIE signal ports and at most more than twenty PCIE signal ports. Among them, PCIE signal port is a high-speed serial interface technology for computer peripherals, designed to replace the old PCI, PCI-X and AGP bus standards to achieve higher data rates and simplify system design.

[0066] Typically, the PCIE signal port in the server is a plug-in type signal port, that is, the slave device needs to be connected to the PCIE signal port in the server through a cable.

[0067] In the related art, the PCIE signal port in the server can be functionally tested using traditional testing equipment, which includes materials such as riser cards, network cards, graphics cards, hard disk backplanes, hard disks, cables, etc. Major server manufacturers have not developed independent test fixtures for functional testing of PCIE signal ports in servers, but instead use the configuration equipment of the project where the server to be tested is located for testing.

[0068] Figure 1 This is a simulation schematic diagram of using traditional testing equipment to perform functional testing on the PCIE signal port in the server in the related art. Figure 1 As shown, in the related art, RISER+network card, or hard disk backplane+hard disk, is usually used to perform functional testing on the PCIE signal port in the server to be tested, and the above-mentioned RISER card, hard disk backplane and connecting cables are all configuration devices of the project where the server to be tested is located.

[0069] In the related art, conventional testing equipment is used to perform functional testing on the PCIE signal port in the server to be tested, which has the following technical defects.

[0070] First, the number of data channels that a PCIE signal port in a server can support is usually 8, while the number of data channels that a hard disk can support is usually 4, and the number of data channels that a network card can support is usually 16.

[0071] In the related art, when using traditional test equipment to perform functional tests on the PCIE signal ports in the server under test, one PCIE signal port in the server under test needs to be connected to two hard disks to complete the functional test, or two PCIE signal ports in the server under test need to be connected to one network card to perform functional tests. If the server under test includes 20 PCIE signal ports, 40 hard disks or 10 network cards need to be connected, and more test equipment needs to be connected.

[0072] Second, in the related art, when using traditional test equipment to perform functional tests on the PCIE signal ports in the server under test, it can only rely on the configuration equipment of the project where the server under test is located, and the hard disk backplane usually includes four specifications: 2 hard disks, 4 hard disks, 8 hard disks or 16 hard disks, and the RISER card usually has a single network port or dual network ports. Therefore, the connection method between the PCIE signal port in the server under test and the traditional test equipment is relatively limited, the test environment is complex and cumbersome, and because the redundantly designed PCIE signal port in the server under test has not developed supporting equipment, it is impossible to perform functional tests on the redundantly designed PCIE signal port in the server under test.

[0073] Third, the configuration equipment of the project where the server to be tested is located may have short cables, and the size of the riser card and hard disk backplane may not be suitable for the test scenario, making it difficult to implement functional testing of the PCIE signal port in the server to be tested.

[0074] Fourth, there are many PCIE signal ports in the server to be tested, and a lot of test equipment needs to be connected. The environment is complex, and each test equipment needs to design a fixed module, which leads to a linear increase in the design workload of the project where the server to be tested is located;

[0075] Fifth, the configuration devices of different server projects are not the same, and the connection relationships between the configuration devices are also different. Therefore, the test environments between different servers are very different, and neither the quantity nor the size can be unified. Therefore, it is difficult to achieve standardized functional testing of the PCIE signal ports in the server.

[0076] Sixth, the test environment is complex, which may lead to abnormalities during the functional test of the PCIE signal port in the server under test, and it is also difficult to troubleshoot and correct errors.

[0077] In this regard, the present invention provides a test fixture, a test system and a test method. The test fixture provided by the present invention can effectively solve the technical defects of using traditional test equipment in the related art to perform functional tests on PCIE signal ports in a server, can realize functional tests on all PCIE signal ports in the server, simplify the test environment for performing functional tests on PCIE signal ports in the server, and improve the accuracy and efficiency of functional tests on PCIE signal ports in the server.

[0078] Combine the following Figure 2-Figure 8 The test fixture of the present invention is described.

[0079] Figure 2 This is one of the structural diagrams of the test fixture provided by the present invention. Figure 2 As shown, the test fixture 201 includes: a target number of first PCIE signal ports 202 , a target number of second PCIE signal ports 203 , and a clock module 204 ; the first PCIE signal ports 202 correspond to the second PCIE signal ports 203 one by one.

[0080] The first end of the first PCIE signal port 202 is connected to the PCIE signal port 206 to be tested in the electronic device 205 to be tested; the second end of each first PCIE signal port 202 is connected to the first end of the second PCIE signal port 203 corresponding to each first PCIE signal port 202; the third end of each first PCIE signal port 202 is connected to the first end of the clock module 204, and the second end of the clock module 204 is connected to the second end of each second PCIE signal port 203; the third end of each second PCIE signal port 203 is connected to the input end of a PCIE card 207.

[0081] Any first PCIE signal port 202 is used to send the PCIE signal to the second PCIE signal port 203 corresponding to any first PCIE signal port 202 when receiving the PCIE signal sent by the PCIE signal port to be tested 206 connected to any first PCIE signal port 202 .

[0082] The clock module 204 is used to obtain a clock source signal corresponding to the PCIE signal when it is determined that any first PCIE signal port 202 receives a PCIE signal sent by a PCIE signal port 206 to be tested and connected to any first PCIE signal port 202, and then send the obtained clock source signal to each second PCIE signal port 203.

[0083] Any second PCIE signal port 203 is used to send the PCIE signal and the clock source signal most recently received from the clock module 204 to the PCIE card 207 connected to any second PCIE signal port 203 upon receiving the PCIE signal sent by the first PCIE signal port 202 corresponding to any second PCIE signal port 203, so that the PCIE card 207 can respond to the PCIE signal and the clock source signal, and then obtain the test result of the PCIE signal port 206 to be tested connected to the first PCIE signal port 202 corresponding to any second PCIE signal port 203 based on the response status of the PCIE card 207.

[0084] Specifically, in the embodiment of the present invention, the PCIE signal port in the electronic device 205 to be tested is determined as the PCIE signal port 206 to be tested. The PCIE signal port 206 to be tested in the electronic device 205 to be tested is the test object of the test fixture 201 provided by the present invention. Based on the test fixture 201 provided by the present invention, the PCIE signal port 206 to be tested in the electronic device 205 to be tested can be functionally tested.

[0085] It is understandable that the electronic device to be tested 205 can be determined based on actual needs. In the embodiment of the present invention, the electronic device to be tested 205 is not specifically limited.

[0086] It should be noted that the electronic device to be tested 205 in the embodiment of the present invention may be an electronic device such as a computer or a server.

[0087] Preferably, the electronic device to be tested 205 in the embodiment of the present invention may be a server.

[0088] It should be noted that in the embodiment of the present invention, the first PCIE signal port 202 and the second PCIE signal port 203 have the same number of data channels. For example, the first PCIE signal port 202 and the second PCIE signal port 203 both have 4, 8 or 16 data channels.

[0089] It should be noted that, in the embodiments of the present invention, N Indicates the number of targets, the number of targets N Can be determined based on prior knowledge and / or actual conditions, such as the target number N The target number may be determined based on the number of data channels of the first PCIE signal port 202 and the second PCIE signal port 203, the number of data channels of the PCIE signal port 206 to be tested in the electronic device 205 to be tested, and the number of the PCIE signal ports 206 to be tested. N No specific limitation is given.

[0090] The first PCIE signal port in the test fixture 201 i With the second PCIE signal port i correspond. i =1,2,3,…, N .

[0091] It should be noted that, in the embodiment of the present invention, the first end of the first PCIE signal port 202 may be connected to one or more PCIE signal ports 206 to be tested.

[0092] It should be noted that the PCIE signal port in the embodiment of the present invention may include an MCIO (Multi-Channel Input / Output) signal port, a Slimline signal port, a GENZ signal port, an OCP signal port, and the like.

[0093] As an optional embodiment, the number of the PCIE signal ports 206 to be tested connected to the first PCIE signal port 202 is determined based on the number of data channels of the first PCIE signal port 202 and the number of data channels of the PCIE signal ports 206 to be tested.

[0094] Specifically, when the number of data channels of the first PCIE signal port 202 is the same as the number of data channels of the PCIE signal port 206 to be tested, the first end of the first PCIE signal port 202 may be connected to one PCIE signal port 206 to be tested. When the number of data channels of the first PCIE signal port 202 is twice the number of data channels of the PCIE signal port 206 to be tested, the first end of the first PCIE signal port 202 may be connected to two PCIE signal ports 206 to be tested. When the number of data channels of the first PCIE signal port 202 is four times the number of data channels of the PCIE signal port 206 to be tested, the first end of the first PCIE signal port 202 may be connected to four PCIE signal ports 206 to be tested.

[0095] It should be noted that Figure 2 The test fixture 201 shown in the figure shows the connection relationship between the first PCIE signal port 202 and the PCIE signal port 206 to be tested when the number of data channels of the first PCIE signal port 202 is the same as the number of data channels of the PCIE signal port 206 to be tested. Figure 2 As shown, when the number of data channels of the first PCIE signal port 202 is the same as the number of data channels of the PCIE signal port 206 to be tested, the first PCIE signal port 202 in the test fixture 201 is i The first PCIE signal port 202 and the PCIE signal port to be tested in the electronic device to be tested 205 i Corresponding, the first PCIE signal port i The first end is connected to the PCIE signal port to be tested i The following takes the case where the number of data channels of the first PCIE signal port 202 is the same as the number of data channels of the PCIE signal port to be tested 206 as an example to illustrate the test fixture 201 provided by the present invention.

[0096] It should be noted that, in the embodiment of the present invention, the number of data channels of the first PCIE signal port 202 is not less than the number of data channels of the PCIE signal port 206 to be tested.

[0097] As an optional embodiment, the first end of the first PCIE signal port 202 is plugged and connected to the PCIE signal port 206 to be tested, and the third end of each second PCIE signal port 203 is plugged and connected to a PCIE card 207 .

[0098] It should be noted that the plug-in connection refers to setting corresponding plug-in fitting fixing structures at relevant parts of the components that need to be fixed to each other.

[0099] The first end of the first PCIE signal port 202 is plugged and connected to the PCIE signal port 206 to be tested, and the third end of each second PCIE signal port 203 is plugged and connected to a PCIE card 207, which has the advantages of fast and convenient connection operation, high connection reliability, strong repeatability, waterproofness, dustproofness, and good electrical and mechanical properties.

[0100] For the first PCIE signal port in the test fixture 201 i , the first PCIE signal port i After receiving the PCIE signal port to be tested i In the case of sending a PCIE signal, the first PCIE signal port i The second end and the second PCIE signal port i The first end of the PCIE signal is sent to the second PCIE signal port i .

[0101] The first PCIE signal port i After receiving the PCIE signal port to be tested i In the case of sending a PCIE signal, the clock module 204 can transmit the signal through the first end of the clock module 204 and the first PCIE signal port i The third end of the clock module 204 obtains the clock source signal corresponding to the PCIE signal, and transmits the clock source signal to the second end of the clock module 204 and the second PCIE signal port. i The second end of the PCIE signal sends the clock source signal corresponding to the PCIE signal to each second PCIE signal port 203.

[0102] Second PCIE signal port i Upon receiving the first PCIE signal port i In the case of a PCIE signal sent by the clock module 204 and a clock source signal corresponding to the PCIE signal sent by the clock module 204, the PCIE signal and the clock source signal corresponding to the PCIE signal can be sent to the PCIE card i .

[0103] PCIE Card i After receiving the PCIE signal and the clock source signal corresponding to the PCIE signal, the PCIE signal and the clock source signal corresponding to the PCIE signal can be responded to, thereby i Get the response status of the PCIE signal port to be tested i of the test results.

[0104] It is understandable that on the PCIE card iIf the response state after responding to the PCIE signal and the clock source signal corresponding to the PCIE signal meets the expected state, the PCIE signal port to be tested can be determined. i The test result is the PCIE signal port to be tested i No abnormality; on the PCIE card i If the response state after responding to the PCIE signal and the clock source signal corresponding to the PCIE signal does not meet the expected state, it can be determined that the PCIE signal port to be tested i The test result is the PCIE signal port to be tested i There is an abnormality. Among them, the PCIE card i The expected state after responding to the PCIE signal and the clock source signal corresponding to the PCIE signal is determined based on the content of the PCIE signal.

[0105] It should be noted that the PCIE card 207 in the embodiment of the present invention may include but is not limited to a network card, a sound card, a graphics card, a hard disk, a RAID card, and a high-speed data transmission card.

[0106] The test fixture in the embodiment of the present invention includes a target number of first PCIE signal ports, a target number of second PCIE signal ports and a clock module. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the PCIE signal is sent to a second PCIE signal port corresponding to any first PCIE signal port. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. When any second PCIE signal port receives a PCIE signal sent by a first PCIE signal port corresponding to any second PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. In the case of an E signal, the PCIE signal and the clock source signal sent by the clock module that is most recently received are sent to the PCIE card connected to any second PCIE signal port, so that the PCIE card responds to the PCIE signal and the clock source signal, and then based on the response state of the PCIE card, the test result of the PCIE signal port to be tested connected to the first PCIE signal port corresponding to any second PCIE signal port is obtained. The test fixture provided by the present invention can be used to perform more accurate and efficient functional tests on the PCIE signal ports in the electronic device, the test environment and the test operation are simpler, and the reliability during the test process is high. The test fixture provided by the present invention has a high degree of standardization, which can greatly reduce the design workload of electronic equipment, can be widely used in functional tests of PCIE signal ports of different electronic devices, has stronger reusability, and has a broader market application prospect.

[0107] Figure 3 FIG. 2 is a second structural diagram of the test fixture provided by the present invention. As an optional embodiment, Figure 3 As shown, the test fixture 201 further includes: a target number of retimer chips 301 ; a one-to-one correspondence between the first PCIE signal port 202 , the retimer chip 301 and the second PCIE signal port 203 .

[0108] The second end of each first PCIE signal port 202 is connected to the first end of the second PCIE signal port 203 corresponding to each first PCIE signal port 202 through the retimer chip 301 corresponding to each first PCIE signal port 202 .

[0109] Specifically, since the PCIE signal is a high-speed signal, the signal quality may be reduced during the transmission process of the PCIE signal in the test fixture 201 due to the long communication link and connector contact, thereby affecting the response state of the PCIE card 207 connected to the test fixture 201, and reducing the test accuracy of the functional test of the PCIE signal port 206 to be tested.

[0110] Therefore, the test fixture 201 in the embodiment of the present invention further includes a target number of retimer chips 301 . The retimer chips 301 in the test fixture can be used to optimize the transmission of PCIE signals and improve the stability of the test fixture 201 .

[0111] The retimer chip is an ultra-high-speed timing integration chip suitable for high-speed data transmission protocols. The retimer chip 301 is mainly used to solve the signal attenuation and timing reorganization problems that occur during high-speed data transmission to improve signal quality and transmission distance.

[0112] It should be noted that the number of data channels of the retimer chip 301 in the embodiment of the present invention is the same as the number of data channels of the first PCIE signal port 202. For example, the number of data channels of the first PCIE signal port 202 and the retimer chip 301 are both 4, 8 or 16.

[0113] The first PCIE signal port in the test fixture 201 i The second port of the retimer chip i One end of the re-timer chip is connected to i The other end is connected to the second PCIE signal port i The first end of the connection.

[0114] The retimer chip 301 in the test fixture 201 can adjust and compensate the PCIE signal received by the first PCIE signal port 202 one by one, and use advanced signal conditioning technology to compensate for the loss on the communication link between the first PCIE signal port 202 and the second PCIE signal port 203, and eliminate the influence of various jitter sources, thereby improving the integrity of the PCIE signal received by the PCIE card 207 and increasing the effective transmission distance of the PCIE signal.

[0115] Figure 4 FIG. 3 is a schematic diagram of the structure of the test fixture provided by the present invention. As an optional embodiment, Figure 4 As shown, the clock module 204 includes: a clock multiplexer 401; a third end of each first PCIE signal port 202 is connected to a first end of the clock multiplexer 401, and a second end of the clock multiplexer 401 is connected to a second end of each second PCIE signal port 203.

[0116] The clock multiplexer 401 is used to obtain a clock source signal corresponding to the PCIE signal through the PCIE signal port 206 under test connected to any first PCIE signal port 202 when it is determined that any first PCIE signal port 202 receives a PCIE signal sent by the PCIE signal port 206 under test connected to any first PCIE signal port 202, and then send the obtained clock source signal to each second PCIE signal port 203.

[0117] Specifically, the first PCIE signal port in the test fixture 201 i The third end of the clock multiplexer 401 is connected to the first end of the clock multiplexer 401, and the second end of the clock multiplexer 401 is connected to the first PCIE signal port in the test fixture 201. i The second end of the connection.

[0118] The first PCIE signal port i After receiving the PCIE signal port to be tested i In the case of sending a PCIE signal, the clock multiplexer 401 can be connected to the first PCIE signal port i Connected PCIE signal port to be tested i , obtain the clock source signal corresponding to the above PCIE signal, and then send the obtained clock source signal to each second PCIE signal port 203, so that the second PCIE signal port i Upon receiving the first PCIE signal port i In the case of a PCIE signal sent by the clock module 204 and a clock source signal corresponding to the PCIE signal sent by the clock module 204, the PCIE signal and the clock source signal corresponding to the PCIE signal can be sent to the PCIE card i .

[0119] The clock module in the embodiment of the present invention includes a clock multiplexer. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested, the clock multiplexer can more accurately and efficiently obtain a clock source signal corresponding to the PCIE signal to be tested through the PCIE signal to be tested.

[0120] Figure 5 FIG. 4 is a schematic diagram of the structure of the test fixture provided by the present invention. As an optional embodiment, Figure 5 As shown, the clock module 204 includes: a clock expansion module 501.

[0121] The second end of the clock multiplexer 401 is connected to the second end of each second PCIE signal port 203 through the clock expansion module 501 .

[0122] The clock multiplexer 401 is also used to send a target instruction to the clock expansion module 501 when any first PCIE signal port 202 receives a PCIE signal sent by a PCIE signal port 206 to be tested that is connected to any first PCIE signal port 202, and if a clock source signal corresponding to the PCIE signal is not obtained through the PCIE signal port 206 to be tested that is connected to any first PCIE signal port 202.

[0123] The clock expansion module 501 is used to generate a clock source signal as the clock source signal corresponding to the PCIE signal when receiving the target instruction, and then copy the clock source signal corresponding to the PCIE signal, and after obtaining the clock source signals corresponding to the target number of PCIE signals, send the clock source signal corresponding to each PCIE signal to each second PCIE signal port 203.

[0124] Specifically, the first PCIE signal port i After receiving the PCIE signal port to be tested i In the case of sending a PCIE signal, the clock multiplexer 401 can be connected to the first PCIE signal port i Connected PCIE signal port to be tested i , obtain the clock source signal corresponding to the above PCIE signal.

[0125] However, the PCIE signal port to be tested i It does not necessarily contain a clock signal. If the clock multiplexer 401 is connected to the first PCIE signal port i Connected PCIE signal port to be tested i If the clock source signal corresponding to the above PCIE signal is not obtained, the PCIE card will i Failure to respond normally to received PCIE signals leads to test failure.

[0126] Therefore, in the embodiment of the present invention, the clock multiplexer 401 is connected to the first PCIE signal port i Connected PCIE signal port to be tested i , when the clock source signal corresponding to the above PCIE signal is not obtained, a target instruction is sent to the clock expansion module 501.

[0127] When receiving the above-mentioned target instruction, the clock extension module 501 can generate a clock source signal as the clock source signal corresponding to the above-mentioned PCIE signal, and then can copy the clock source signal corresponding to the above-mentioned PCIE signal. After obtaining the target number of clock source signals corresponding to the above-mentioned PCIE signals, each clock source signal corresponding to the above-mentioned PCIE signal is sent to each second PCIE signal port 203.

[0128] The clock module in the embodiment of the present invention also includes a clock extension module. When the clock multiplexer fails to obtain the clock source signal corresponding to the PCIE signal, the clock extension module can generate a clock source signal as the clock source signal corresponding to the PCIE signal, and then copy the clock source signal corresponding to the above PCIE signal. After obtaining the target number of clock source signals corresponding to the above PCIE signals, the clock source signal corresponding to each PCIE signal is sent to each second PCIE signal port, thereby avoiding the failure of the test of the PCIE signal port to be tested due to the lack of the clock source signal, and can further improve the reliability of the test fixture.

[0129] As an optional embodiment, any second PCIE signal port 203 is also used to send response status information to the first PCIE signal port 202 corresponding to any second PCIE signal port 203 upon receiving response status information returned by the PCIE signal port 206 to be tested connected to any second PCIE signal port 203. The response status information is used to indicate the response status of the PCIE signal port 206 to be tested connected to any second PCIE signal port 203 after responding to the PCIE signal sent by any second PCIE signal port 203 and the clock source information corresponding to the PCIE signal.

[0130] Specifically, PCIE card i After responding to the received PCIE signal and the clock source signal corresponding to the PCIE signal, the second PCIE signal port i Returns the value used to represent the PCIE card i Response status information of the response status.

[0131] Second PCIE signal port i After receiving the PCIE card i In the case of sending the response status information, the above response status information can be sent to the first PCIE signal port i .

[0132] When any first PCIE signal port 202 receives response status information sent by the second PCIE signal port 203 corresponding to any first PCIE signal port 202, the response status information is sent to the PCIE signal port 206 to be tested connected to any first PCIE signal port, so that the PCIE signal port 206 to be tested connected to any first PCIE signal port sends the response status information to the processor in the electronic device 205 to be tested, so that the processor obtains the test result of the PCIE signal port 206 to be tested connected to any first PCIE signal port based on the response status information.

[0133] Specifically, the first PCIE signal port i After receiving the second PCIE signal port i In the case of sending the response status information, the above response status information can be sent to the PCIE signal port to be tested i .

[0134] PCIE signal port to be tested i When the above response status information is received, the above response status information can be sent to the processor in the electronic device under test 205, so that the processor in the electronic device under test 205 can determine whether the PCIE card is i PCIE signal port to be tested i The response state after the PCIE signal sent out and the clock source signal corresponding to the above PCIE signal responds to the expected state, and the PCIE card is determined i If the response status of the PCIE signal port to be tested meets the expected status, determine i The test result is the PCIE signal port to be tested i No abnormality, confirm the PCIE card i If the response status of the PCIE signal port to be tested meets the unexpected status, determine i The test result is the PCIE signal port to be tested i There is an anomaly.

[0135] Figure 6 FIG. 5 is a schematic diagram of the structure of the test fixture provided by the present invention. As an optional embodiment, Figure 6 As shown, the test fixture 201 further includes: a data bus test module 601 and an indication module 602 .

[0136] A first end of the data bus test module 601 is connected to a first end of each first PCIE signal port 202 , and a second end of the data bus test module 601 is connected to the indication module.

[0137] Any second PCIE signal port 203 is further used to send the data bus signal to the first PCIE signal port 202 corresponding to any second PCIE signal port 203 when receiving the data bus signal sent by the PCIE signal port 206 to be tested connected to any second PCIE signal port 203 .

[0138] Any first PCIE signal port 202 is further configured to send the data bus signal to the data bus test module 601 when receiving a data bus signal sent by a second PCIE signal port 203 corresponding to any first PCIE signal port 202 .

[0139] The data bus test module 601 is used to perform a communication link test corresponding to any first PCIE signal port 202 in response to a data bus signal sent by any first PCIE signal port 202, and then, when it is determined that there is no abnormality in the communication link corresponding to any first PCIE signal port 202, the control indication module 602 sends an indication signal indicating that there is no abnormality in the communication link corresponding to any first PCIE signal port 202.

[0140] Specifically, the second PCIE signal port i After receiving the PCIE card i In the case of a data bus signal sent, the data bus signal can be sent to the first PCIE signal port i .

[0141] The first PCIE signal port i When the data bus signal is received, the data bus signal may be sent to the data bus test module 601 .

[0142] It should be noted that the data bus test module 601 is a microcontroller module composed of multiple microcontroller units (MCUs). The microcontroller units in the data bus test module 601 correspond one-to-one to the second PCIE signal port 203 and the first PCIE signal port 202. Any microcontroller unit in the data bus test module 601 has a unique address.

[0143] The data bus test module 601 receives the first PCIE signal port i In the case of the above data bus signal sent, a data bus scanning action can be performed to scan the addresses of each micro control unit in the data bus test module 601. When the first PCIE signal port is scanned i The first PCIE signal port can be determined by the address of the corresponding micro control unit. i The corresponding communication link is normal, the first PCIE signal porti The corresponding micro control unit can control the indication module 602 to send a signal indicating the first PCIE signal port i There is no abnormal indication signal on the corresponding communication link.

[0144] It should be noted that the indication module 602 in the embodiment of the present invention can send indication signals in the form of sound, light, electricity, etc. The embodiment of the present invention does not specifically limit the specific structure of the indication module 602 and the specific type of the indication signal sent.

[0145] Optionally, the indication module 602 in the embodiment of the present invention may include an LED indicator light.

[0146] The test fixture in the embodiment of the present invention also includes a data bus test module and an indication module, so that the test fixture can perform a more accurate and efficient functional test on the PCIE signal port in the electronic device, and at the same time, based on the uplink data bus signal, test whether the communication link inside the test fixture is abnormal, which can further improve the reliability of the test fixture.

[0147] Figure 7 FIG. 6 is a sixth structural diagram of the test fixture provided by the present invention. As an optional embodiment, Figure 7 As shown, the test fixture 201 further includes: a data bus port 701 .

[0148] The third end of the data bus test module 601 is connected to the first end of the data bus port, and the second end of the data bus port is connected to the data bus port 702 to be tested in the electronic device 205 to be tested.

[0149] The data bus port 701 is used to send the data bus signal to the data bus test module 601 when receiving the data bus signal sent by the data bus port 702 to be tested.

[0150] The data bus test module 601 is used to test the data bus port 702 to be tested in response to the data bus signal sent by the data bus port 701 .

[0151] It should be noted that, in general, modules such as the Baseboard Management Controller (BMC) in an electronic system will perform a system self-check when the electronic system is started. When the BMC performs a system self-check, it will actively scan all connected data buses to detect whether the devices connected to these data buses exist and are working properly.

[0152] Therefore, the embodiment of the present invention utilizes the characteristic that the electronic system will perform a system self-check when it is started, and determines whether there is an abnormality in the data bus interface to be tested by determining whether the electronic system to be tested can scan the address corresponding to the data bus interface to be tested in the data bus test module 601 during the system self-check.

[0153] It should be noted that the second end of the data bus port in the embodiment of the present invention can be plug-connected with the data bus port 702 to be tested in the electronic device 205 to be tested.

[0154] As an optional embodiment, the data bus is an I2C data bus.

[0155] The test fixture in the embodiment of the present invention further includes a data bus port, and the data bus port and the data bus test module can be used to test the data bus port 702 to be tested in the electronic device to be tested, thereby improving the functionality and adaptability of the test fixture.

[0156] Figure 8 FIG. 7 is a schematic diagram of the structure of the test fixture provided by the present invention. As an optional embodiment, Figure 8 As shown, the test fixture 201 further includes: a virtual pin interface 801 and a controller 802; an indication module 602 includes: an indicator light.

[0157] The first end of the virtual pin interface is connected to the virtual pin interface 803 to be tested in the electronic device 205 to be tested, the second end of the virtual pin interface 801 is connected to the first end of the controller 802, the second end of the controller 802 is respectively connected to the clock multiplexer 401 and the clock expansion module 501, and the third end of the controller 802 is connected to the indication module 602.

[0158] The virtual pin interface 801 is used to send the virtual pin signal to the controller 802 when receiving the virtual pin signal sent by the virtual pin interface 803 to be tested.

[0159] The controller 802 is used to obtain the clock source signal corresponding to the virtual pin signal from the clock multiplexer 401 or the clock expansion module 501, and then perform a lighting test on the virtual pin interface 803 to be tested based on the virtual pin signal and the clock source signal corresponding to the virtual pin signal.

[0160] It should be noted that the virtual private port (VPP) interface 801 is similar to the I2C data bus port 701 and is a specific transmission method implemented based on the I2C bus protocol, and its transmission data has a specific interaction protocol.

[0161] The controller 802 in the embodiment of the present invention can simulate the process of interactive data, so that the controller 802 can parse the virtual pin signal sent to the controller 802 by the virtual pin interface 801, and the controller 802 can light up the corresponding indicator light in the indication module 602 to realize the VPP lighting test.

[0162] Among them, the lighting test refers to a test method that verifies whether the internal interface, circuit or function of the device is working properly by controlling the on and off state of the indicator light on the device. The indicator light is often used as a status indicator because of its intuitiveness to reflect the operating status or fault information of the device.

[0163] It should be noted that the controller 802 in the embodiment of the present invention may be a complex programmable logic device (CPLD).

[0164] It should be noted that in the embodiment of the present invention, the virtual pin signal does not participate in the selection control of the clock source signal. The clock source signal corresponding to the virtual pin signal is obtained by the controller 802 itself.

[0165] It should be noted that when using the test fixture 201 provided by the present invention for testing, it is necessary to perform a wiring evaluation in advance to evaluate whether the PCIE signal port 206 to be tested connected to the first PCIE signal port 202 carries a clock source signal, and then use the dial module on the controller 802 to control the controller 802 to select the corresponding PCIE signal port 206 to be tested to obtain the clock source signal corresponding to the virtual pin signal.

[0166] The test fixture in the embodiment of the present invention also includes a virtual pin interface 801 and a controller 802, which can be used to perform a lighting test on the virtual pin interface 803 to be tested in the electronic device 205 to further improve the functionality and adaptability of the test fixture.

[0167] As an optional embodiment, Figure 8 As shown, the test fixture 201 further includes: a power supply interface 804 and a power supply conversion module 805 .

[0168] An input end of the power supply interface 804 is connected to a power source, and an output end of the power supply interface 804 is connected to a power supply conversion module 805 .

[0169] Specifically, the power conversion module 805 can be used to convert the power supply voltage provided by the power supply into a power supply voltage of 1.8V, 3.3V, 5V or 12V to power each component in the test fixture 201 .

[0170] The power supply conversion module 805 can also provide protection measures such as overvoltage and overcurrent to prevent the test fixture 201 from being damaged due to power supply.

[0171] Fig. 9 This is one of the design drawings of the test fixture provided by the present invention. Fig.10 This is the second design drawing of the test fixture provided by the present invention. Fig. 9 and Fig.10 shown.

[0172] The test fixture provided by the present invention frees the FCT test of the PCIE signal port from the constraints of the project (including project configuration scheme, supporting boards, cable length, etc.), making the test scheme unified, simple, integrated and modular, and further simplifying the design of the test fixture. Compared with the traditional test method, the test fixture provided by the present invention adds a signal compensation function, the high-speed signal quality is improved, and the test yield and stability are improved. After the test fixture provided by the present invention unifies the test environment, it solves the problem that the test fixture cannot be standardized and modularized, and greatly improves the degree of automation.

[0173] The test fixture provided by the present invention realizes the independence and integration of the PCIE signal port FCT test, wherein the independence means that the test scheme is free from the dependence on the project configuration scheme, and the integration means that the test that originally required multiple devices can be completed by a single device.

[0174] The test fixture provided by the present invention further promotes the development of FCT fixtures, provides a research direction for the standardized design of FCT fixtures, simplifies fixture design, and unifies design modules. In addition, the introduction of Retimer also greatly reduces the error rate of PCIE testing, improves the quality of test signals, and reduces the difficulty of error correction and troubleshooting.

[0175] Based on the contents of the above embodiments, a test system includes: any of the above test fixtures 201 and multiple PCIE cards 207; the number of test fixtures 201 is determined based on the number of PCIE signal ports 206 to be tested in the electronic device 205 to be tested; the third end of each second PCIE signal port 203 in the test fixture 201 is connected to a PCIE card 207.

[0176] Specifically, the specific structure of the test fixture 201 in the embodiment of the present invention, the connection method between the test fixture 201 and the PCIE signal port 206 to be tested in the electronic device 205 to be tested, and the connection method between the test fixture 201 and the PCIE card 207 can refer to the contents of the above embodiments, and will not be repeated in the embodiment of the present invention.

[0177] The test system in the embodiment of the present invention includes a test fixture and a PCIE card. The test fixture includes a target number of first PCIE signal ports, a target number of second PCIE signal ports, and a clock module. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the PCIE signal is sent to a second PCIE signal port corresponding to any first PCIE signal port. When any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. When any second PCIE signal port receives a first PCIE signal corresponding to any second PCIE signal port, the clock module obtains a clock source signal corresponding to the PCIE signal, and then sends the obtained clock source signal to each second PCIE signal port. In the case of a PCIE signal sent by a first PCIE signal port, the PCIE signal and the clock source signal sent by the clock module which is received most recently are sent to a PCIE card connected to any second PCIE signal port, so that the PCIE card responds to the PCIE signal and the clock source signal, and then based on the response state of the PCIE card, a test result of the PCIE signal port to be tested which is connected to the first PCIE signal port corresponding to any second PCIE signal port is obtained. The test fixture provided by the present invention can be used to perform more accurate and efficient functional tests on the PCIE signal ports in electronic devices, the test environment and the test operation are simpler, and the reliability during the test process is high. The test fixture provided by the present invention has a high degree of standardization, which can greatly reduce the design workload of electronic devices, can be widely used in functional tests of PCIE signal ports of different electronic devices, has stronger reusability, and has a broader market application prospect.

[0178] As an optional embodiment, the test system further includes: a processor; the processor is connected to each PCIE card 207.

[0179] The processor is used to obtain the response status of the PCIE card 207 after responding to the PCIE signal and the clock source signal sent by the test fixture 201, and then obtain the test result of the PCIE signal port 206 to be tested based on the response status.

[0180] Fig.11 Schematic diagram of the test method provided by the present invention. Fig.11 The test method of the present invention is described below. The test method provided by the present invention is implemented based on the test system described above. When the PCIE signal port 206 to be tested in the electronic device 205 to be tested is connected to the test fixture 201 in the test system, as shown in FIG. Fig.11As shown, the method includes: step 111, controlling the electronic device 205 to be tested to output a PCIE signal through the PCIE signal port 206 to be tested, so that the test fixture 201 sends the PCIE signal to the PCIE card 207 in the electronic device to be tested when receiving the PCIE signal.

[0181] Step 112: Get the response status of the PCIE card 207.

[0182] Step 113: Based on the response status, obtain the test result of the PCIE signal port 206 to be tested.

[0183] It should be noted that the execution subject of the embodiment of the present invention is a processor in the test system.

[0184] It should be noted that the specific implementation process of the testing method provided by the present invention can refer to the contents of the above embodiments, and the embodiments of the present invention will not be described in detail.

[0185] The embodiment of the present invention controls the electronic device to be tested to output a PCIE signal through the PCIE signal port to be tested, so that when the test fixture receives the PCIE signal, it sends the PCIE signal to the PCIE card in the electronic device to be tested, obtains the response status of the PCIE card, and obtains the test result of the PCIE signal port to be tested based on the response status. The PCIE signal port in the electronic device can be functionally tested more accurately and efficiently, the test environment and test operation are simpler, the reliability and standardization during the test process are high, the design workload of the electronic device can be greatly reduced, and it can be widely applied to the functional testing of the PCIE signal ports of different electronic devices, with stronger reusability and broader market application prospects.

[0186] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A test fixture, characterized in that: include: A target number of first high-speed serial computer expansion bus standard PCIE signal ports, a target number of second PCIE signal ports and a clock module; The first PCIE signal port corresponds to the second PCIE signal port one by one; the target number is determined based on the number of data channels of the first PCIE signal port and the second PCIE signal port, the number of data channels of the PCIE signal port to be tested in the electronic device to be tested, and the number of the PCIE signal ports to be tested; The first end of the first PCIE signal port is connected to the PCIE signal port to be tested in the electronic device to be tested; the second end of each first PCIE signal port is connected to the first end of the second PCIE signal port corresponding to each first PCIE signal port; the third end of each first PCIE signal port is connected to the first end of the clock module, and the second end of the clock module is connected to the second end of each second PCIE signal port; The third end of each of the second PCIE signal ports is connected to an input end of a PCIE card; Any first PCIE signal port is used to send the PCIE signal to a second PCIE signal port corresponding to any first PCIE signal port when receiving a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port; The clock module is used to obtain a clock source signal corresponding to the PCIE signal when it is determined that any first PCIE signal port receives a PCIE signal sent by a PCIE signal port to be tested connected to any first PCIE signal port, and then send the obtained clock source signal to each of the second PCIE signal ports; Any second PCIE signal port is used to send the PCIE signal and the clock source signal sent by the clock module most recently received to the PCIE card connected to any second PCIE signal port when receiving the PCIE signal sent by the first PCIE signal port corresponding to the any second PCIE signal port, so that the PCIE card can respond to the PCIE signal and the clock source signal, and then obtain the test result of the PCIE signal port to be tested connected to the first PCIE signal port corresponding to the any second PCIE signal port based on the response status of the PCIE card.

2. The test fixture according to claim 1, characterized in that: Also includes: Target number of retimer chips; The first PCIE signal port, the retimer chip and the second PCIE signal port correspond one to one; The second end of each first PCIE signal port is connected to the first end of the second PCIE signal port corresponding to each first PCIE signal port through the retimer chip corresponding to each first PCIE signal port.

3. The test fixture according to claim 2, characterized in that: The clock module comprises: a clock multiplexer; the third end of each of the first PCIE signal ports is connected to the first end of the clock multiplexer, and the second end of the clock multiplexer is connected to the second end of each of the second PCIE signal ports; The clock multiplexer is used to obtain a clock source signal corresponding to the PCIE signal through the PCIE signal port to be tested connected to any of the first PCIE signal ports when it is determined that any of the first PCIE signal ports receives a PCIE signal sent by the PCIE signal port to be tested connected to any of the first PCIE signal ports, and then send the obtained clock source signal to each of the second PCIE signal ports.

4. The test fixture according to claim 3, characterized in that: The clock module includes: a clock expansion module; The second end of the clock multiplexer is connected to the second end of each of the second PCIE signal ports through the clock expansion module; The clock multiplexer is further configured to, when any of the first PCIE signal ports receives a PCIE signal sent by a PCIE signal port to be tested connected to any of the first PCIE signal ports, send a target instruction to the clock expansion module if a clock source signal corresponding to the PCIE signal is not obtained through the PCIE signal port to be tested connected to any of the first PCIE signal ports; The clock expansion module is used to generate a clock source signal as the clock source signal corresponding to the PCIE signal when receiving the target instruction, and then copy the clock source signal corresponding to the PCIE signal, and after obtaining the clock source signals corresponding to the target number of PCIE signals, send the clock source signal corresponding to each PCIE signal to each of the second PCIE signal ports.

5. The test fixture according to claim 4, characterized in that: Also includes: Data bus test module and indication module; The first end of the data bus test module is respectively connected to the first end of each of the first PCIE signal ports, and the second end of the data bus test module is connected to the indication module; Any second PCIE signal port is further used to send the data bus signal to the first PCIE signal port corresponding to any second PCIE signal port when receiving the data bus signal sent by the PCIE signal port to be tested connected to the any second PCIE signal port; Any first PCIE signal port is further used to send the data bus signal to the data bus test module when receiving a data bus signal sent by a second PCIE signal port corresponding to any first PCIE signal port; The data bus test module is used to perform a communication link test corresponding to any first PCIE signal port in response to a data bus signal sent by any first PCIE signal port, and then, when it is determined that there is no abnormality in the communication link corresponding to any first PCIE signal port, control the indication module to send an indication signal indicating that there is no abnormality in the communication link corresponding to any first PCIE signal port.

6. The test fixture according to claim 5, characterized in that: Also includes: Data bus port; The third end of the data bus test module is connected to the first end of the data bus port, and the second end of the data bus port is connected to the data bus port to be tested in the electronic device to be tested; The data bus port is used to send the data bus signal to the data bus test module when receiving the data bus signal sent by the data bus port to be tested; The data bus test module is used for testing the data bus port to be tested in response to a data bus signal sent by the data bus port.

7. The test fixture according to claim 6, characterized in that: Also includes: Virtual pin interface and controller; The indication module comprises: an indicator light; The first end of the virtual pin interface is connected to the virtual pin interface to be tested in the electronic device to be tested, the second end of the virtual pin interface is connected to the first end of the controller, the second end of the controller is respectively connected to the clock multiplexer and the clock expansion module, and the third end of the controller is connected to the indication module; The virtual pin interface is used to send the virtual pin signal to the controller when receiving the virtual pin signal sent by the virtual pin interface to be tested; The controller is used to obtain the clock source signal corresponding to the virtual pin signal from the clock multiplexer or the clock expansion module, and then perform a lighting test on the virtual pin interface to be tested based on the virtual pin signal and the clock source signal corresponding to the virtual pin signal.

8. The test fixture according to claim 1, characterized in that: Any second PCIE signal port is further used to send the response status information to the first PCIE signal port corresponding to any second PCIE signal port when receiving the response status information returned by the PCIE signal port to be tested connected to the any second PCIE signal port, wherein the response status information is used to indicate the response status of the PCIE signal port to be tested connected to the any second PCIE signal port after responding to the PCIE signal sent by the any second PCIE signal port and the clock source information corresponding to the PCIE signal; When any first PCIE signal port receives response status information sent by the second PCIE signal port corresponding to the any first PCIE signal port, the response status information is sent to the PCIE signal port to be tested connected to the any first PCIE signal port, so that the PCIE signal port to be tested connected to the any first PCIE signal port sends the response status information to the processor in the electronic device to be tested, so that the processor obtains the test result of the PCIE signal port to be tested connected to the any first PCIE signal port based on the response status information.

9. The test fixture according to claim 6, characterized in that: The data bus port is an I2C data bus port.

10. The test fixture according to claim 1, characterized in that: The number of the PCIE signal ports to be tested connected to the first PCIE signal port is determined based on the number of data channels of the first PCIE signal port and the number of data channels of the PCIE signal port to be tested.

11. The test fixture according to claim 1, characterized in that: Also includes: Power supply interface and power supply conversion module; The input end of the power supply interface is connected to the power supply, and the output end of the power supply interface is connected to the power supply conversion module.

12. The test fixture according to any one of claims 1 to 11, characterized in that: The first end of the first PCIE signal port is plug-connected to the PCIE signal port to be tested, and the third end of each of the second PCIE signal ports is plug-connected to a PCIE card.

13. A testing system, characterized in that: include: A test fixture and a plurality of PCIE cards as claimed in any one of claims 1 to 12; the number of the test fixtures is determined based on the number of PCIE signal ports to be tested in the electronic device to be tested; and the third end of each second PCIE signal port in the test fixture is connected to one of the PCIE cards.

14. The test system according to claim 13, characterized in that: Also includes: processor; The processor is connected to each of the PCIE cards; The processor is used to obtain a response state of the PCIE card after responding to the PCIE signal and the clock source signal sent by the test fixture, and then obtain a test result of the PCIE signal port to be tested based on the response state.

15. A test method implemented based on the test system according to claim 13 or 14, characterized in that: When a PCIE signal port to be tested in the electronic device to be tested is connected to a test fixture in the test system, the method includes: Controlling the electronic device to be tested to output a PCIE signal through the PCIE signal port to be tested, so that the test fixture sends the PCIE signal to a PCIE card in the electronic device to be tested when receiving the PCIE signal; Obtaining the operating status of the PCIE card; Based on the running status, a test result of the PCIE signal port to be tested is obtained.

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