2.5D packaging structure and 2.5D packaging method

Abstract

The present application relates to a 2.5D packaging structure and a 2.5D packaging method, and relates to the field of semiconductor packaging technology. The 2.5D packaging structure includes multiple support structures, a second substrate, and multiple chips. Each support structure includes a first substrate and a conductive column. The conductive column runs through the first substrate and protrudes from both sides of the first substrate respectively. Multiple support structures are electrically connected to the second substrate; there is a gap between adjacent support structures. Multiple chips are stacked and electrically connected to the conductive columns of the support structure. By setting gaps between the support structures, it is beneficial for the bottom filling glue to be dispersed onto the second substrate, reducing the amount of bottom filling glue accumulated at the bottom of the chip, and reducing the impact of the colloid stress on the chip.

Description

Technical Field

[0001] The present application relates to the field of semiconductor packaging technology, and in particular to a 2.5D packaging structure and a 2.5D packaging method. Background Art

[0002] In the existing 2.5D packaging structure, a large number of chips are integrated on the adapter board. Each chip needs to be glued at the bottom, that is, the bottom filler is formed. The more chips are integrated, the more glue the bottom filler accumulates. The greater the impact of the colloid structural stress on the adapter board and the colloid stress on the bottom chip. It is easy to cause the bottom chip to crack or fail due to the structural stress generated by the colloid. Summary of the invention

[0003] The purpose of the present application is to provide a 2.5D packaging structure and a 2.5D packaging method, which can improve the structural strength, disperse the accumulated glue amount of the bottom chip, and improve the packaging quality.

[0004] In order to achieve the above objectives:

[0005] In a first aspect, the present invention provides a 2.5D packaging structure, comprising:

[0006] A plurality of support structures, each of the support structures comprising a first substrate, a first barrier layer, a second barrier layer and a conductive column; the first barrier layer and the second barrier layer are located on both sides of the first substrate; the conductive column penetrates the first barrier layer, the first substrate and the second barrier layer, and protrudes from the first barrier layer and the second barrier layer respectively;

[0007] a second substrate, a plurality of the support structures being electrically connected to the second substrate; gaps being provided between adjacent support structures; and a receiving cavity being formed between the first substrate and the second substrate and communicating with the gaps;

[0008] A plurality of HBM chips are stacked and electrically connected to the conductive pillars of the support structure.

[0009] In an optional embodiment, a group of stacked HBM chips are arranged on a side of each supporting structure away from the second substrate, and a bridge chip is provided between at least two adjacent groups of stacked HBM chips, and the bridge chip is electrically connected to at least one of the multiple stacked HBM chips in each group.

[0010] In an optional embodiment, the bridge chip includes one or more stacked HBM chips.

[0011] In an optional embodiment, the conductive pillar includes a first conductive pillar, a second conductive pillar, a third conductive pillar and a fourth conductive pillar, the second conductive pillar and the third conductive pillar are used to electrically connect the HBM chip; the fourth conductive pillar of one of the support structures and the first conductive pillar of another adjacent support structure are used to electrically connect the bridge chip.

[0012] In an optional embodiment, the support structure includes a bottom support structure and an intermediate support structure, the bottom support structure is electrically connected to the second substrate; the side of the bottom support structure away from the second substrate is connected to the stacked HBM chips; the side of the HBM chip away from the bottom support structure is connected to the intermediate support structure.

[0013] In an optional embodiment, the intermediate supporting structure is arranged corresponding to the gap between the adjacent bottom supporting structures.

[0014] In an optional embodiment, a stacked chip is provided between the intermediate support structure and the bottom support structure, the stacked chip includes at least one upright chip and at least one flip chip, the upright chip is electrically connected to a conductive column on a side of the intermediate support structure close to the bottom support structure, and the flip chip is electrically connected to a conductive column on a side of the bottom support structure close to the intermediate support structure;

[0015] The face-up chip and the flip-chip are electrically connected directly or indirectly.

[0016] In an optional implementation, the HBM chip is connected to a side of the intermediate support structure away from the bottom support structure.

[0017] In an optional embodiment, at least one groove area is formed on a side of the intermediate support structure close to the bottom support structure.

[0018] In an optional embodiment, a plurality of the intermediate support structures are staggered and stacked to form a multilayer structure, and the number of the intermediate support structures in each layer is different. The closer a layer is to the second substrate, the fewer the number of the intermediate support structures is; and the number of the intermediate support structures increases layer by layer in a direction away from the second substrate.

[0019] In an optional embodiment, the first layer includes one intermediate support structure, the second layer includes two intermediate support structures, the two intermediate support structures of the second layer are respectively connected to the conductive pillars at both ends of the intermediate support structure of the first layer; the two intermediate support structures of the second layer form a groove area on the side close to the second substrate.

[0020] In an optional embodiment, an HBM chip is provided on the intermediate support structure of the first layer, and the HBM chip is located between two intermediate support structures of the second layer;

[0021] And / or, at least one of the two intermediate support structures of the second layer is provided with an HBM chip.

[0022] In an optional embodiment, an electronic component spaced apart from the support structure is further disposed on the second substrate.

[0023] In a second aspect, the present invention provides a 2.5D packaging method for preparing a 2.5D packaging structure as described in any one of the aforementioned embodiments.

[0024] Through the above technical solution, multiple support structures are provided on the second substrate, and the HBM chips are stacked on the support structures to improve the strength of the packaging structure. There are gaps between adjacent support structures, and the bottom filling glue can partially enter the gap and flow onto the second substrate, so that the bottom filling glue accumulated by the bottom HBM chip can be shared, reducing the impact of the colloid stress on the bottom chip and improving the packaging quality.

[0025] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 A schematic diagram of a first structural embodiment of the packaging structure provided in the present application;

[0028] Figure 2 A schematic diagram of a support structure of a packaging structure provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of an HBM chip with a packaging structure provided in an embodiment of the present application;

[0030] Figure 4 A second structural schematic diagram of the packaging structure provided in an embodiment of the present application;

[0031] Figure 5 A third structural schematic diagram of the packaging structure provided in the embodiment of the present application;

[0032] Figure 6A fourth structural schematic diagram of the packaging structure provided in an embodiment of the present application;

[0033] Figure 7 A fifth structural schematic diagram of the packaging structure provided in the embodiment of the present application;

[0034] Figure 8 A sixth structural schematic diagram of the packaging structure provided in an embodiment of the present application.

[0035] Icons: 110-support structure; 111-first substrate; 112-conductive column; 113-barrier layer; 121-first conductive column; 122-second conductive column; 123-third conductive column; 124-fourth conductive column; 125-gap; 126-bottom filling glue; 127-accommodating cavity; 130-second substrate; 131-HBM chip; 132-metal column; 133-solder joint; 135-bridge chip; 136-groove area; 140-electronic component; 141-bottom support structure; 143-middle support structure; 151-upright chip; 152-flip chip; 161-first base support; 162-second base support; 163-third base support; 164-fourth base support; 171-first layer middle support structure; 172-second layer middle support structure; 173-third layer middle support structure; 180-plastic package. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0037] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0038] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0039] Combination Figure 1 and Figure 2 The 2.5D packaging structure provided in the present application includes a plurality of support structures 110, a second substrate 130 and a plurality of chips. In this embodiment, the chip is an HBM chip 131 as an example. Of course, in other embodiments, the chip can also be other types of chips, which are not specifically limited here.

[0040] Each support structure 110 includes a first substrate 111 and a conductive column 112. The conductive column 112 penetrates the first substrate 111 and protrudes from both sides of the first substrate 111. Multiple support structures 110 are electrically connected to the second substrate 130. There is a gap 125 between adjacent support structures 110. A receiving cavity 127 connected to the gap 125 is formed between the first substrate 111 and the second substrate 130. Multiple HBM chips 131 are stacked and electrically connected to the conductive column 112 of the support structure 110. By providing the support structure 110, the reliability and structural strength of the second substrate 130 and the entire packaging structure can be improved, and the bearing capacity of the stacked chips is better. The gap 125 is provided between the support structures 110, which is conducive to the dispersion of the bottom filling glue 126 on the second substrate 130, reduces the amount of the bottom filling glue 126 accumulated at the bottom of the HBM chip 131, and reduces the influence of the colloid stress on the HBM chip 131.

[0041] It should be noted that the second substrate 130 is provided with many precision wirings, and the wiring wire diameter is small and the density is high. If a large number of chips are stacked directly on the second substrate 130, since there is a bottom filler 126 under each layer of chips, a large amount of colloid (bottom filler 126) will accumulate on the second substrate 130, thereby generating a large structural stress. The large colloid structural stress not only threatens the integrity and reliability of the underlying chip, but also affects the second substrate 130, and easily causes the internal wiring to break or severely deform, thereby causing short circuits or breaks, etc., causing circuit failure, affecting the reliability of the package. Therefore, in this embodiment, a support structure 110 is provided, which can improve the structural strength and bearing capacity, and the structure is more stable and reliable. In addition, the support structure 110 shares and bears a large amount of colloid stress, reduces the amount of glue on the second substrate 130, and thus reduces the impact of the colloid stress on the second substrate 130. In addition, there is a gap 125 between the support structures 110, which is conducive to improving the fluidity of the colloid. The bottom filler 126 will partially enter the gap 125 and disperse onto the second substrate 130. This reduces the amount of glue under the bottom chip and reduces the impact of glue stress on the bottom chip. The bottom filling glue 126 is dispersed on the second substrate 130 and the support structure 110, which protects both the bottom chip and the second substrate 130. It can be understood that the bottom filling glue 126 is provided on both sides of the support structure 110, and the stress of the glue can be partially offset, thereby reducing the destructiveness of the glue stress.

[0042] It should be noted that the gap 125 is relatively small relative to the length of the entire support structure 110 , so most of the bottom filling glue 126 is still concentrated on the support structure 110 , and the support structure 110 absorbs and bears most of the glue stress.

[0043] It should be noted that, on the first substrate 111, since the conductive pillars 112 penetrate and protrude from the first substrate 111, after the conductive pillars 112 are electrically connected to the second substrate 130, there is a receiving cavity 127 of a certain height between the first substrate 111 and the second substrate 130, and the receiving cavity 127 can accommodate a portion of the bottom filling glue 126 and is also conducive to improving the heat dissipation performance. In addition, the plurality of conductive pillars 112 divide the receiving cavity 127 into a plurality of sub-cavities, which is conducive to improving the fluidity and filling properties of the colloid.

[0044] Optionally, a barrier layer 113 is provided on at least one side surface of the first substrate 111, and the conductive column 112 penetrates the barrier layer 113 and the first substrate 111, and protrudes from the barrier layer 113 and the first substrate 111. This arrangement can further improve the structural strength and bearing capacity, and the ability to resist colloid stress damage is stronger. In this embodiment, the barrier layer 113 is respectively provided on two surfaces of the first substrate 111. Of course, in some optional embodiments, the barrier layer 113 can also be formed only on one surface of the first substrate 111, which is not specifically limited here.

[0045] In this embodiment, the stacked chips are high bandwidth memory chips, that is, HBM chips 131, where HBM is the abbreviation of High Bandwidth Memory. Of course, this is not limited to this, and other types of chips may also be used.

[0046] Optionally, the barrier layer 113 is made of a shielding material that can prevent X-rays from passing through, such as at least one of lead, gold, silver and copper. In this way, when the welding quality of the package structure is tested, the barrier layer 113 can be used to block X-rays to prevent the X-rays from meeting the HBM chip 131 and generating a photoelectric effect to damage the HBM chip 131. During the test, the package structure can be inverted or placed upright according to the position of the support structure 110, so that the barrier layer 113 in the support structure 110 can effectively block X-rays.

[0047] Optionally, a group of stacked HBM chips 131 is arranged on one side of each support structure 110 away from the second substrate 130. The number of stacked HBM chips 131 is not limited and can be designed according to actual needs. The number can be several, dozens, hundreds or thousands. The stacking form is not limited to normal stacking or misaligned stacking. If normal stacking is adopted, the integration density can be improved. If misaligned stacking is adopted, the heat dissipation performance can be improved, and the bonding between the plastic package 180 and the chip can be improved. Of course, normal stacking and misaligned stacking can also be included at the same time.

[0048] The number of support structures 110 on the second substrate 130 is not limited, and can be several, dozens, dozens or hundreds, etc. A bridge chip 135 is provided between at least two adjacent groups of stacked HBM chips 131, and the bridge chip 135 is electrically connected to at least one of the multiple HBM chips 131 in each group of stacks. Of course, a bridge chip 135 can also be provided between each two adjacent groups of stacked HBM chips 131, or the bridge chip 135 is only provided between some of the two groups of stacked HBM chips 131. The bridge chip 135 can be an HBM chip 131 or other types of chips. The bridge chip 135 can be one or multiple stacked ones, which is not specifically limited here. In this embodiment, the bridge chip 135 includes one or more stacked HBM chips 131.

[0049] It can be understood that the conductive pillars 112 are distributed in an array on the first substrate 111 . Figure 2 It is illustrated that each support structure 110 includes a plurality of rows and four columns of conductive pillars 112. Optionally, the four columns of conductive pillars 112 include a first conductive pillar 121, a second conductive pillar 122, a third conductive pillar 123 and a fourth conductive pillar 124. Among them, the first conductive pillar 121 and the fourth conductive pillar 124 are relatively located at the edge, and the second conductive pillar 122 and the third conductive pillar 123 are relatively located in the middle. The second conductive pillar 122 and the third conductive pillar 123 are used to electrically connect the HBM chip 131. It can be understood that one of the two solder joints 133 of the HBM chip 131 is electrically connected to the second conductive pillar 122, and the other is electrically connected to the third conductive pillar 123. The first conductive pillar 121 and the fourth conductive pillar 124 are relatively located at the edge, and have a certain glue blocking effect, which can retain a large amount of colloid above the support structure 110 and reduce the bottom filling glue 126 entering the second substrate 130. In this embodiment, the fourth conductive pillar 124 of one supporting structure 110 and the first conductive pillar 121 of another adjacent supporting structure 110 are used to electrically connect the bridge chip 135 . That is, the bridge chip 135 is stacked above the gap 125 between the two supporting structures 110 .

[0050] In addition, the conductive pillars 112 can also improve the bonding strength between the bottom filling glue 126 and the first substrate 111 and the chip, and the bonding strength between the plastic package 180 and the first substrate 111 and the chip.

[0051] Combination Figure 3 Optionally, each HBM chip 131 has a metal column 132 that runs through the chip, that is, there are solder joints 133 on both the front and back sides of the HBM chip 131. When stacked, the solder joints 133 on the front side of the upper HBM chip 131 are directly soldered to the solder joints 133 on the back side of the lower HBM chip 131. The transmission path is short, the transmission efficiency is high, and the reading and writing speed is fast.

[0052] It should be noted that the stacking height of the bridge chip 135 is less than or equal to the height of the stacked chips above the second conductive column 122 and the third conductive column 123. If the number of chips stacked above the second conductive column 122 and the third conductive column 123 is N, N is a natural number greater than or equal to 1. Then the stacking number of bridge chips 135 between the two groups of stacked chips can be less than or equal to N. If the stacking number of bridge chips 135 is less than N, a groove area 136 will be left above the gap 125. The groove area 136 can be located at any position at the bottom, middle or top of the stacking height. The groove area 136 is conducive to improving the fluidity of the colloid, heat dissipation, and improving the filling property of the plastic package 180 and the bonding force between the plastic package 180 and the chip.

[0053] Optionally, an electronic component 140 is further disposed on the second substrate 130 and is spaced apart from the support structure 110. The electronic component 140 includes but is not limited to at least one of a chip, a capacitor, a resistor and other components.

[0054] Combination Figure 4 Optionally, the support structure 110 includes a bottom support structure 141 and an intermediate support structure 143. The bottom support structure 141 and the intermediate support structure 143 have the same structure, but the spatial distribution positions are different. The bottom support structure 141 is electrically connected to the second substrate 130. The side of the bottom support structure 141 away from the second substrate 130 is connected to the stacked HBM chip 131; the side of the HBM chip 131 away from the bottom support structure 141 is connected to the intermediate support structure 143. Among them, the number of bottom support structures 141 is not limited. The number of intermediate support structures 143 is not limited, and the intermediate support structure 143 can also have multiple layers. The multiple layers can be arranged adjacent to each other or at intervals, which is not specifically limited here.

[0055] Optionally, the intermediate support structure 143 is arranged corresponding to the gap 125 between the adjacent bottom support structures 141. In this embodiment, only one intermediate support structure 143 is shown. Among them, the two bottom support structures 141 respectively stack HBM chips 131 on the second conductive pillar 122 and the third conductive pillar 123, that is, two groups of HBM chips 131 are formed. Each group includes two HBM chips 131. Above the two groups of HBM chips 131, an intermediate support structure 143 is stacked. The lower parts of the first conductive pillar 121 and the fourth conductive pillar 124 of the intermediate support structure 143 are electrically connected to the two groups of HBM chips 131 respectively. In this way, a groove area 136 is formed below the second conductive pillar 122 and the third conductive pillar 123 of the intermediate support structure 143, which is conducive to improving the heat dissipation efficiency and the fluidity of the colloid.

[0056] Optionally, at least one groove area 136 is formed on one side of the intermediate support structure 143 close to the bottom support structure 141. It can be understood that if the number of each group of HBM chips 131 is greater and the stacking height is higher, the height of the groove area 136 is higher. If one or more bridge chips 135 are mounted in the groove area 136. For example, if multiple bridge chips 135 are spaced apart in the height direction, multiple groove areas 136 can be formed.

[0057] Optionally, an HBM chip 131 is connected to the side of the intermediate support structure 143 away from the bottom support structure 141, which can improve the chip integration. Optionally, a group of HBM chips 131 can be mounted above the intermediate support structure 143, and the group of HBM chips 131 is electrically connected to the second conductive column 122 and the third conductive column 123 on the upper side of the intermediate support structure 143. The first conductive column 121 and the fourth conductive column 124 next to it can improve the heat dissipation performance. It can also serve as a glue blocking effect. The setting of the intermediate support structure 143 can partially block the bottom filling glue 126 above the intermediate support structure 143. Thereby dispersing the colloid stress and reducing the impact of the colloid stress on the chip.

[0058] It should be noted that in the stacked structure, at least a portion of the conductive pillars of the support structure 110 extend into the trench region 136, for example Figure 4 In the figure, the fourth conductive column 124 of the left bottom support structure 141, the first conductive column 121 of the right bottom support structure 141, and the lower ends of the second conductive column 122 and the third conductive column 123 of the middle support structure 143. In this way, the groove area 136 can be divided into multiple flow channels, which is beneficial to improve the fluidity of the colloid or plastic package 180, thereby improving the filling property of the colloid or plastic package 180, and improving the structural bonding force and reliability.

[0059] Combination Figure 5 Alternatively, in some embodiments, two groups of HBM chips 131 may be mounted on the intermediate support structure 143, wherein one group of HBM chips 131 is electrically connected to the first conductive pillar 121 and the second conductive pillar 122 on the upper side of the intermediate support structure 143, and the other group of HBM chips 131 is electrically connected to the third conductive pillar 123 and the fourth conductive pillar 124 on the upper side of the intermediate support structure 143. The number of each group of HBM chips 131 is not limited and may be one or more. This arrangement can improve the chip integration and the computing power of the HBM chip 131.

[0060] Combination Figure 6 Optionally, a stacked chip is provided between the intermediate support structure 143 and the bottom support structure 141, and the stacked chip includes at least one upright chip 151 and at least one flip chip 152, the upright chip 151 is electrically connected to the conductive column 112 on the side of the intermediate support structure 143 close to the bottom support structure 141, and the flip chip 152 is electrically connected to the conductive column 112 on the side of the bottom support structure 141 close to the intermediate support structure 143. The upright chip 151 and the flip chip 152 are electrically connected directly or indirectly. In other words, the upright chip 151 and the flip chip 152 are mounted back to back. The upright chip 151 and the flip chip 152 in this embodiment respectively use the HBM chip 131. Only two stacked chips are shown in the figure, and in some embodiments, the number of stacked chips can be more.

[0061] Combination Figure 7 Optionally, multiple intermediate support structures 143 are stacked in a staggered manner to form a multi-layer structure, and the number of intermediate support structures 143 in each layer is different. The closer the layer is to the second substrate 130, the fewer the number of intermediate support structures 143 is; the number of intermediate support structures 143 increases layer by layer in a direction away from the second substrate 130. In this way, the multi-layer intermediate support structure 143 builds more chip mounting space for the top, which is conducive to integrating more chips and improving chip integration.

[0062] Optionally, the first intermediate support structure 171 includes one, the second intermediate support structure 172 includes two, the two second intermediate support structures 143 are respectively connected to the conductive pillars 112 at both ends of the first intermediate support structure 143; the two second intermediate support structures 143 form a groove area 136 on one side close to the second substrate 130. Only two intermediate support structures 143 are shown in the figure.

[0063] In the illustrated structure of this embodiment, the bottom support structure 141 includes a first base support 161, a second base support 162, a third base support 163 and a fourth base support 164. Five HBM chips 131 are stacked on the middle part (the second conductive pillar 122 and the third conductive pillar 123) of the first base support 161. Two HBM chips 131 are stacked on the middle part (the second conductive pillar 122 and the third conductive pillar 123) of the second base support 162. Four HBM chips 131 are stacked above the gap 125 between the first base support 161 and the second base support 162. The chip stacking structure on the third base support 163 and the fourth base support 164 is the same as the chip stacking structure on the first base support 161 and the second base support 162, and is arranged in a left-right symmetrical manner with respect to the gap 125 between the second base support 162 and the third base support 163.

[0064] The first intermediate support structure 171 is disposed above the gap 125 between the second base support 162 and the third base support 163, wherein the first conductive column 121 is electrically connected to the HBM chip 131 on the second base support 162, the fourth conductive column 124 is electrically connected to the HBM chip 131 on the third base support 163, and a groove area 136 is formed below the second conductive column 122 and the third conductive column 123.

[0065] The second intermediate support structure 172 includes two. The fourth conductive column 124 of the left intermediate support structure 143 is electrically connected to the first conductive column 121 of the first intermediate support structure 171, and the first conductive column 121 and the second conductive column 122 are connected to the two solder joints 133 of the bridge chip 135 above the gap 125 between the first base support 161 and the second base support 162. A groove area 136 is formed below the third conductive column 123. The intermediate support structure 143 on the right is symmetrical with the intermediate support structure 143 on the left. This arrangement can not only improve the heat dissipation performance, but also improve the bonding force between the plastic package 180 and the chip.

[0066] It is worth noting that the intermediate support structure 143 is distributed in a similar fan-shaped manner. That is, the farther away from the second substrate 130, the number of intermediate support structures 143 in each layer gradually increases, so that more groove areas 136 are formed. In addition, a portion of the conductive column extends into each groove area 136 to form a flow channel, which can improve the fluidity and filling properties of the colloid and the plastic package 180. Multiple groove areas 136 can be distributed symmetrically, or they can be distributed in a positive or misaligned manner, which is not specifically limited here.

[0067] It is easy to understand that, due to the formation of multiple groove areas 136, the fluidity and filling property of the plastic package 180 are greatly improved, so it is only necessary to set the bottom filling glue 126 on the bottom support structure 141 and the bottom stacked chip. The rest of the place can be filled by the plastic package 180, and the filling effect is good. In this way, a large number of process steps for forming the bottom filling glue 126 can be omitted, the amount of colloid used can be saved, and the structural stress caused by the colloid can be reduced.

[0068] Optionally, an HBM chip 131 is provided on the intermediate support structure 143 of the first layer, and the HBM chip 131 is located between two intermediate support structures 143 of the second layer. Alternatively, at least one of the two intermediate support structures 143 of the second layer is provided with an HBM chip 131. Alternatively, all intermediate support structures 143 are provided with an HBM chip 131, which is not specifically limited here.

[0069] Optionally, the lower end of the fourth conductive column 124 of the second-layer intermediate support structure 172 is electrically connected to the upper end of the first conductive column 121 of the first-layer intermediate support structure 171, and the HBM chip 131 is stacked on the upper end of the fourth conductive column 124 of the second-layer intermediate support structure 172, which is also beneficial to improving the computing power of the stacked HBM chip 131.

[0070] Combination Figure 8It can be understood that if the third intermediate support structure 173 is continuously arranged on the second intermediate support structure 172, there can be two third intermediate support structures 173, and the lower end of the fourth conductive column 124 of the third intermediate support structure 173 on the left is electrically connected to the upper end of the first conductive column 121 of the second intermediate support structure 172 on the left. The lower end of the first conductive column 121 of the third intermediate support structure 173 on the right is electrically connected to the upper end of the fourth conductive column 124 of the second intermediate support structure 172 on the right. By analogy, each layer can be two, respectively connected to the leftmost conductive column 112 and the rightmost conductive column 112, forming a fan-shaped structure.

[0071] Alternatively, the first intermediate structure layer includes one; the second intermediate structure layer includes two, which are respectively arranged at the two ends of the first intermediate support structure 171; the third intermediate support structure 173 includes at least two, which are respectively arranged at the two ends of the second intermediate support structure 172; the fourth intermediate support structure 143 and above include at least two, which are respectively arranged at the two ends of the next intermediate support structure 143, and the remaining multiple are arranged at intervals in the middle of the next intermediate support structure 143. For example, the number of intermediate support structures 143 in each layer is different, and the closer to the second substrate 130, the fewer the number of intermediate support structures 143; the number of intermediate support structures 143 increases layer by layer in the direction away from the second substrate 130.

[0072] Specifically, the first intermediate support structure 171 includes one, and the second intermediate support structure 172 includes two, which are respectively arranged at the two ends of the first intermediate support structure 171. The third intermediate support structure 173 includes three, two of which are respectively arranged at the two ends of the second intermediate support structure 172, and the remaining one is arranged in the middle. The fourth intermediate support structure 143 includes four, two of which are respectively arranged at the two ends of the third intermediate support structure 173, and the remaining two are evenly spaced in the middle. And so on, a fan-shaped structure is formed.

[0073] Such a stacking method can provide more chip stacking space and improve integration. In the height direction of the stack, multiple groove areas 136 are staggered and distributed, which can provide more heat dissipation space and improve heat dissipation performance. And the structural stress of the colloid is evenly dispersed to multiple support structures 110, reducing the impact of the colloid stress on the chip and the entire structure. In addition, the use of the support structure 110 as a mounting method can avoid the traditional TSV perforation technology, thereby avoiding the defects caused by the TSV perforation technology.

[0074] Optionally, a plastic package 180 is further disposed on the second substrate 130, and the plastic package 180 encapsulates all devices on the second substrate 130. Of course, in some embodiments, the plastic package 180 may also be omitted, which is not specifically limited here.

[0075] An embodiment of the present invention further provides a 2.5D packaging method for preparing the aforementioned 2.5D packaging structure.

[0076] In summary, the 2.5D packaging structure and 2.5D packaging method provided by the embodiments of the present invention have the following beneficial effects:

[0077] A plurality of support structures 110 are provided on the second substrate 130, and the HBM chip 131 is stacked on the support structure 110 to improve the strength of the packaging structure. There is also a gap 125 between adjacent support structures 110, and the bottom filling glue 126 can partially enter the gap 125 and flow onto the second substrate 130, so that the bottom filling glue 126 accumulated by the bottom HBM chip 131 can be shared, reducing the impact of the colloid stress on the bottom chip and the second substrate 130, and improving the packaging quality. The plurality of support structures 110 are stacked in an offset manner to form a groove area 136, which is conducive to improving the fluidity of the colloid, improving the heat dissipation performance, improving the integration, uniformly dispersing the colloid stress, and improving the bonding force between the plastic package 180 and the chip, thereby improving the packaging quality.

[0078] It should be noted that, in the absence of conflict, the features in the embodiments of this application may be combined with each other.

[0079] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A 2.5D packaging structure, characterized in that: include: a plurality of support structures, each of the support structures comprising a first substrate and a conductive pillar; The conductive pillars penetrate the first substrate and protrude from two sides of the first substrate respectively; a second substrate, a plurality of the support structures being electrically connected to the second substrate; gaps being provided between adjacent support structures; and a receiving cavity being formed between the first substrate and the second substrate and communicating with the gaps; A plurality of chips, wherein the plurality of chips are stacked and electrically connected to the conductive pillars of the support structure; The support structure comprises a bottom support structure and an intermediate support structure, wherein the bottom support structure is electrically connected to the second substrate; a side of the bottom support structure away from the second substrate is connected to the stacked chips; a side of the chip away from the bottom support structure is connected to the intermediate support structure; The plurality of intermediate support structures are stacked in an offset manner to form a multilayer structure, and the number of the intermediate support structures in each layer is different. The closer a layer is to the second substrate, the fewer the number of the intermediate support structures is; and the number of the intermediate support structures increases layer by layer in a direction away from the second substrate; Alternatively, the first intermediate structure layer includes one; the second intermediate structure layer includes two, which are respectively arranged at the two ends of the first intermediate support structure; the third intermediate support structure includes at least two, at least two of which are respectively arranged at the two ends of the second intermediate support structure; the fourth intermediate support structure and above include at least two, at least two of which are respectively arranged at the two ends of the next intermediate support structure, and the remaining multiple ones are arranged at intervals in the middle of the next intermediate support structure.

2. The 2.5D packaging structure according to claim 1, characterized in that: The chip includes an HBM chip; a group of stacked HBM chips is arranged on a side of each support structure away from the second substrate, and a bridge chip is arranged between at least two adjacent groups of stacked HBM chips, and the bridge chip is electrically connected to at least one of the multiple stacked HBM chips in each group.

3. The 2.5D packaging structure according to claim 2, characterized in that: The bridge chip includes one or more stacked HBM chips.

4. The 2.5D packaging structure according to claim 2, characterized in that: The conductive pillars include a first conductive pillar, a second conductive pillar, a third conductive pillar and a fourth conductive pillar, wherein the second conductive pillar and the third conductive pillar are used to electrically connect the HBM chip; the fourth conductive pillar of one of the support structures and the first conductive pillar of another adjacent support structure are used to electrically connect the bridge chip.

5. The 2.5D packaging structure according to claim 1, characterized in that: The intermediate support structure is arranged correspondingly to the gap between the adjacent bottom support structures.

6. The 2.5D packaging structure according to claim 5, characterized in that: A stacked chip is provided between the intermediate support structure and the bottom support structure, the stacked chip includes at least one upright chip and at least one flip chip, the upright chip is electrically connected to a conductive column on a side of the intermediate support structure close to the bottom support structure, and the flip chip is electrically connected to a conductive column on a side of the bottom support structure close to the intermediate support structure; The face-up chip and the flip-chip are electrically connected directly or indirectly.

7. The 2.5D packaging structure according to claim 1, characterized in that: The chip is connected to a side of the intermediate supporting structure away from the bottom supporting structure.

8. The 2.5D packaging structure according to claim 1, characterized in that: At least one groove region is formed on a side of the intermediate support structure close to the bottom support structure.

9. The 2.5D packaging structure according to claim 1, characterized in that: The first layer intermediate support structure includes one, the second layer intermediate support structure includes two, the two second layer intermediate support structures are respectively connected to the conductive pillars at both ends of the first layer intermediate support structure; the two second layer intermediate support structures form a groove area on one side close to the second substrate.

10. The 2.5D packaging structure according to claim 9, characterized in that: An HBM chip is arranged on the intermediate support structure of the first layer, and the HBM chip is located between two intermediate support structures of the second layer; And / or, at least one of the two intermediate support structures of the second layer is provided with an HBM chip.

11. The 2.5D packaging structure according to claim 1, characterized in that: A barrier layer is disposed on at least one side surface of the first substrate, and the conductive column penetrates the barrier layer and the first substrate and protrudes from the barrier layer and the first substrate.

12. The 2.5D packaging structure according to any one of claims 1 to 11, characterized in that: The second substrate is also provided with electronic components spaced apart from the support structure.

13. A 2.5D packaging method, characterized in that: Used to prepare the 2.5D packaging structure as claimed in any one of claims 1 to 12.

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