Chip packaging structure, chip packaging method and circuit system

Abstract

The embodiments of the present application relate to the field of semiconductor device technology, and in particular to a chip packaging structure, a chip packaging method and a circuit system, wherein the chip packaging structure includes a wafer, a surface metal layer, a first polymer layer, a redistribution layer, a second polymer layer and an under-ball metal layer stacked in sequence; wherein the surface metal layer includes a pad, the first polymer layer has a first through hole, and the redistribution layer is electrically connected to the pad through the first through hole; the second polymer layer has a second through hole, and the under-ball metal layer is electrically connected to the redistribution layer through the second through hole. The distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1; when the first distance d1 satisfies d1≤200μm, a plurality of first grooves arranged at intervals are opened on the first edge, and the second polymer layer is connected to the first polymer layer through the first groove, then the first groove forms an anchoring effect and forms a stress relief area, thereby reducing the risk of short circuit caused by deformation of the redistribution layer.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor device technology, and in particular to a chip packaging structure, a chip packaging method and a circuit system. Background Art

[0002] In today's highly information-based and digital era, chip technology, as the core of electronic technology, plays a vital role. Chip packaging, such as wafer-level chip scale packaging (WLCSP) is the most compact packaging form, with thermal and electrical performance superior to wire bonding and other interposer packaging technologies. Among them, the chip includes a wafer, a surface metal layer, a first polymer layer, a redistribution layer, a second polymer layer, and an under-ball metal layer stacked in sequence; the redistribution layer (RDL) contacts the pads on the surface metal layer through a through hole. The under-ball metal layer is electrically connected to the redistribution layer, and solder balls are set on the under-ball metal layer for electrical connection to external devices.

[0003] In the process of implementing the present application, the applicant discovered that: currently, when the redistribution layer is warped due to temperature changes, external forces, etc., the redistribution layer causes the first polymer layer to deform, which can easily cause cracking of the first polymer layer and short circuit of the surface metal layer, resulting in chip failure. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a chip packaging structure, a chip packaging method and a circuit system, which overcome the above problems or at least partially solve the above problems.

[0005] According to one aspect of an embodiment of the present application, a chip packaging structure is provided, comprising a wafer, a surface metal layer, a first polymer layer, a redistribution layer, a second polymer layer and an under-ball metal layer stacked in sequence; the surface metal layer comprises a solder pad, the first polymer layer has a first through hole, and the redistribution layer is electrically connected to the solder pad through the first through hole; the second polymer layer has a second through hole, and the under-ball metal layer is electrically connected to the redistribution layer through the second through hole, and a solder ball is arranged on the under-ball metal layer, and the solder ball is used to electrically connect to an external device; the distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1; when the first distance d1 satisfies d1≤200μm, a first edge of the redistribution layer is provided with a plurality of first grooves arranged at intervals, and the second polymer layer is connected to the first polymer layer through the first grooves.

[0006] In an optional manner, a distance between two adjacent first grooves is not less than 20 μm; a distance between the first groove and a second edge of the redistribution layer is not less than 20 μm, wherein the first edge intersects with the second edge.

[0007] In an optional manner, the length of the first groove is 20 μm; the width b1 of the first groove satisfies 20 μm≤b1≤60 μm.

[0008] In an optional manner, the thickness of the redistribution layer is 10 μm.

[0009] In an optional manner, the material of the second polymer layer is the same as that of the first polymer layer.

[0010] In an optional manner, along a first direction, the first groove has a first projection, the surface metal layer has a second projection, and the second projection completely covers the first projection; wherein the first direction is the direction from the surface metal layer to the redistribution layer.

[0011] In an optional manner, the distance from the second edge of the redistribution layer to the edge of the surface metal layer is a second distance d2; when the second distance d2 satisfies d2≤200μm, a plurality of second grooves arranged at intervals are opened at the second edge of the redistribution layer, and the second polymer layer is connected to the first polymer layer through the second grooves.

[0012] In an optional manner, a distance between two adjacent second grooves is not less than 20 μm; and a distance between the second groove and the first edge is not less than 20 μm.

[0013] In an optional manner, the length of the second groove is 20 μm; the width b2 of the second groove satisfies 20 μm≤b2≤60 μm.

[0014] In an optional manner, along the first direction, the second groove has a third projection, the surface metal layer has a second projection, and the second projection completely covers the third projection; wherein the first direction is the direction from the surface metal layer to the redistribution layer.

[0015] In an optional manner, when the first distance d1 ≤ 100 μm and / or the second distance d2 ≤ 100 μm, the redistribution layer is further provided with a plurality of stress release holes arranged at intervals, and the second polymer layer is connected to the first polymer layer through the stress release holes.

[0016] In an optional manner, a distance between two adjacent stress release holes is not less than 20 μm; and a distance between the stress release hole and an edge of the redistribution layer is not less than 40 μm.

[0017] In an optional manner, the stress release hole is a rectangular hole, and the length of the stress release hole is 20 μm; the width b3 of the stress release hole satisfies 20 μm≤b3≤60 μm.

[0018] In an optional manner, along the first direction, the stress release hole has a fourth projection, the surface metal layer has a second projection, and the second projection completely covers the fourth projection; wherein the first direction is the direction from the surface metal layer to the redistribution layer.

[0019] According to one aspect of an embodiment of the present application, a chip packaging method is provided, comprising: depositing a first polymer layer on a surface metal layer on a wafer; forming a first through hole in the first polymer layer to expose a pad located on the surface metal layer of the wafer; forming a redistribution layer on the first polymer layer, the redistribution layer being electrically connected to the pad through the first through hole, the distance from a first edge of the redistribution layer to an edge of the surface metal layer being a first distance d1, and when the first distance d1 satisfies d1≤200μm, the first edge of the formed redistribution layer has a plurality of first grooves arranged at intervals; depositing a second polymer layer, the second polymer layer being connected to the first polymer layer through the first groove; forming a second through hole in the second polymer layer; forming an under ball metal layer at the second through hole, the under ball metal layer being electrically connected to the redistribution layer; and arranging solder balls on the under ball metal layer, the solder balls being used to electrically connect to external devices.

[0020] In an optional manner, the step of forming a redistribution layer on the first polymer layer further includes: opening the first groove at a first edge of the redistribution layer at a position not less than 20 μm away from a second edge of the redistribution layer, and opening the first groove at a position at an interval of not less than 20 μm, wherein the first edge intersects with the second edge.

[0021] In an optional manner, the distance from the second edge of the redistribution layer to the edge of the surface metal layer is a second distance d2, and the second edge intersects with the first edge. When the second distance d2 satisfies ≤200μm, a plurality of second grooves spaced apart are opened on the second edge of the redistribution layer so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the second grooves.

[0022] In an optional manner, when the first distance d1≤100μm and / or the second distance d2≤100μm, a plurality of stress release holes arranged at intervals are provided in the redistribution layer so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the stress release holes.

[0023] In an optional manner, the step of providing a plurality of stress release holes spaced apart in the redistribution layer further includes: forming the stress release holes at a position not less than 40 μm away from an edge of the redistribution layer, and forming the stress release holes at a position spaced apart not less than 20 μm.

[0024] According to one aspect of an embodiment of the present application, a circuit system is provided, comprising a chip of the chip packaging structure described in any one of the above, or a chip packaged by the chip packaging method described in any one of the above.

[0025] The beneficial effects of the embodiments of the present application include: providing a chip packaging structure, comprising a wafer, a surface metal layer, a first polymer layer, a redistribution layer, a second polymer layer and an under-ball metal layer stacked in sequence; wherein the surface metal layer comprises a pad, the first polymer layer has a first through hole, and the redistribution layer is electrically connected to the pad through the first through hole; the second polymer layer has a second through hole, and the under-ball metal layer is electrically connected to the redistribution layer through the second through hole, and a solder ball is arranged on the under-ball metal layer, and the solder ball is used to electrically connect to an external device. The distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1; when the first distance d1 satisfies d1≤200μm, a plurality of first grooves arranged at intervals are provided on the first edge of the redistribution layer, and the second polymer layer is connected to the first polymer layer through the first groove. That is, compared with the prior art, the chip packaging structure provided in the embodiments of the present application is further provided with a first groove. The present application realizes the connection between the second polymer layer and the first polymer layer through the first groove. The first groove forms an anchoring effect, which can improve the cohesion among the first polymer layer, the redistribution layer and the second polymer layer, thereby enhancing the binding effect of the first polymer layer and the second polymer layer on the redistribution layer. On the other hand, a stress relief area is formed at the first groove, so the redistribution layer is not easily deformed and warped due to temperature, external force, etc., so that the surface metal layer is not easily deformed by the redistribution layer, which can reduce the risk of deformation and short circuit of the surface metal layer and the risk of cracks in the first polymer layer.

[0026] In addition, the distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1. When the first distance d1 satisfies d1≤200μm, the first groove is located at the first edge, that is, the first groove is opened at the first edge of the redistribution layer only when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is ≤200μm, that is, the first groove is not set when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is greater than 200μm. Since the applicant found in the process of realizing this application that when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is greater than 200μm, the risk of deformation short circuit of the surface metal layer is small, and the risk of crack formation in the first polymer layer is small, then through the above-mentioned first distance d1 and the first groove, on the one hand, the first groove can be opened at the first edge when the first distance d1≤200μm, thereby reducing the risk of short circuit caused by deformation of the redistribution layer and reducing the risk of crack formation in the first polymer layer; on the other hand, the first groove is not opened when the first distance d1>200μm, thereby saving the processing steps of the chip packaging structure, reducing the resistance of the redistribution layer and ensuring the stability of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0028] Figure 1 is a cross-sectional view of a chip packaging structure in the prior art;

[0029] Figure 2 It is a cross-sectional effect diagram of a chip packaging structure in the prior art;

[0030] Figure 3 is a cross-sectional view of an implementation of a chip packaging structure provided in an embodiment of the present application;

[0031] Figure 4 is a schematic diagram of a redistribution layer provided in an embodiment of the present application stacked on a surface metal layer;

[0032] Figure 5 It is a schematic diagram of another implementation method of stacking the redistribution layer on the surface metal layer provided in an embodiment of the present application;

[0033] Figure 6 It is a schematic diagram of another implementation method of stacking the redistribution layer on the surface metal layer provided in the embodiment of the present application;

[0034] Figure 7 It is a schematic diagram of another implementation method of stacking the redistribution layer on the surface metal layer provided in the embodiment of the present application;

[0035] Figure 8 is a cross-sectional view of another implementation of the chip packaging structure provided in the embodiment of the present application;

[0036] Fig. 9 It is a schematic diagram of another implementation method of stacking the redistribution layer on the surface metal layer provided in the embodiment of the present application;

[0037] Fig.10 It is a schematic diagram of an implementation method in which a redistribution layer provided in an embodiment of the present application is stacked on a surface metal layer;

[0038] Fig.11 It is a schematic diagram of an extended implementation method in which a redistribution layer is stacked on a surface metal layer provided in an embodiment of the present application;

[0039] Fig.12 It is a schematic diagram of the chip packaging process provided in an embodiment of the present application.

[0040] The reference numerals are as follows:

[0041] Chip packaging structure 100p;

[0042] Wafer 10p, surface metal layer 20p, first polymer layer 30p, redistribution layer 40p, second polymer layer 50p, under ball metal layer 60p, solder ball 70p;

[0043] pad 21p, first through hole 31p, second through hole 51p;

[0044] riftg;

[0045] Chip packaging structure 100;

[0046] Wafer 10, surface metal layer 20, first polymer layer 30, redistribution layer 40, second polymer layer 50, under ball metal layer 60, solder ball 70;

[0047] Solder pad 21, first through hole 31, second through hole 51;

[0048] A first edge 401, a second edge 402;

[0049] A first groove 41, a second groove 42, and a stress release hole 43;

[0050] A first direction D1, a second direction D2, and a third direction D3;

[0051] A first distance d1, a second distance d2;

[0052] A first spacing G1, a second spacing G2, and a third spacing G3;

[0053] The first margin is E1, the second margin is E2, and the third margin is E3;

[0054] The first projection is 41s, the second projection is 20s, the third projection is 42s, and the fourth projection is 43s;

[0055] The length L1 of the first groove 41 and the width b1 of the first groove 41;

[0056] The length L2 of the second groove 42 and the width b2 of the second groove 42;

[0057] The stress release hole 43 has a length L3 and a width b3. DETAILED DESCRIPTION

[0058] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "vertical", "horizontal", "left", "right", "inside", "outside" and similar expressions used in this specification are for illustrative purposes only.

[0059] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0060] Embodiment 1

[0061] In order to facilitate readers to understand the inventive concept of the present application, the chip packaging structure 100p in the prior art is briefly described. Figure 1 The chip packaging structure 100p in the prior art includes a wafer 10p, a surface metal layer 20p, a first polymer layer 30p, a redistribution layer 40p, a second polymer layer 50p and an under-ball metal layer 60p stacked in sequence; wherein the surface metal layer 20p includes a pad 21p, the first polymer layer 30p has a first through hole 31p, and the redistribution layer 40p is electrically connected to the pad 21p through the first through hole 31p; the second polymer layer 50p has a second through hole 51p, and the under-ball metal layer 60p is electrically connected to the redistribution layer 40p through the second through hole 51p, and a solder ball 70p is arranged on the under-ball metal layer 60p, and the solder ball 70p is used to electrically connect to an external device.

[0062] See also Figure 2 , Figure 2 is a cross-sectional effect diagram of a chip packaging structure 100p of the prior art, Figure 2 , a crack g is formed in the first polymer layer 30p. The applicant of the present application found that the reason for the formation of the crack g is that the redistribution layer 40p and the first polymer layer 30p are made of different materials, the redistribution layer 40p has a very high metal density, and there is a serious adhesion problem between the redistribution layer 40p and the first polymer layer 30p. In addition, the redistribution layer 40p and the first polymer layer 30p have different deformation capabilities to temperature, external force, etc., that is, when the temperature changes, the expansion / contraction deformation sizes of the redistribution layer 40p and the first polymer layer 30p are different, and when subjected to external force, the deformation capabilities of the redistribution layer 40p and the first polymer layer 30p are different.

[0063] It is also important to note that the applicant of the present application discovered that due to the serious adhesion problem between the redistribution layer 40p and the first polymer layer 30p, and the different deformation capabilities of the redistribution layer 40p and the first polymer layer 30p in response to temperature, external force, etc., when the redistribution layer 40p warps, it is easy for one of the polymer layers 30p to deform, and one of the polymer layers 30p is pulled and easily cracked, resulting in a short circuit risk in the surface metal layer 20p.

[0064] Based on the defects of the chip packaging structure 100p in the prior art, the applicant has improved the chip packaging structure 100p in the prior art. Figure 3 and Figure 4 , Figure 3 is a cross-sectional view of a chip packaging structure 100 provided in an embodiment of the present application, Figure 4 FIG. 4 is a schematic diagram of a redistribution layer 40 provided in an embodiment of the present application stacked on a surface metal layer 20. Figure 3 and Figure 4The chip packaging structure 100 provided in the embodiment of the present application includes a wafer 10, a surface metal layer 20, a first polymer layer 30, a redistribution layer 40, a second polymer layer 50 and an under-ball metal layer 60 stacked in sequence; wherein the surface metal layer 20 includes a pad 21, the first polymer layer 30 has a first through hole 31, and the redistribution layer 40 is electrically connected to the pad 21 through the first through hole 31; the second polymer layer 50 has a second through hole 51, and the under-ball metal layer 60 is electrically connected to the redistribution layer 40 through the second through hole 51, and a solder ball 70 is arranged on the under-ball metal layer 60, and the solder ball 70 is used to electrically connect to an external device. The distance from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is a first distance d1; when the first distance d1 satisfies d1≤200μm, the first edge 401 of the redistribution layer 40 is provided with a plurality of first grooves 41 arranged at intervals, and the second polymer layer 50 is connected to the first polymer layer 30 through the first grooves 41. That is, compared with the prior art, the chip packaging structure 100 provided in the embodiment of the present application is further provided with a first groove 41. The present application realizes the connection between the second polymer layer 50 and the first polymer layer 30 through the first groove 41. The first groove 41 forms an anchoring effect, which can improve the cohesion between the first polymer layer 30, the redistribution layer 40 and the second polymer layer 50, thereby improving the binding effect of the first polymer layer 30 and the second polymer layer 50 on the redistribution layer 40. On the other hand, a stress relief area is formed at the first groove 41, so that the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the formation of a crack g in the first polymer layer 30.

[0065] In addition, the distance from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is a first distance d1. When the first distance d1 satisfies d1≤200μm, the first groove 41 is located at the first edge 401, that is, the first groove 41 is opened on the first edge 401 of the redistribution layer 40 only when the distance from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is ≤200μm, that is, the first groove 41 is not set when the distance from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is greater than 200μm. Since the applicant discovered in the process of realizing the present application that when the distance from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is greater than 200 μm, the short-circuit risk of the surface metal layer 20 is small, and the risk of the first polymer layer 30 forming a crack g is small, then through the limitation of the above-mentioned first distance d1 and the first groove 41, on the one hand, the first groove 41 can be opened at the first edge 401 when the first distance d1≤200 μm, thereby reducing the short-circuit risk of the surface metal layer 20 and reducing the risk of the first polymer layer 30 forming a crack g; on the other hand, the first groove 41 is not opened when the first distance d1>200 μm, thereby saving the processing steps of the chip packaging structure 100, reducing the resistance of the redistribution layer 40, and ensuring the stability of the chip packaging structure 100.

[0066] In order to facilitate the reader to understand the inventive concept of the present application, the first direction D1 is defined as the direction from the surface metal layer 20 to the redistribution layer 40, the direction from the notch of the first groove 41 to the groove bottom is defined as the second direction D2, and the third direction D3 is defined as being perpendicular to the first direction D1 and the second direction D2. The second direction D2 and the third direction D3 are actually parallel to the surface metal layer 20, and the third direction D3 is perpendicular to the second direction D2.

[0067] It can be understood that, along the plane defined by the second direction D2 and the third direction D3, the first edge 401 of the redistribution layer 40 is the edge of the redistribution layer 40 closest to the edge of the surface metal layer 20; the first distance d1 from the first edge 401 of the redistribution layer 40 to the edge of the surface metal layer 20 is the shortest distance between the first edge 401 and the edge of the surface metal layer 20.

[0068] It is worth noting that, in some embodiments, a plurality of the first grooves 41 are evenly spaced apart, thereby improving the uniformity of the stress relief of the first grooves 41 .

[0069] It is worth noting that, in some embodiments, the distance between two adjacent first grooves 41 is a first distance G1, which is not less than 20 μm; the distance between the first groove 41 and the second edge 402 of the redistribution layer 40 is a first margin E1, which is not less than 20 μm, wherein the first edge 401 intersects with the second edge 402. Through the above arrangement, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the positions of the plurality of first grooves 41, the overall performance of the chip packaging structure 100 can be guaranteed, and the yield of the chip packaging structure 100 can be guaranteed.

[0070] It is worth noting that, in some embodiments, the length L1 of the first groove 41 is 20 μm; the width b1 of the first groove 41 satisfies 20 μm ≤ b1 ≤ 60 μm. Among them, the length L1 of the first groove 41 is the distance from the notch of the first groove 41 to the bottom of the groove, that is, the length L1 of the first groove 41 is the size of the first groove 41 along the second direction D2; the width b1 of the first groove 41 is the size of the first groove 41 along the third direction D3. Through the above settings, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the size of the first groove 41, the overall performance of the chip packaging structure 100 can be further guaranteed, and the yield of the chip packaging structure 100 can be further guaranteed.

[0071] It is worth noting that, in some embodiments, the thickness of the redistribution layer 40 is 10 μm. This limitation further reduces the risk of deformation and warping of the redistribution layer 40 due to temperature, external force, etc.

[0072] It is worth noting that, in some embodiments, the material of the second polymer layer 50 is the same as the material of the first polymer layer 30. With this definition, when the second polymer layer 50 is connected to the first polymer layer 30 through the first groove 41, compared with the case where the material of the second polymer layer 50 is different from the material of the first polymer layer 30, the adhesion between the second polymer layer 50 and the first polymer layer 30 is strong, and the binding force of the second polymer layer 50 and the first polymer layer 30 on the redistribution layer 40 is strong, which can further reduce the risk of deformation of the redistribution layer 40.

[0073] It is worth noting that, in some embodiments, the material of the second polymer layer 50 includes but is not limited to polybenzoxazole and polyimide; the material of the first polymer layer 30 includes but is not limited to polybenzoxazole and polyimide.

[0074] It is worth noting that, in some embodiments, see Figure 5 Along the first direction D1, the first groove 41 has a first projection 41s, and the surface metal layer 20 has a second projection 20s, and the second projection 20s completely covers the first projection 41s, that is, the first groove 41 is completely covered by the surface metal layer 20, so that on the one hand, the first groove 41 can be used as a stress relief area, and on the other hand, the uniformity of the overall stress distribution of the chip packaging structure 100 can be improved, thereby ensuring the overall performance of the chip packaging structure 100.

[0075] It is worth noting that, in some embodiments, see Figure 6 , the distance from the second edge 402 of the redistribution layer 40 to the edge of the surface metal layer 20 is a second distance d2; when the second distance d2 satisfies d2≤200μm, the second edge 402 of the redistribution layer 40 is provided with a plurality of second grooves 42 arranged at intervals, and the second polymer layer 50 is connected to the first polymer layer 30 through the second grooves 42. That is, compared with the prior art, the chip packaging structure 100 provided in the embodiment of the present application is provided with a second groove 42 in addition to the first groove 41. The present application connects the second polymer layer 50 to the first polymer layer 30 through the first groove 41 and / or the second groove 42. The first groove 41 and / or the second groove 42 form an anchoring effect, which can improve the cohesion among the first polymer layer 30, the redistribution layer 40 and the second polymer layer 50, thereby enhancing the binding effect of the first polymer layer 30 and the second polymer layer 50 on the redistribution layer 40. On the other hand, a stress relief area is formed at the first groove 41 and / or the second groove 42, so that the redistribution layer 40 is not easily deformed and warped due to temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of crack g forming in the first polymer layer 30.

[0076] In addition, the distance from the second edge 402 of the redistribution layer 40 to the edge of the surface metal layer 20 is a second distance d2. When the second distance d2 satisfies d2≤200μm, the second groove 42 is located at the second edge 402, that is, the second groove 42 is opened at the second edge 402 of the redistribution layer 40 only when the distance from the second edge 402 of the redistribution layer 40 to the edge of the surface metal layer 20 is ≤200μm, that is, the second groove 42 is not set when the distance from the second edge 402 of the redistribution layer 40 to the edge of the surface metal layer 20 is greater than 200μm. Since the applicant discovered in the process of realizing the present application that when the distance from the second edge 402 of the redistribution layer 40 to the edge of the surface metal layer 20 is greater than 200 μm, the short-circuit risk of the surface metal layer 20 is small, and the risk of the first polymer layer 30 forming a crack g is small, then through the limitation of the above-mentioned second distance d2 and the second groove 42, on the one hand, the second groove 42 can be opened at the second edge 402 when the second distance d2≤200 μm, thereby reducing the short-circuit risk of the surface metal layer 20 and reducing the risk of the first polymer layer 30 forming a crack g; on the other hand, the second groove 42 is not opened when the second distance d2>200 μm, thereby saving the processing steps of the chip packaging structure 100, reducing the resistance of the redistribution layer 40, and ensuring the stability of the chip packaging structure 100.

[0077] It can be understood that the second edge 402 of the above-mentioned redistribution layer 40 is the edge of the redistribution layer 40 that is closest to the edge of the surface metal layer 20 in the third direction D3; the second distance d2 from the second edge 402 of the above-mentioned redistribution layer 40 to the edge of the surface metal layer 20 is the shortest distance between the second edge 402 and the edge of the surface metal layer 20 in the third direction D3.

[0078] It is worth noting that, in some embodiments, a plurality of the second grooves 42 are evenly spaced apart, thereby improving the uniformity of the stress relief of the second grooves 42 .

[0079] It is worth noting that, in some embodiments, the distance between two adjacent second grooves 42 is a second distance G2, and the second distance G2 is not less than 20 μm; the distance between the second groove 42 and the first edge 401 of the redistribution layer 40 is a second margin E2, and the second margin E2 is not less than 20 μm, wherein the second edge 402 intersects with the first edge 401. Through the above arrangement, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the positions of the plurality of second grooves 42, the overall performance of the chip packaging structure 100 can be guaranteed, and the yield of the chip packaging structure 100 can be guaranteed.

[0080] It is worth noting that, in some embodiments, the length L2 of the second groove 42 is 20 μm; the width b2 of the second groove 42 satisfies 20 μm ≤ b2 ≤ 60 μm. Among them, the length L2 of the second groove 42 is the distance from the notch of the second groove 42 to the bottom of the groove, that is, the length L2 of the second groove 42 is the size of the second groove 42 along the third direction D3; the width b2 of the second groove 42 is the size of the second groove 42 along the second direction D2. Through the above settings, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the size of the second groove 42, the overall performance of the chip packaging structure 100 can be further guaranteed, and the yield of the chip packaging structure 100 can be further guaranteed.

[0081] It is worth noting that, in some embodiments, see Figure 7 Along the first direction D1, the second groove 42 has a third projection 42s, and the surface metal layer 20 has a second projection 20s, and the second projection 20s completely covers the third projection 42s, that is, the second groove 42 is completely covered by the surface metal layer 20, so that on the one hand, the second groove 42 can be used as a stress relief area, and on the other hand, the uniformity of the overall stress distribution of the chip packaging structure 100 can be improved, thereby ensuring the overall performance of the chip packaging structure 100.

[0082] It is worth noting that, in some embodiments, see Figure 8 and Fig. 9, when the first distance d1≤100μm, and / or the second distance d2≤100μm, the redistribution layer 40 is further provided with a plurality of stress release holes 43 arranged at intervals, and the second polymer layer 50 is connected to the first polymer layer 30 through the stress release holes 43. That is, compared with the prior art, the chip packaging structure 100 provided in the embodiment of the present application is provided with stress release holes 43 in addition to the first groove 41 and the second groove 42. The present application connects the second polymer layer 50 to the first polymer layer 30 through the first groove 41, the second groove 42 and the stress release hole 43. The first groove 41 and / or the stress release hole 43 form an anchoring effect, which can improve the cohesion between the first polymer layer 30, the redistribution layer 40 and the second polymer layer 50, thereby enhancing the binding effect of the first polymer layer 30 and the second polymer layer 50 on the redistribution layer 40. On the other hand, a stress relief area is formed at the first groove 41, the second groove 42 and the stress release hole 43, so that the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of crack g forming in the first polymer layer 30.

[0083] In addition, when the first distance d1≤100μm, and / or the second distance d2≤100μm, in addition to the first groove 41 and the second groove 42, the stress release hole 43 is also provided. Since the applicant of the present application found in the process of realizing the present application that when the first distance d1≤100μm, and / or the second distance d2≤100μm, that is, when the redistribution layer 40 is provided closer to the edge of the surface metal layer 20, the adhesion of the first polymer layer 30 and the second polymer layer 50 to the redistribution layer 40 is small, only the first distance d1≤100μm and the second distance d2≤100μm are provided on the redistribution layer 40. The first groove 41 and the second groove 42 may not necessarily solve the technical problem that the redistribution layer 40 is easily deformed and warped due to temperature, external force, etc., and when a stress release hole 43 is further provided in the redistribution layer 40, the stress release hole 43 can be located in the middle of the redistribution layer 40, so that the redistribution layer 40 is not easily deformed and warped due to temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20, reduce the risk of cracks g forming in the first polymer layer 30, and improve the yield of the chip packaging structure 100.

[0084] It is worth noting that, in some embodiments, the plurality of stress release holes 43 are evenly spaced, thereby improving the uniformity of stress relief of the stress release holes 43 .

[0085] It is worth noting that, in some embodiments, the distance between two adjacent stress release holes 43 is a third distance G3, and the third distance G3 is not less than 20 μm; the distance between the stress release hole 43 and the edge of the redistribution layer 40 is a third margin E3, and the third margin E3 is not less than 40 μm. The distance between the stress release hole 43 and the edge of the redistribution layer 40 is the distance between the stress release hole 43 and the first edge 401 of the redistribution layer 40, or the distance between the stress release hole 43 and the second edge 402 of the redistribution layer 40. Through the above settings, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the positions of the plurality of stress release holes 43, the overall performance of the chip packaging structure 100 can be guaranteed, and the yield of the chip packaging structure 100 can be guaranteed.

[0086] It is worth noting that, in some embodiments, the stress release hole 43 is a rectangular hole, and the length L3 of the stress release hole 43 is 20 μm; the width b3 of the stress release hole 43 satisfies 20 μm ≤ b3 ≤ 60 μm. The length L3 of the stress release hole 43 is the size of the stress release hole 43 along the third direction D3; the width b3 of the stress release hole 43 is the size of the stress release hole 43 along the second direction D2. Through the above settings, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer 40 is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer 30 is not easily deformed by the redistribution layer 40, which can reduce the short circuit risk of the surface metal layer 20 and the risk of the first polymer layer 30 forming a crack g; on the other hand, by limiting the size of the stress release hole 43, the overall performance of the chip packaging structure 100 can be further guaranteed, and the yield of the chip packaging structure 100 can be further guaranteed.

[0087] It is worth noting that, in some embodiments, see Fig.10 , along the first direction D1, the stress release hole 43 has a fourth projection 43s, and the surface metal layer 20 has a second projection 20s, and the second projection 20s completely covers the fourth projection 43s, that is, the stress release hole 43 is completely covered by the surface metal layer 20, so that on the one hand, the stress release hole 43 can be used as a stress relief area, and on the other hand, the uniformity of the overall stress distribution of the chip packaging structure 100 can be improved, thereby ensuring the overall performance of the chip packaging structure 100.

[0088] It is worth noting that the shapes of the first groove 41, the second groove 42, and the stress release hole 43 are not limited to those provided in the present application. Figures 2 to 10 The rectangle shown can also be various. For example, the first groove 41 can be a fan-shaped groove, a semicircular groove, a rectangular groove, a sawtooth groove, etc. Fig.11 The following examples illustrate some possible shapes of the first groove 41. For example, the second groove 42 may be a fan-shaped groove, a semicircular groove, a rectangular groove, a sawtooth groove, etc. Fig.11 The following examples illustrate some possible shapes of the first groove 42. For example, the stress release hole 43 may be circular, rectangular, polygonal, etc. Fig.11 Some possible shapes of the stress relief hole 43 are shown as examples.

[0089] It is worth mentioning that Fig.11 It is only an example of the possible implementation of the first groove 41, the second groove 42 and the third groove 43. In practical applications, for a chip packaging structure 100, the shapes of the multiple first grooves 41 can be the same or different, that is, a mixture of multiple shapes can be adopted. Similarly, for a chip packaging structure 100, the shapes of the multiple second grooves 42 can be the same or different, that is, a mixture of multiple shapes can be adopted. Similarly, for a chip packaging structure 100, the shapes of the multiple stress release holes 43 can be the same or different, that is, a mixture of multiple shapes can be adopted.

[0090] In order to help readers understand the inventive concept of the present application, the effect of the chip packaging structure 100 of the present application is now described in combination with experiments.

[0091] Experimental test method: The chip package structure 100 is placed in a temperature box and subjected to a temperature cycle from -65 degrees to +150 degrees. At the same time, the chip package structure 100 is also undergoing a functional test. After 1000 temperature cycles, the various functions of the chip package structure 100 are tested to see if they are normal.

[0092] When the first distance d1 satisfies d1≤200 μm and the first groove 41 is not configured, all chips undergoing the above test will have abnormal functions after the test. However, the chip version configured with the first groove 41 according to the present invention can pass the above test without damage.

[0093] Embodiment 2

[0094] The present application also provides a chip packaging method. Fig.12 , Fig.12 FIG. 1 is a schematic diagram of a chip packaging process according to an embodiment of the present application. Fig.12 The chip packaging method comprises the following steps:

[0095] Step S10, depositing a first polymer layer on the surface metal layer on the wafer.

[0096] There are many ways to deposit the first polymer layer on the surface metal layer on the wafer, such as using chemical vapor deposition or physical vapor deposition to deposit the polymer. The chemical vapor deposition method generates a polymer film on the surface metal layer through a chemical reaction, while the physical vapor deposition method deposits the polymer material directly onto the surface metal layer through a physical process (such as sputtering).

[0097] Step S20: forming a first through hole on the first polymer layer to expose the pad located on the surface metal layer of the wafer.

[0098] The first through hole may be formed on the first polymer layer by patterning the first polymer layer. Patterning the first polymer layer is a prior art and will not be described in detail herein.

[0099] Step S30, forming a redistribution layer on the first polymer layer, the redistribution layer being electrically connected to the pad through the first through hole, the distance from the first edge of the redistribution layer to the edge of the surface metal layer being the first distance d1, forming a redistribution layer on the first polymer layer, the redistribution layer being electrically connected to the pad through the first through hole, the distance from the first edge of the redistribution layer to the edge of the surface metal layer being the first distance d1, when the first distance d1 satisfies d1≤200 μm, the first edge of the formed redistribution layer has a plurality of first grooves arranged at intervals;

[0100] A redistribution layer is formed on the first polymer layer, and when the first distance d1 satisfies d1≤200 μm, the first edge of the redistribution layer is formed to have a plurality of first grooves spaced apart from each other, which can be achieved by electroplating or sputtering. When the redistribution layer is formed by electroplating or sputtering, the position of the first groove is avoided, and the formed redistribution layer has the first groove.

[0101] It is worth noting that, in some embodiments, a metal layer may be formed on the first polymer layer, and then the metal layer may be patterned or etched to form a redistribution layer having a first groove.

[0102] It is worth noting that, in some embodiments, the material of the redistribution layer is copper.

[0103] Step S40 , depositing a second polymer layer, wherein the second polymer layer is connected to the first polymer layer through the first groove.

[0104] The method of depositing and forming the second polymer layer may be the same as the method of forming the first polymer layer, which will not be described in detail herein.

[0105] Step S50: forming a second through hole in the second polymer layer.

[0106] The implementation method of forming the second through hole on the second polymer layer may be the same as the above-mentioned method of forming the first through hole on the first polymer layer, which will not be described in detail herein.

[0107] Step S60 , forming an under ball metallization layer at the second through hole, wherein the under ball metallization layer is electrically connected to the redistribution layer.

[0108] The UBM layer may be formed at the second through hole by electroplating or sputtering in the prior art.

[0109] Step S70, disposing solder balls on the UBM layer, wherein the solder balls are used to electrically connect to external devices.

[0110] The solder balls may be arranged on the metal layer under the ball by using a template or a fixture to accurately place the solder balls on the metal layer under the ball. The template or the fixture is provided with through holes or grooves matching the size of the solder balls to ensure that the position and quantity of the solder balls are accurate. When placing the solder balls, the solder balls may be assisted to fall into the through holes or grooves on the template or the fixture by means of vibration, air pressure or a robotic arm.

[0111] It is worth noting that, in some embodiments, the step of forming a redistribution layer on the first polymer layer further includes: opening the first groove at a first edge of the redistribution layer at a position not less than 20 μm away from the second edge of the redistribution layer, and opening the first groove at a position not less than 20 μm apart, wherein the first edge intersects with the second edge. Through this method, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, the short circuit risk of the surface metal layer can be reduced, and the risk of cracks in the first polymer layer can be reduced; on the other hand, by limiting the positions of multiple first grooves, the overall performance of the chip packaging structure can be guaranteed, and the yield of the chip packaging structure can be guaranteed.

[0112] It is worth noting that, in some embodiments, the distance from the second edge of the redistribution layer to the edge of the surface metal layer is a second distance d2, and the second edge intersects with the first edge. When the second distance d2 satisfies ≤200μm, a plurality of second grooves arranged at intervals are provided at the second edge of the redistribution layer, so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the second groove. That is, compared with the prior art, the chip packaging method provided in the embodiment of the present application has a second groove in addition to the first groove. The present application realizes the connection between the second polymer layer and the first polymer layer through the first groove and / or the second groove. The first groove and / or the second groove form an anchoring effect, which can improve the cohesion between the first polymer layer, the redistribution layer and the second polymer layer, thereby improving the binding effect of the first polymer layer and the second polymer layer on the redistribution layer. On the other hand, a stress relief area is formed at the first groove and / or the second groove, so that the redistribution layer is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, which can reduce the risk of short circuit of the surface metal layer and the risk of crack formation in the first polymer layer.

[0113] It is worth noting that, in some embodiments, when the first distance d1≤100μm, and / or the second distance d2≤100μm, a plurality of stress release holes arranged at intervals are provided in the redistribution layer, so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the stress release holes. That is, compared with the prior art, the chip packaging method provided in the embodiment of the present application forms a stress release hole in addition to the first groove and the second groove formed in the redistribution layer. The present application realizes the connection between the second polymer layer and the first polymer layer through the first groove, the second groove and the stress release hole. The first groove and / or the stress release hole form an anchoring effect, which can improve the cohesion between the first polymer layer, the redistribution layer and the second polymer layer, thereby enhancing the binding effect of the first polymer layer and the second polymer layer on the redistribution layer. On the other hand, the first groove, the second groove and the stress release hole form a stress relief area, so that the redistribution layer is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, which can reduce the risk of short circuit of the surface metal layer and the risk of crack formation in the first polymer layer.

[0114] In addition, when the first distance d1≤100μm, and / or the second distance d2≤100μm, in addition to setting the first groove and the second groove, the stress release hole is also set. Because the applicant of the present application found in the process of realizing the present application that when the first distance d1≤100μm, and / or the second distance d2≤100μm, that is, when the redistribution layer is set closer to the edge of the surface metal layer, the adhesion of the first polymer layer and the second polymer layer to the redistribution layer is small, and only setting the first groove and the second groove in the redistribution layer does not necessarily solve the technical problem that the redistribution layer is easily deformed and warped due to temperature, external force, etc., and when the redistribution layer is further provided with a stress release hole, the stress release hole can be located in the middle of the redistribution layer, which can make the redistribution layer not easily deformed and warped due to temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, which can reduce the short circuit risk of the surface metal layer, reduce the risk of cracks in the first polymer layer, and improve the yield of the chip packaging structure.

[0115] It is worth noting that, in some embodiments, the step of providing a plurality of stress release holes arranged at intervals in the redistribution layer further includes: forming the stress release holes at a position not less than 40 μm away from the edge of the redistribution layer, and forming the stress release holes at a position not less than 20 μm apart. Through the above arrangement, on the one hand, the invention goal of the present application can be achieved, that is, the redistribution layer is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, the short circuit risk of the surface metal layer can be reduced, and the risk of cracks in the first polymer layer can be reduced; on the other hand, by limiting the positions of the plurality of stress release holes, the overall performance of the chip packaging structure can be guaranteed, and the yield of the chip packaging structure can be guaranteed.

[0116] In the embodiment of the present application, a redistribution layer having a first groove can be formed by a chip packaging method. The chip packaging structure formed by the chip packaging method provided by the embodiment of the present application realizes the connection between the second polymer layer and the first polymer layer through the first groove. The first groove forms an anchoring effect, which can improve the cohesion between the first polymer layer, the redistribution layer and the second polymer layer, thereby enhancing the binding effect of the first polymer layer and the second polymer layer on the redistribution layer. On the other hand, a stress relief area is formed at the first groove, so the redistribution layer is not easily deformed and warped by temperature, external force, etc., so that the first polymer layer is not easily deformed by the redistribution layer, which can reduce the short circuit risk of the surface metal layer and the risk of cracks in the first polymer layer. In addition, the distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1. When the first distance d1 satisfies d1≤200μm, the first groove is located at the first edge, that is, the first groove is opened at the first edge of the redistribution layer only when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is ≤200μm, that is, the first groove is not set when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is greater than 200μm. Since the applicant found in the process of realizing this application that when the distance from the first edge of the redistribution layer to the edge of the surface metal layer is greater than 200μm, the risk of deformation short circuit of the surface metal layer is small, and the risk of crack formation in the first polymer layer is small, then through the above-mentioned first distance d1 and the first groove, on the one hand, the first groove can be opened at the first edge when the first distance d1≤200μm, thereby reducing the risk of short circuit of the surface metal layer and reducing the risk of crack formation in the first polymer layer; on the other hand, the first groove is not opened when the first distance d1>200μm, so that the chip packaging method is simple, the resistance of the redistribution layer is reduced, and the stability of the formed chip packaging structure is good.

[0117] Embodiment 3

[0118] The embodiment of the present application also provides an example of a circuit system, which includes a chip of the chip packaging structure in the embodiment, or a chip packaged by the chip packaging method in the embodiment 2. The specific structure and function of the chip packaging structure can be referred to in the above embodiment 1, which will not be described in detail here. The specific implementation of the chip packaging method can be referred to in the above embodiment 2, which will not be described in detail here.

[0119] It should be noted that the preferred embodiments of the present application are given in the specification and drawings of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described in the specification. These embodiments are not used as additional limitations on the content of the present application. The purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. In addition, the above-mentioned technical features continue to be combined with each other to form various embodiments not listed above, which are all regarded as the scope of the description of the present application; further, for ordinary technicians in this field, they can be improved or transformed according to the above description, and all these improvements and transformations should belong to the scope of protection of the claims attached to the present application.

Claims

1. A chip packaging structure, characterized in that: It includes a wafer, a surface metal layer, a first polymer layer, a redistribution layer, a second polymer layer and an under-ball metal layer stacked in sequence; The surface metal layer includes a pad, the first polymer layer has a first through hole, and the redistribution layer is electrically connected to the pad through the first through hole; The second polymer layer has a second through hole, the UBM layer is electrically connected to the redistribution layer through the second through hole, a solder ball is arranged on the UBM layer, and the solder ball is used to electrically connect to an external device; The distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1; When the first distance d1 satisfies d1≤200 μm, a plurality of first grooves arranged at intervals are provided at the first edge of the redistribution layer, and the second polymer layer is connected to the first polymer layer through the first grooves; when the first distance d1 satisfies d1>200 μm, the first grooves are not provided; When the first distance d1 is less than or equal to 100 μm, the redistribution layer is further provided with a plurality of stress release holes arranged at intervals, and the second polymer layer is connected to the first polymer layer through the stress release holes; A direction from the notch opening to the bottom of the first notch is a second direction. Along the second direction, the stress release hole is located between the first notch and the first through hole.

2. The chip packaging structure according to claim 1, characterized in that: The distance between two adjacent first grooves is not less than 20 μm; The first groove is at a distance of not less than 20 μm from a second edge of the redistribution layer, wherein the first edge intersects the second edge.

3. The chip packaging structure according to claim 2, characterized in that: The length of the first groove is 20 μm; The width b1 of the first groove satisfies 20 μm≤b1≤60 μm.

4. The chip packaging structure according to claim 2, characterized in that: The thickness of the redistribution layer is 10 μm.

5. The chip packaging structure according to claim 1, characterized in that: The material of the second polymer layer is the same as that of the first polymer layer.

6. The chip packaging structure according to claim 1, characterized in that: Along a first direction, the first groove has a first projection, the surface metal layer has a second projection, and the second projection completely covers the first projection; Wherein, the first direction is the direction from the surface metal layer to the redistribution layer.

7. The chip packaging structure according to claim 2, characterized in that: The distance from the second edge of the redistribution layer to the edge of the surface metal layer is a second distance d2; When the second distance d2 satisfies d2≤200 μm, a plurality of second grooves arranged at intervals are formed at the second edge of the redistribution layer, and the second polymer layer is connected to the first polymer layer through the second grooves.

8. The chip packaging structure according to claim 7, characterized in that: The distance between two adjacent second grooves is not less than 20 μm; The distance between the second groove and the first edge is not less than 20 μm.

9. The chip packaging structure according to claim 8, characterized in that: The length of the second groove is 20 μm; A width b2 of the second groove satisfies 20 μm≤b2≤60 μm.

10. The chip packaging structure according to claim 8, characterized in that: Along the first direction, the second groove has a third projection, the surface metal layer has a second projection, and the second projection completely covers the third projection; Wherein, the first direction is the direction from the surface metal layer to the redistribution layer.

11. The chip packaging structure according to any one of claims 7 to 10, characterized in that: When the second distance d2 is less than or equal to 100 μm, the redistribution layer is further provided with a plurality of the stress release holes which are arranged at intervals, and the second polymer layer is connected to the first polymer layer through the stress release holes.

12. The chip packaging structure according to claim 11, characterized in that: The distance between two adjacent stress release holes is not less than 20 μm; The distance between the stress release hole and the edge of the redistribution layer is not less than 40 μm.

13. The chip packaging structure according to claim 12, characterized in that: The stress release hole is a rectangular hole, and the length of the stress release hole is 20 μm; The width b3 of the stress release hole satisfies 20 μm≤b3≤60 μm.

14. The chip packaging structure according to claim 11, characterized in that: Along the first direction, the stress release hole has a fourth projection, the surface metal layer has a second projection, and the second projection completely covers the fourth projection; Wherein, the first direction is the direction from the surface metal layer to the redistribution layer.

15. A chip packaging method, characterized in that: include: depositing a first polymer layer on a surface metal layer on the wafer; forming a first through hole on the first polymer layer to expose the pad located on the surface metal layer of the wafer; A redistribution layer is formed on the first polymer layer, the redistribution layer is electrically connected to the pad through the first through hole, the distance from the first edge of the redistribution layer to the edge of the surface metal layer is a first distance d1, when the first distance d1 satisfies d1≤200μm, the first edge of the formed redistribution layer has a plurality of first grooves arranged at intervals; when the first distance d1 satisfies d1>200μm, the first groove is not provided; when the first distance d1≤100μm, the redistribution layer is further provided with a plurality of stress release holes arranged at intervals; the direction from the notch to the bottom of the first groove is a second direction, along which the stress release hole is located between the first groove and the first through hole; depositing a second polymer layer, wherein the second polymer layer is connected to the first polymer layer through the first groove; forming a second through hole in the second polymer layer; forming an under ball metallization layer at the second through hole, wherein the under ball metallization layer is electrically connected to the redistribution layer; A solder ball is disposed on the UBM layer, and the solder ball is used for electrically connecting to an external device.

16. The chip packaging method according to claim 15, characterized in that: The step of forming a redistribution layer on the first polymer layer further comprises: The first groove is opened at a first edge of the redistribution layer at a position not less than 20 μm away from a second edge of the redistribution layer, and the first groove is opened at a position not less than 20 μm apart, wherein the first edge intersects the second edge.

17. The chip packaging method according to claim 15, characterized in that: The distance from the second edge of the redistribution layer to the edge of the surface metal layer is a second distance d2, and the second edge intersects with the first edge. When the second distance d2 satisfies ≤200μm, a plurality of second grooves arranged at intervals are opened at the second edge of the redistribution layer so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the second grooves.

18. The chip packaging method according to claim 17, characterized in that: When the second distance d2 ≤ 100 μm, a plurality of the stress release holes are disposed at intervals in the redistribution layer, so that after the second polymer layer is deposited, the second polymer layer is connected to the first polymer layer through the stress release holes.

19. The chip packaging method according to claim 18, characterized in that: The step of providing a plurality of stress relief holes spaced apart in the redistribution layer further comprises: The stress release holes are formed at positions not less than 40 μm away from an edge of the redistribution layer, and the stress release holes are formed at positions with an interval not less than 20 μm.

20. A circuit system, characterized in that: A chip comprising the chip packaging structure as claimed in any one of claims 1 to 14, or a chip packaged by the chip packaging method as claimed in any one of claims 15 to 19.

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