Double-channel multi-gate high-voltage-resistant GaN HEMT device and manufacturing method thereof

Abstract

The invention discloses a double-channel multi-gate high-voltage-withstanding GaN HEMT device and a manufacturing method, the device comprises a substrate layer, and a GaN high-resistance layer, a GaN channel layer and a first AlGaN barrier layer which are grown on the substrate layer in sequence, a first non-doped GaN layer, a second AlGaN barrier layer and a second non-doped GaN layer are grown on the first AlGaN barrier layer close to the middle part in sequence, a source electrode and a drain electrode are symmetrically manufactured on the two sides of the first AlGaN barrier layer, and the first non-doped GaN layer, the second non-doped GaN layer and the second non-doped GaN layer are symmetrically manufactured on the two sides of the second AlGaN barrier layer. The first non-doped GaN layer and the second AlGaN barrier layer are respectively connected with the source electrode and the drain electrode, and gaps are respectively kept between the second non-doped GaN layer and the source electrode and between the second non-doped GaN layer and the drain electrode; a first pGaN layer and a first grid are sequentially grown on the surface of the second non-doped GaN layer; a secondary epitaxial non-doped GaN layer, a secondary epitaxial pGaN layer and a second grid are sequentially grown on the other side of the surface of the first non-doped GaN layer, and gaps are kept between the secondary epitaxial non-doped GaN layer and the second AlGaN barrier layer and between the secondary epitaxial pGaN layer and the second non-doped GaN layer, so that 2DHG on the upper layer and 2DHG on the lower layer can be led out through the first grid and the second grid; and high voltage resistance of the device is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor discrete devices, and in particular to a dual-channel multi-gate high-voltage GaN HEMT device and a manufacturing method thereof. Background Art

[0002] In AlGaN / GaN heterojunction, high-density, high-mobility 2DEG is generated due to polarization effect, which makes it have great potential in power semiconductor devices with high blocking voltage, large current capacity, high switching speed and low on-resistance. However, traditional HEMT devices have only one channel, and the current and on-resistance cannot compete with SiC-based MOS.

[0003] Currently, there are also dual-channel GaN HEMT devices that can achieve low resistance and large current, but their voltage resistance performance is relatively weak. Summary of the invention

[0004] The embodiment of the present application provides a dual-channel multi-gate high-voltage GaN HEMT device and a manufacturing method, wherein the dual-channel multi-gate high-voltage GaN HEMT device has a secondary epitaxy and a multi-gate structure. When the device is turned off, 2DHG can be led out through the ohmic contact of pGaN, so that both double barrier layers are depletion layers, and only fixed charges are retained, so as to achieve the purpose of uniform electric field, thereby effectively improving the voltage resistance performance of the GaN HEMT device and realizing the high voltage resistance of the device.

[0005] A first aspect of an embodiment of the present application provides a dual-channel multi-gate high withstand voltage GaN HEMT device, comprising a substrate layer and a GaN high resistance layer, a GaN channel layer and a first AlGaN barrier layer sequentially grown on the substrate layer, wherein a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer are sequentially grown on the surface of the first AlGaN barrier layer near the middle, and a source and a drain are symmetrically made on both sides of the first undoped GaN layer, wherein the first undoped GaN layer and the second AlGaN barrier layer are connected to the source and the drain at both ends, respectively, and a gap is maintained between the two ends of the second undoped GaN layer and the source and the drain, respectively;

[0006] A first pGaN layer and a first gate are sequentially grown on the surface of the second undoped GaN layer, and the upper layer 2DHG is led out through the first gate;

[0007] A secondary epitaxial undoped GaN layer, a secondary epitaxial pGaN layer and a second gate are sequentially grown on the surface of the first undoped GaN layer between the first pGaN layer and the source electrode. The secondary epitaxial pGaN layer and the second gate are respectively maintained at the same height as the first pGaN layer and the first gate. The secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer both maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer, and the lower layer 2DHG is led out through the second gate.

[0008] In a possible implementation manner, the substrate layer is a sapphire substrate.

[0009] In a possible implementation, the source electrode and the drain electrode are both made of Ni / Al / Ni / Au metal alloy.

[0010] In a possible implementation manner, the materials of the first gate and the second gate are both Ni / Au metal alloy.

[0011] A second aspect of the embodiments of the present application provides a method for manufacturing the aforementioned dual-channel multi-gate high withstand voltage GaN HEMT device, comprising the following steps:

[0012] S10, sequentially growing a GaN high resistance layer, a GaN channel layer, a first AlGaN barrier layer, a uGaN-1 layer, an AlGaN-2 layer, a uGaN-2 layer, and a pGaN-1 layer on the substrate layer;

[0013] S20, sequentially forming the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at a predetermined position on the surface of the pGaN-1 layer;

[0014] S30, repeating the steps of photolithography, etching and desmearing and cleaning to sequentially form the first pGaN layer, the second undoped GaN layer and the second AlGaN barrier layer at a predetermined position on the surface of the pGaN-1 layer;

[0015] S40, respectively photolithographically patterning the first gate and the second gate on the surface of the first pGaN layer and the secondary epitaxial pGaN layer, then evaporating the P ohmic contact by PVD process, stripping and cleaning, and then performing RTA annealing to form the first gate and the second gate;

[0016] S50, patterning the source and drain electrodes at predetermined positions on the surface of the pGaN-1 layer, evaporating the N-ohm contact by PVD process, stripping and cleaning, and finally performing RTA annealing to form the source and drain electrodes.

[0017] In a possible implementation, in step S20, sequentially forming the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at a predetermined position on the surface of the pGaN-1 layer specifically includes:

[0018] S21, etching the range of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer on the surface of the pGaN-1 layer by using a positive photolithography process, removing the original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by using an ICP etching technology, and removing the photoresist and cleaning after the etching is completed;

[0019] S22, forming a SiO2 layer on the surface of the pGaN-1 layer, etching the patterns of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by using a positive photolithography process, then removing the SiO2 layer of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer pattern portion by using a wet HF etching method, and finally removing the resist by using a cleaning process;

[0020] S23, growing the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer successively at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by the MOCVD secondary epitaxial method, and then removing the SiO2 layer except the secondary epitaxial pGaN layer by wet HF etching, so that gaps are maintained around the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer.

[0021] In a possible implementation, in step S40, the environment of the RTA annealing is an atmospheric environment, and the temperature of the RTA annealing is 600°C to 650°C.

[0022] In a possible implementation, in step S50, the environment of the RTA annealing is a N2@1SLM environment, and the temperature of the RTA annealing is 750°C to 950°C.

[0023] Beneficial effects: Compared with the prior art, the dual-channel multi-gate high-voltage GaN HEMT device and the manufacturing method provided by the present application, wherein the dual-channel multi-gate high-voltage GaN HEMT device can use the secondary epitaxy and multi-gate structure to lead out 2DHG by ohmic contact when the device is turned off, wherein the first gate leads out the 2DHG of the upper layer, and the second gate leads out the 2DHG of the lower layer, thereby realizing the depletion of 2DHG under reverse bias, and at the same time, 2DEG is led out through the source and the drain, and at the same time, the first AlGaN barrier layer and the second AlGaN barrier layer are both depletion layers, and only fixed charges are retained, so as to achieve the purpose of uniform electric field, thereby effectively improving the voltage resistance performance of the GaN HEMT device;

[0024] In addition, the dual-channel device forms a dual 2DEG, which can greatly increase the operating current of the device and reduce the on-resistance.

[0025] These and other objects, features and advantages of the present invention will be fully reflected in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the three-dimensional structure of the double-channel multi-gate high-voltage GaN HEMT device of the present application is shown.

[0027] Figure 2 Shows this application Figure 1 Schematic diagram of the cross-sectional structure of section A in the middle.

[0028] Figure 3 Shows this application Figure 1 Schematic diagram of the structure of the cross section at point B. DETAILED DESCRIPTION

[0029] The following description is used to disclose the present invention so that those skilled in the art can implement the present invention. The preferred embodiments described below are only examples, and those skilled in the art can think of other obvious variations. The basic principles of the present invention defined in the following description can be applied to other embodiments, variations, improvements, equivalents, and other technical solutions that do not deviate from the spirit and scope of the present invention.

[0030] Those skilled in the art should understand that, in the disclosure of the specification, the orientation or position relationship indicated by the terms "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. are based on the orientation or position relationship shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the above terms should not be understood as limiting the present invention.

[0031] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the element may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0032] refer to Figures 1 to 3According to one aspect of the present application, a dual-channel multi-gate high withstand voltage GaN HEMT device is provided, comprising a substrate layer and a GaN high resistance layer, a GaN channel layer and a first AlGaN barrier layer sequentially grown on the substrate layer, wherein the substrate layer is preferably a sapphire substrate, wherein a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer are sequentially grown on the surface of the first AlGaN barrier layer near the middle, and a source S and a drain D are symmetrically grown on both sides of the first undoped GaN layer, wherein the first undoped GaN layer and the second AlGaN barrier layer are connected to the source S and the drain D at both ends, respectively, and at the same time, a gap is maintained between the two ends of the second undoped GaN layer and the source S and the drain D, respectively;

[0033] In addition, a first pGaN layer and a first gate G1 are sequentially grown on the surface of the second undoped GaN layer, so that the upper layer 2DHG can be led out through the first gate G1;

[0034] In addition, a secondary epitaxial undoped GaN layer uGaN, a secondary epitaxial pGaN layer pGaN-2 and a second gate G2 are sequentially grown on the surface of the first undoped GaN layer between the first pGaN layer and the source electrode, wherein the secondary epitaxial pGaN layer pGaN-2 and the second gate G2 respectively maintain the same height as the first pGaN layer and the first gate G1, and at the same time, the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 both maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer, so that the lower layer 2DHG can be led out through the second gate G2.

[0035] In a conventional double-channel structure, 2DHG, i.e., two-dimensional hole gas, will be generated between the lower AlGaN barrier layer and the GaN layer between the double barrier layer. The generation of 2DHG will lead to the concentration of the electric field. If the 2DHG is not led out, the voltage resistance performance of the device will inevitably be reduced, seriously affecting the quality and service life of the device.

[0036] The dual-channel multi-gate high-voltage GaN In HEMT devices, due to the polarization effect between AlGaN and GaN, a two-dimensional electron gas (2DEG) is generated on the surface of the GaN layer below the AlGaN, that is, 2DEG is generated between the first AlGaN barrier layer and the GaNchannel layer, and between the second AlGaN barrier layer and the first undoped GaN layer. At the same time, a two-dimensional hole gas (2DHG) is generated on the surface of the GaN layer above the AlGaN layer, that is, 2DHG is generated between the second undoped GaN layer and the second AlGaN barrier layer, and between the first undoped GaN layer and the first AlGaN barrier layer, which are the upper 2DHG and the lower 2DHG respectively. When a reverse voltage is applied to the first gate G1 and the second gate G2, the upper hole 2DHG will flow to the first gate G1, and the lower hole 2DHG will flow to the second gate G2. At the same time, 2DEG is respectively led out through the source and the drain, that is, the purpose of depletion of 2DEG and 2DHG in the first AlGaN barrier layer and the second AlGaN barrier layer can be achieved, and the electric field distribution is relatively uniform, thereby improving the withstand voltage performance of the device. At the same time, when the device is turned on, because it is a dual channel, the on-resistance is reduced and the current is increased.

[0037] In one embodiment, the source electrode and the drain electrode are both made of Ni / Al / Ni / Au metal alloy.

[0038] In one embodiment, the materials of the first gate G1 and the second gate G2 are both Ni / Au metal alloy.

[0039] Another aspect of the present application provides a method for manufacturing the aforementioned dual-channel multi-gate high withstand voltage GaN HEMT device, comprising the following steps:

[0040] S10, sequentially growing a GaN high resistance layer, a GaN channel layer, a first AlGaN barrier layer, a uGaN-1 layer, an AlGaN-2 layer, a uGaN-2 layer, and a pGaN-1 layer on a substrate layer (preferably a sapphire substrate);

[0041] S20, sequentially forming the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 at predetermined positions on the surface of the pGaN-1 layer, more specifically:

[0042] S21, firstly, using a positive photolithography process to etch the range of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN on the surface of the pGaN-1 layer, and using an ICP etching technique to remove the original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the positions of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN, and after the etching is completed, remove the photoresist and clean;

[0043] S22, using ALD / PVD / CVD and other processes to make a SiO2 layer on the surface of the pGaN-1 layer, using a positive photolithography process to carve out the patterns of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN, and then using wet HF etching to remove the SiO2 layer of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN pattern portion, and finally using a cleaning process to remove the resist;

[0044] S23, sequentially growing the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 at the positions of the secondary epitaxial pGaN layer pGaN-2 and the secondary epitaxial undoped GaN layer uGaN by a MOCVD secondary epitaxial method, and then removing the SiO2 layer except the secondary epitaxial pGaN layer pGaN-2 by wet HF etching, so that the peripheral sides of the secondary epitaxial undoped GaN layer uGaN and the secondary epitaxial pGaN layer pGaN-2 maintain gaps, that is, they do not maintain contact with the subsequent second undoped GaN layer and the second AlGaN barrier layer;

[0045] S30, repeating the steps of photolithography, etching, and stripping and cleaning to sequentially form the first pGaN layer, the second undoped GaN layer, and the second AlGaN barrier layer at a predetermined position on the surface of the pGaN-1 layer, that is, firstly photolithography the pattern of the first pGaN layer using a positive photolithography process, then etching its pattern using an ICP etching process, stripping and cleaning, secondly photolithography the pattern of the second undoped GaN layer using a positive photolithography process, then etching its pattern using an ICP etching process, stripping and cleaning, and finally photolithography the pattern of the second AlGaN barrier layer using a positive photolithography process, then etching its pattern using an ICP etching process, stripping and cleaning;

[0046] S40, respectively, on the surface of the first pGaN layer and the secondary epitaxial pGaN layer pGaN-2, the patterns of the first gate G1 and the second gate G2 are photolithographically formed by a positive photolithography process, and then the P ohmic contact (Ni / Au) is evaporated by a PVD process, and the photolithography is stripped and cleaned, and then RTA annealing is performed to form the first gate G1 and the second gate G2, wherein the environment of the RTA annealing is an atmospheric environment, and the temperature of the RTA annealing is 600° C. to 650° C.;

[0047] S50, using a positive photolithography process to photolithograph the source and drain patterns at predetermined positions on the surface of the pGaN-1 layer, then using a PVD process to evaporate the N ohmic contact, stripping and cleaning, and finally performing RTA annealing to form the source and drain, wherein the RTA annealing environment is a N2@1SLM environment, and the RTA annealing temperature is 750°C to 950°C.

[0048] It should be noted that the terms "first, second" in the present application are only used for descriptive purposes and do not indicate any order. They cannot be understood as indicating or implying relative importance. These terms can be interpreted as names.

[0049] It should be understood by those skilled in the art that the embodiments of the present invention described above and shown in the accompanying drawings are only examples and do not limit the present invention. The advantages of the present invention have been fully and effectively achieved. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments, and the embodiments of the present invention may be deformed or modified in any way without departing from the principles.

Claims

1. A dual-channel multi-gate high withstand voltage GaN HEMT device, characterized in that: It comprises a substrate layer, and a GaN high-resistance layer, a GaN channel layer and a first AlGaN barrier layer grown sequentially on the substrate layer, wherein a first undoped GaN layer, a second AlGaN barrier layer and a second undoped GaN layer are sequentially grown near the middle of the surface of the first AlGaN barrier layer, and a source and a drain are symmetrically made on both sides of the first undoped GaN layer, wherein the first undoped GaN layer and the second AlGaN barrier layer are connected to the source and the drain at both ends respectively, and a gap is maintained between the two ends of the second undoped GaN layer and the source and the drain respectively; A first pGaN layer and a first gate are sequentially grown on the surface of the second undoped GaN layer, and the upper layer 2DHG is led out through the first gate; A secondary epitaxial undoped GaN layer, a secondary epitaxial pGaN layer and a second gate are sequentially grown on the surface of the first undoped GaN layer between the first pGaN layer and the source electrode. The secondary epitaxial pGaN layer and the second gate are respectively maintained at the same height as the first pGaN layer and the first gate. The secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer both maintain a gap with the second AlGaN barrier layer and the second undoped GaN layer, and the lower layer 2DHG is led out through the second gate.

2. The dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 1, characterized in that: The substrate layer is a sapphire substrate.

3. The dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 1, characterized in that: The source electrode and the drain electrode are both made of Ni / Al / Ni / Au metal alloy.

4. The dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 3, characterized in that: The materials of the first gate and the second gate are both Ni / Au metal alloy.

5. A method for manufacturing the dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 1, characterized in that: The following steps are involved: S10, sequentially growing a GaN high resistance layer, a GaN channel layer, a first AlGaN barrier layer, a uGaN-1 layer, an AlGaN-2 layer, a uGaN-2 layer, and a pGaN-1 layer on the substrate layer; S20, sequentially forming the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at a predetermined position on the surface of the pGaN-1 layer; S30, repeating the steps of photolithography, etching, and stripping and cleaning to sequentially form the first pGaN layer, the second undoped GaN layer, and the second AlGaN barrier layer at a predetermined position on the surface of the pGaN-1 layer; S40, respectively photolithographically patterning the first gate and the second gate on the surface of the first pGaN layer and the secondary epitaxial pGaN layer, then evaporating the P ohmic contact by PVD process, stripping and cleaning, and then performing RTA annealing to form the first gate and the second gate; S50, patterning the source and drain electrodes at predetermined positions on the surface of the pGaN-1 layer, evaporating the N-ohm contact by PVD process, stripping and cleaning, and finally performing RTA annealing to form the source and drain electrodes.

6. The method for manufacturing a dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 5, characterized in that: In step S20, sequentially forming the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer at a predetermined position on the surface of the pGaN-1 layer specifically includes: S21, etching the range of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer on the surface of the pGaN-1 layer by using a positive photolithography process, removing the original AlGaN-2 layer, uGaN-2 layer, and pGaN-1 layer at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by using an ICP etching technology, and removing the photoresist and cleaning after the etching is completed; S22, forming a SiO2 layer on the surface of the pGaN-1 layer, etching the patterns of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by using a positive photolithography process, then removing the SiO2 layer of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer pattern portion by using a wet HF etching method, and finally removing the resist by using a cleaning process; S23, growing the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer successively at the positions of the secondary epitaxial pGaN layer and the secondary epitaxial undoped GaN layer by the MOCVD secondary epitaxial method, and then removing the SiO2 layer except the secondary epitaxial pGaN layer by wet HF etching, so that gaps are maintained around the secondary epitaxial undoped GaN layer and the secondary epitaxial pGaN layer.

7. The method for manufacturing a dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 6, characterized in that: In step S40 , the RTA annealing environment is an atmospheric environment, and the RTA annealing temperature is 600° C. to 650° C.

8. The method for manufacturing a dual-channel multi-gate high withstand voltage GaN HEMT device according to claim 6, characterized in that: In step S50, the RTA annealing environment is a N2@1SLM environment, and the RTA annealing temperature is 750°C to 950°C.

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