Antistatic LED device and preparation method thereof

Abstract

The invention relates to an antistatic LED device and a preparation method thereof. The device structure sequentially comprises a substrate layer; a first semiconductor layer; a first stress release layer; a second stress release layer; an active layer; a second semiconductor layer; an electrode layer; the first anti-static layer is located between the first stress release layer and the second stress release layer, and the first anti-static layer is an n-type doped GaN layer; wherein the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conduction types; the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the second stress release layer. The antistatic LED device provided by the invention can effectively improve the antistatic capability and the electrical property of the LED device, thereby improving the reliability and prolonging the service life of the device in various applications.

Description

Technical Field

[0001] The invention relates to the technical field of antistatic LED devices, and in particular to an antistatic LED device and a preparation method thereof. Background Art

[0002] Electrostatic Discharge (ESD) refers to the phenomenon that when two objects with different charges come into contact or close to each other, the charge is instantly transferred. ESD may damage electronic equipment and components, so anti-static measures need to be taken during the electronic manufacturing and assembly process to prevent damage caused by electrostatic discharge.

[0003] For LED products, their anti-ESD capability cannot be ignored. LED products may be affected by electrostatic discharge during production, transportation and use, resulting in product damage, performance degradation or even failure. Therefore, LED products with good ESD protection capabilities are more popular in the market.

[0004] The Human Body Model (HBM) is a standard method for testing the antistatic ability of electronic components. The antistatic ability (HBM) of large-size LEDs is generally required to reach 5kV, and some high-performance LEDs may reach a higher level to meet the needs of different application scenarios. However, the epitaxial structure of existing LED devices does not have an antistatic structure, so it is easily affected by electrostatic discharge, thereby reducing the electrical performance of LED devices and reducing the reliability and life of the devices.

[0005] Therefore, a solution is needed to effectively improve the antistatic ability and electrical performance of LED devices through the design and optimization of LED epitaxial structure, thereby improving the reliability and life of the devices in various applications. Summary of the invention

[0006] Therefore, the present invention provides an antistatic LED device and a preparation method thereof to solve the problem that the epitaxial structure of the existing LED device is not provided with an antistatic structure and is therefore easily affected by electrostatic discharge, thereby reducing the electrical performance of the LED device and reducing the reliability and life of the device.

[0007] The present invention provides an antistatic LED device, comprising:

[0008] substrate layer;

[0009] A first semiconductor layer, located on one side of the substrate layer;

[0010] A first stress release layer is located on a surface of the first semiconductor layer facing away from the substrate layer;

[0011] a second stress release layer, located on a side of the first stress release layer facing away from the first semiconductor layer;

[0012] An active layer is located on a surface of the second stress release layer facing away from the first stress release layer;

[0013] A second semiconductor layer is located on a surface of the active layer facing away from the second stress release layer;

[0014] an electrode layer, located on a surface of the second semiconductor layer facing away from the active layer;

[0015] It also includes: a first antistatic layer, located between the first stress release layer and the second stress release layer, the first antistatic layer being an n-type doped GaN layer;

[0016] Among them, the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conductivity types; the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the second stress release layer.

[0017] Optionally, the doping concentration of the first antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ;

[0018] The thickness of the first antistatic layer is 2nm-30nm.

[0019] Optionally, the first stress release layer is a superlattice layer composed of a first sub-stress release layer and a second sub-stress release layer alternately stacked in pairs; the first sub-stress release layer is In x Ga (1-X) N layer, the second stress release sub-layer is a GaN layer, an AlGaN layer or an n-GaN layer;

[0020] The second stress release layer is a superlattice layer composed of a third sub-stress release layer and a fourth sub-stress release layer alternately stacked in pairs; the third sub-stress release layer is In x Ga (1-X) N layer, the fourth stress release sub-layer is a GaN layer, an AlGaN layer or an n-GaN layer;

[0021] Wherein, the In content in the second stress release layer is greater than the In content in the first stress release layer; the thickness of the second sub-stress release layer is greater than the thickness of the fourth sub-stress release layer; the number of sub-stress release layers stacked in pairs in the second stress release layer is greater than the number of sub-stress release layers stacked in pairs in the first stress release layer;

[0022] Optionally, the number of pairs of the first sub-stress release layers and the second sub-stress release layers alternately stacked in pairs is 1 pair to 20 pairs;

[0023] The number of pairs of the third sub-stress release layer and the fourth sub-stress release layer alternately stacked in pairs is 2 to 40 pairs;

[0024] The thickness of the first stress release layer is 2nm-1000nm, and the thickness of the second stress release layer is 4nm-2000nm.

[0025] Optionally, the silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same;

[0026] The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first stress release layer; and greater than the silicon doping concentration of the second stress release layer;

[0027] or:

[0028] The silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same;

[0029] The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first stress release layer, and is less than the silicon doping concentration of the second stress release layer;

[0030] or:

[0031] The first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration;

[0032] The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first stress release sub-layer, and greater than the silicon doping concentration of the third stress release sub-layer;

[0033] or:

[0034] The first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration;

[0035] The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first stress release sub-layer, and is less than the silicon doping concentration of the third stress release sub-layer.

[0036] Optionally, when the silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same;

[0037] The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0038] The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the second stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0039] When the first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; and the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration;

[0040] The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first stress release sub-layer is 0.1 / cm 3 ~1E3 / cm 3 ;

[0041] The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the third stress release sub-layer is 0.1 / cm 3 ~1E3 / cm 3 .

[0042] Optionally, the antistatic LED device further comprises:

[0043] a second antistatic layer, located between the second stress release layer and the active layer, wherein the second antistatic layer is an n-type doped GaN layer;

[0044] The doping concentration of the second antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ;

[0045] The thickness of the second antistatic layer is 2 nm to 30 nm.

[0046] Optionally, the active layer includes a plurality of alternately stacked first multi-quantum well layers and second multi-quantum well layers, wherein the first multi-quantum well layer is In x Ga (1-X) N, the second multi-quantum well layer is GaN;

[0047] The period of alternating stacking of the first multi-quantum well layer and the second multi-quantum well layer is 3-10.

[0048] Optionally, the antistatic LED device further comprises:

[0049] A third antistatic layer is located between the first multi-quantum well layer and the second multi-quantum well layer; the third antistatic layer is an n-type doped GaN layer;

[0050] The doping concentration of the third antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ;

[0051] The thickness of the third antistatic layer is 2nm-30nm.

[0052] Optionally, the antistatic LED device further comprises:

[0053] A first AlN buffer layer is located on a surface of the substrate layer facing the first semiconductor layer;

[0054] The GaN connecting layer is located on the surface of the first AlN buffer layer facing away from the substrate layer; the GaN connecting layer includes a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer in sequence in the direction facing away from the first AlN buffer layer.

[0055] Optionally, the thickness of the first semiconductor layer is 1 μm to 4 μm, and the doping concentration of the first semiconductor layer is 1E18 / cm 3 ~5E19 / cm 3 ;

[0056] The second semiconductor layer includes, in sequence in a direction facing away from the active layer, a hole injection layer, an electron blocking layer, a lightly doped second semiconductor layer and a heavily doped second semiconductor layer;

[0057] The thickness of the hole injection layer is 10nm-30nm, the thickness of the electron blocking layer is 10nm-30nm, the thickness of the lightly doped second semiconductor layer is 10nm-100nm, and the thickness of the heavily doped second semiconductor layer is 5nm-20nm.

[0058] The present invention also provides a method for preparing an antistatic LED device, comprising the following steps: providing a substrate layer; forming an epitaxial layer: sequentially forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer; forming an electrode layer, and forming the electrode layer on the second semiconductor layer; further comprising: after forming the first stress release layer and before forming the second stress release layer, forming a first antistatic layer on the surface of the first stress release layer facing away from the first semiconductor layer; and forming the second stress release layer on the surface of the first antistatic layer facing away from the first stress release layer.

[0059] The technical solution of the present invention has the following advantages:

[0060] (1) The present invention can effectively improve the electrical performance and anti-static (ESD) capability of the LED by inserting a first anti-static layer (n-type doped GaN layer) between the first stress release layer and the second stress release layer. On the one hand, since the n-type doped GaN layer has a higher electrical conductivity, the transmission efficiency of electrons in the first stress release layer and the second stress release layer can be improved, thereby reducing static electricity accumulation and improving the anti-static capability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer and the second stress release layer, reduce local charge accumulation, reduce the risk of electrostatic discharge, improve the electrical performance of the LED, and improve the reliability and life of the device.

[0061] (2) The present invention can improve the transmission efficiency of electrons in the second stress release layer and the active layer by inserting a second antistatic layer (n-type doped GaN layer) between the second stress release layer and the active layer, thereby reducing static electricity accumulation. At the same time, it can also make the charge distribution in the second stress release layer and the active layer more uniform, reduce local charge accumulation, reduce the risk of electrostatic discharge, and improve the antistatic performance of the LED. In addition, since the active layer is a multi-quantum well structure, the introduction of the second antistatic layer can also optimize the band structure of the multi-quantum well and improve its overall electrical performance and electrostatic tolerance.

[0062] (3) The antistatic LED device provided by the present invention can optimize the energy band structure of the first multi-quantum well layer and the second multi-quantum well layer by inserting a third antistatic layer (n-type doped GaN layer) between the first multi-quantum well layer and the second multi-quantum well layer, thereby improving the overall electrical performance and electrostatic tolerance of the LED device. At the same time, the n-type doped GaN layer can improve the transmission efficiency of electrons in the first multi-quantum well layer and the second multi-quantum well layer, making the charge distribution of the first multi-quantum well layer and the second multi-quantum well layer more uniform, reducing local charge and static electricity accumulation, reducing the risk of electrostatic discharge, and improving the antistatic performance of the LED.

[0063] The method for preparing an antistatic LED device provided by the present invention can prepare the antistatic LED device provided by the present invention. By inserting a first antistatic layer (n-type doped GaN layer) between the first stress release layer and the second stress release layer, the electrical properties and antistatic (ESD) capabilities of the LED can be effectively improved. On the one hand, since the n-type doped GaN layer has a higher electrical conductivity, the transmission efficiency of electrons in the first stress release layer and the second stress release layer can be improved, thereby reducing static electricity accumulation and improving the antistatic capability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer and the second stress release layer, reduce local charge accumulation, reduce the risk of electrostatic discharge, and improve the electrical performance of the LED. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0065] Figure 1 This is a schematic structural diagram of an antistatic LED device according to an embodiment of the present invention;

[0066] Figure 2a It is a schematic diagram of the results of the antistatic test experiment of the traditional structure;

[0067] Figure 2b This is a schematic diagram of the results of an antistatic test experiment according to an embodiment of the present invention;

[0068] Figure 3 A schematic structural diagram of a first stress release layer according to an embodiment of the present invention;

[0069] Figure 4 It is a schematic structural diagram of a second stress release layer according to an embodiment of the present invention;

[0070] Figure 5a A schematic diagram of a silicon doping concentration according to an embodiment of the present invention;

[0071] Figure 5b is a schematic diagram of another silicon doping concentration according to an embodiment of the present invention;

[0072] Figure 5c A schematic diagram of another silicon doping concentration according to an embodiment of the present invention;

[0073] Figure 5d A schematic diagram of another silicon doping concentration according to an embodiment of the present invention;

[0074] Figure 6 It is a schematic structural diagram of another antistatic LED device according to an embodiment of the present invention;

[0075] Figure 7 is a schematic structural diagram of an active layer according to an embodiment of the present invention;

[0076] Figure 8 This is a schematic structural diagram of another antistatic LED device according to an embodiment of the present invention;

[0077] Fig. 9 A schematic diagram of a process for preparing an antistatic LED device according to an embodiment of the present invention;

[0078] Fig.10 A schematic diagram of a specific process of a method for preparing an antistatic LED device according to an embodiment of the present invention;

[0079] Description of reference numerals:

[0080] 1-substrate layer; 2-first semiconductor layer; 3-first stress release layer; 31-first sub-stress release layer; 32-second sub-stress release layer; 4-second stress release layer; 41-third sub-stress release layer; 42-fourth sub-stress release layer; 5-first antistatic layer; 6-active layer; 61-first multi-quantum well layer; 62-second multi-quantum well layer; 63-third antistatic layer; 7-second semiconductor layer; 8-electrode layer; 9-second antistatic layer; 10-first AlN buffer layer; 11-GaN connection layer. DETAILED DESCRIPTION

[0081] In order to solve the problem that the turn-on voltage of an antistatic LED device is high and the device injection current is small under an AC signal, resulting in low device luminous intensity and poor luminous effect, the present invention provides an antistatic LED device, comprising: a substrate layer; a first semiconductor layer, located on one side of the substrate layer; a first stress release layer, located on the surface of the first semiconductor layer facing away from the substrate layer; a second stress release layer, located on the side of the first stress release layer facing away from the first semiconductor layer; an active layer, located on the surface of the second stress release layer facing away from the first stress release layer; a second semiconductor layer, located on the surface of the active layer facing away from the second stress release layer; an electrode layer, located on the surface of the second semiconductor layer facing away from the active layer; and also comprising: a first antistatic layer, located between the first stress release layer and the second stress release layer, the first antistatic layer being an n-type doped GaN layer; wherein the first semiconductor layer and the second semiconductor layer are semiconductor layers of opposite conductivity types; the silicon doping concentration of the first antistatic layer is different from that of the first stress release layer, and the silicon doping concentration of the first antistatic layer is different from that of the second stress release layer.

[0082] The present invention also provides a method for preparing an antistatic LED device, comprising the following steps: providing a substrate layer; forming an epitaxial layer: sequentially forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer and a second semiconductor layer on the surface of the substrate layer; forming an electrode layer, and forming the electrode layer on the second semiconductor layer; further comprising: after forming the first stress release layer and before forming the second stress release layer, forming a first antistatic layer on the surface of the first stress release layer facing away from the first semiconductor layer; and forming the second stress release layer on the surface of the first antistatic layer facing away from the first stress release layer.

[0083] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0084] Example 1

[0085] refer to Figure 1 This embodiment provides an antistatic LED device, comprising:

[0086] Substrate layer 1;

[0087] A first semiconductor layer 2, located on one side of the substrate layer 1;

[0088] A first stress release layer 3, located on a surface of the first semiconductor layer 2 facing away from the substrate layer 1;

[0089] A second stress release layer 4, located on a side of the first stress release layer 3 facing away from the first semiconductor layer 2;

[0090] An active layer 6 is located on a surface of the second stress release layer 4 facing away from the first stress release layer 3;

[0091] A second semiconductor layer 7, located on a surface of the active layer 6 facing away from the second stress release layer 4;

[0092] an electrode layer 8, located on a surface of the second semiconductor layer 7 facing away from the active layer 6;

[0093] It also includes: a first antistatic layer 5, located between the first stress release layer 3 and the second stress release layer 4, and the first antistatic layer 5 is an n-type doped GaN layer;

[0094] Among them, the first semiconductor layer 2 and the second semiconductor layer 7 are semiconductor layers with opposite conductivity types; the silicon doping concentration of the first antistatic layer 5 is different from the silicon doping concentration of the first stress release layer 3, and the silicon doping concentration of the first antistatic layer 5 is different from the silicon doping concentration of the second stress release layer 4.

[0095] The present invention verifies the improvement effect of inserting the first antistatic layer 5 between the first stress release layer 3 and the second stress release layer 4 on the antistatic ability of the LED through experimental design. Two groups of LED samples are made, one group is a traditional structure, and the other group is an improved structure in which the first antistatic layer 5 is inserted between the first stress release layer 3 and the second stress release layer 4 (refer to the above Figure 1 ). The two groups of samples were subjected to chip process flow and standard HBM test to compare their ESD tolerance. If the chip cannot withstand the ESD voltage level, it will be broken down and leakage will occur. The ESD protection level and yield rate are evaluated accordingly. In the specific experiment, thousands of chips will be made on the epitaxial wafer, and 150 chips will be sampled for testing. The ESD protection limit value will be tested one by one. The structure of the entire epitaxial wafer is consistent. After statistics, the approximate ESD protection capability of this epitaxial wafer can be known. The experimental results are as follows Figure 2a-2b shown.

[0096] Figure 2a The test results for the traditional structure are as follows: Figure 2b 4K means that the chip is tested under an ESD voltage of 4000V, and then the chip is tested for leakage. If there is no leakage, it means that the chip can resist ESD to 4K level, and then gradually test the ESD resistance limit value to a larger ESD voltage.

[0097] It can be seen that compared with the traditional structure, the ESD HBM level of the structure of the present invention is improved from less than 4K to 8K, and the ESD HBM level of the entire epitaxial wafer is significantly improved, proving that the technical solution of the present invention can effectively improve the anti-static ability of the LED.

[0098] The present invention can effectively improve the electrical performance and anti-static (ESD) capability of the LED by inserting the first antistatic layer 5 (n-type doped GaN layer) between the first stress release layer 3 and the second stress release layer 4. On the one hand, since the n-type doped GaN layer has a higher electrical conductivity, the transmission efficiency of electrons in the first stress release layer and the second stress release layer can be improved, thereby reducing static electricity accumulation and improving the anti-static capability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer 3 and the second stress release layer 4, reduce local charge accumulation, reduce the risk of electrostatic discharge, improve the electrical performance of the LED, and improve the reliability and life of the device.

[0099] Furthermore, in this embodiment, the doping concentration of the first antistatic layer 5 is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the first antistatic layer 5 is 2nm to 30nm.

[0100] The silicon doping concentration of the first antistatic layer 5 is controlled at 2E17 / cm 3 ~1E19 / cm 3 When the antistatic ability of the device is effectively improved, if it is lower than 2E17 / cm 3 If it is higher than 1E19 / cm, there is no obvious silicon doping, which can not improve the antistatic ability. 3 , it will affect the luminous efficiency of the device.

[0101] When the thickness of the first antistatic layer 5 is 2nm to 30nm, the transmission efficiency of electrons in the first stress release layer 3 and the second stress release layer 4 can be effectively improved, so that the charges are distributed more evenly in the first stress release layer 3 and the second stress release layer 4, local charge accumulation is reduced, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the first antistatic layer 5 is less than 2nm, its conductive effect is weak and it cannot effectively disperse or absorb the charges of electrostatic discharge; if the thickness of the first antistatic layer 5 is greater than 30nm, it may increase the overall resistance and thickness of the LED, affect the electrical performance of the LED, and increase the difficulty of the process.

[0102] Furthermore, in this embodiment, if Figure 3 As shown, the first stress release layer 3 is a superlattice layer composed of a first sub-stress release layer 31 and a second sub-stress release layer 32 alternately stacked in pairs; the first sub-stress release layer 31 is In x Ga (1-X) N layer, the second stress release sub-layer 32 is a GaN layer, an AlGaN layer or an n-GaN layer;

[0103] like Figure 4 As shown, the second stress release layer 4 is a superlattice layer composed of a third sub-stress release layer 41 and a fourth sub-stress release layer 42 alternately stacked in pairs; the third sub-stress release layer 41 is In x Ga (1-X) N layer, the fourth stress release sub-layer 42 is a GaN layer, an AlGaN layer or an n-GaN layer;

[0104] The In content of the second stress release layer 4 is greater than the In content of the first stress release layer 3; the thickness of the second sub-stress release layer 32 is greater than the thickness of the fourth sub-stress release layer 42; the number of sub-stress release layers stacked in pairs in the second stress release layer 4 is greater than the number of sub-stress release layers stacked in pairs in the first stress release layer 3;

[0105] Further, in this embodiment, the number of pairs of the first sub-stress release layers 31 and the second sub-stress release layers 32 alternately stacked in pairs is 1 pair to 20 pairs;

[0106] The number of pairs of the third stress release sub-layers 41 and the fourth stress release sub-layers 42 alternately stacked in pairs is 2 to 40 pairs;

[0107] The thickness of the first stress release layer 3 is 2 nm to 1000 nm, and the thickness of the second stress release layer 4 is 4 nm to 2000 nm.

[0108] Furthermore, in some embodiments, the present invention controls the silicon doping concentration of the first antistatic layer 5 by taking into account the high and low combinations of different silicon doping concentrations in the first stress release layer 3 and the second stress release layer 4, so as to improve the antistatic ability of the LED.

[0109] In one embodiment, Figure 5a As shown, the silicon doping concentration of the first stress release sub-layer 31, the silicon doping concentration of the second stress release sub-layer 32, the silicon doping concentration of the third stress release sub-layer 41 and the silicon doping concentration of the fourth stress release sub-layer 42 are the same;

[0110] The silicon doping concentration of the first antistatic layer 5 is greater than the silicon doping concentration of the first stress release layer 3; and greater than the silicon doping concentration of the second stress release layer 4;

[0111] By inserting the first antistatic layer 5 (n-type doped GaN layer) into the first stress release layer 3 and the second stress release layer 4, and controlling the silicon doping concentration of the first antistatic layer 5 to form a doping concentration difference with the stress release layers on both sides, the electron transmission efficiency can be improved, the anti-static discharge capability of the LED can be significantly improved, and the risk of damage caused by static electricity can be reduced.

[0112] In another embodiment, Figure 5b As shown, the silicon doping concentration of the first stress release sub-layer 31, the silicon doping concentration of the second stress release sub-layer 32, the silicon doping concentration of the third stress release sub-layer 41 and the silicon doping concentration of the fourth stress release sub-layer 42 are the same;

[0113] The silicon doping concentration of the first antistatic layer 5 is less than the silicon doping concentration of the first stress release layer 3, and less than the silicon doping concentration of the second stress release layer 4;

[0114] By inserting the first antistatic layer 5 (n-type doped GaN layer) into the first stress release layer 3 and the second stress release layer 4, and controlling the silicon doping concentration of the first antistatic layer 5 to form a doping concentration difference with the stress release layers on both sides, the electron transmission efficiency can be improved, the anti-static discharge capability of the LED can be significantly improved, and the risk of damage caused by static electricity can be reduced.

[0115] In yet another embodiment, Figure 5c As shown, the first stress release sub-layer 31 and the third stress release sub-layer 41 are doped with silicon, and the second stress release sub-layer 32 and the fourth stress release sub-layer 42 are not doped with silicon; the first stress release sub-layer 31 and the third stress release sub-layer 41 have the same silicon doping concentration;

[0116] The silicon doping concentration of the first antistatic layer 5 is greater than the silicon doping concentration of the first stress release sub-layer 31 , and greater than the silicon doping concentration of the third stress release sub-layer 41 ;

[0117] By inserting a first antistatic layer 5 (n-type doped GaN layer) into the first stress release layer 3 and the second stress release layer 4, and controlling the silicon doping concentration of the first antistatic layer 5 to form a doping concentration difference with the first sub-stress release layer 31 and the third sub-stress release layer 41, the electron transmission efficiency can be improved, the anti-static discharge capability of the LED is significantly improved, the risk of damage caused by static electricity is reduced, and at the same time, the durability and life of the LED are improved, and the early failure caused by static electricity and other electrical stresses is reduced.

[0118] In yet another embodiment, Figure 5d As shown, the first stress release sub-layer 31 and the third stress release sub-layer 41 are doped with silicon, and the second stress release sub-layer 32 and the fourth stress release sub-layer 42 are not doped with silicon; the first stress release sub-layer 31 and the third stress release sub-layer 41 have the same silicon doping concentration;

[0119] The silicon doping concentration of the first antistatic layer 5 is lower than the silicon doping concentration of the first stress release sub-layer 31 , and lower than the silicon doping concentration of the third stress release sub-layer 32 .

[0120] By inserting the first antistatic layer 5 (n-type doped GaN layer) into the first stress release layer 3 and the second stress release layer 4, and controlling the silicon doping concentration of the first antistatic layer 5 and the first sub-stress release layer 31 and the third sub-stress release layer 41 to form a doping concentration difference, the electron transmission efficiency can be improved, and the anti-static discharge capability of the LED can be significantly improved.

[0121] Further, in this embodiment, when the silicon doping concentration of the first stress release sub-layer 31, the silicon doping concentration of the second stress release sub-layer 32, the silicon doping concentration of the third stress release sub-layer 41 and the silicon doping concentration of the fourth stress release sub-layer 42 are the same (i.e., the above Figure 5a and Figure 5b ),

[0122] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the first stress release layer 3 is 0.1 / cm 3 ~1E3 / cm 3 ;

[0123] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the second stress release layer 4 is 0.1 / cm 3 ~1E3 / cm 3 ;

[0124] The difference in silicon doping concentration between the first antistatic layer 5 and the first stress release layer 3 is controlled within 0.1 / cm 3 ~1E3 / cm 3 When the static electricity resistance of the device is less than 0.1 / cm 3 If it is higher than 1E3 / cm 3 , it will affect the luminous efficiency of the device.

[0125] Further, in this embodiment, when the first stress release layer 31 and the third stress release layer 41 are doped with silicon, the second stress release layer 32 and the fourth stress release layer 42 are not doped with silicon; when the silicon doping concentrations of the first stress release layer 31 and the third stress release layer 41 are the same (i.e., the above Figure 5c and Figure 5d situation);

[0126] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the first stress release sub-layer 31 is 0.1 / cm 3 ~1E3 / cm 3 ;

[0127] The difference between the silicon doping concentration of the first antistatic layer 5 and the doping concentration of the third stress release sub-layer 41 is 0.1 / cm 3 ~1E3 / cm 3 .

[0128] The difference in silicon doping concentration between the first antistatic layer 5 and the first stress release sub-layer 31, and the difference in silicon doping concentration between the first antistatic layer 5 and the third stress release sub-layer 41 are controlled within 0.1 / cm 3 ~1E3 / cm 3 When the antistatic effect is effectively improved, if it is less than 0.1 / cm 3 If it is higher than 1E3 / cm 3 , it will affect the luminous efficiency.

[0129] Furthermore, in some embodiments, Figure 6 As shown, the antistatic LED device also includes:

[0130] A second antistatic layer 9 is located between the second stress release layer 4 and the active layer 6, and the second antistatic layer 9 is an n-type doped GaN layer;

[0131] The doping concentration of the second antistatic layer 9 is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the second antistatic layer 9 is 2nm to 30nm.

[0132] The silicon doping concentration of the second antistatic layer 9 is controlled at 2E17 / cm 3 ~1E19 / cm 3 When the antistatic ability of the device is effectively improved, if it is lower than 2E17 / cm 3 If it is higher than 1E19 / cm 3 , it will affect the luminous efficiency of the device.

[0133] When the thickness of the second antistatic layer 9 is 2nm to 30nm, the transmission efficiency of electrons in the second stress release layer 4 and the active layer 6 can be effectively improved, so that the charges are more evenly distributed in the second stress release layer 4 and the active layer 6, local charge accumulation is reduced, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the second antistatic layer 9 is less than 2nm, its conductive effect is weak and it cannot effectively disperse or absorb the charges of electrostatic discharge; if the thickness of the second antistatic layer 9 is greater than 30nm, it may increase the overall resistance and thickness of the LED, affect the electrical performance of the LED, and increase the difficulty of the process.

[0134] This embodiment can improve the transmission efficiency of electrons in the second stress release layer 4 and the active layer 6 by inserting the second antistatic layer 9 (n-type doped GaN layer) between the second stress release layer 4 and the active layer 6, thereby reducing static electricity accumulation. At the same time, it can also make the charge distribution in the second stress release layer 4 and the active layer 6 more uniform, reduce local charge accumulation, reduce the risk of electrostatic discharge, and improve the antistatic performance of the LED. In addition, since the active layer 6 is a multi-quantum well structure, the introduction of the second antistatic layer 9 can also optimize the band structure of the multi-quantum well and improve its overall electrical performance and electrostatic tolerance.

[0135] Furthermore, in some embodiments, Figure 7 As shown, the active layer 6 includes a plurality of alternately stacked first multi-quantum well layers 61 and second multi-quantum well layers 62, wherein the first multi-quantum well layer is In x Ga (1-X) N, the second multi-quantum well layer is GaN;

[0136] The period of alternating stacking of the first multi-quantum well layer 61 and the second multi-quantum well layer 62 is 3-10.

[0137] Further, such as Figure 7 As shown, in some embodiments, the antistatic LED device further comprises:

[0138] A third antistatic layer 63 is located between the first multi-quantum well layer 61 and the second multi-quantum well layer 62; the third antistatic layer 63 is an n-type doped GaN layer;

[0139] In specific implementation, a third antistatic layer 63 can be inserted between any two layers of the alternately stacked first multi-quantum well layer 61 and the second multi-quantum well layer 62, or multiple third antistatic layers 63 can be inserted at multiple positions of the alternate stacking, which is not limited in this embodiment.

[0140] The doping concentration of the third antistatic layer 63 is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the third antistatic layer 63 is 2nm to 30nm.

[0141] The silicon doping concentration of the third antistatic layer 63 is controlled at 2E17 / cm 3 ~1E19 / cm 3 When the antistatic ability of the device is effectively improved, if it is lower than 2E17 / cm 3 If it is higher than 1E19 / cm 3 , it will affect the luminous efficiency of the device

[0142] When the thickness of the third antistatic layer 63 is 2nm to 30nm, the transmission efficiency of electrons in the first multi-quantum well layer 61 and the second multi-quantum well layer 62 can be effectively improved, so that the charges are distributed more evenly in the first multi-quantum well layer 61 and the second multi-quantum well layer 62, local charge accumulation is reduced, the risk of electrostatic discharge is reduced, and the electrical performance of the LED is improved. If the thickness of the third antistatic layer 63 is less than 2nm, its conductive effect is weak and it cannot effectively disperse or absorb the charge of electrostatic discharge; if the thickness of the first antistatic layer 63 is greater than 30nm, the overall resistance and thickness of the LED may be increased, affecting the electrical performance of the LED and increasing the process difficulty.

[0143] This embodiment can optimize the energy band structure of the first multi-quantum well layer 61 and the second multi-quantum well layer 62 by inserting the third antistatic layer 63 (n-type doped GaN layer) between the first multi-quantum well layer 61 and the second multi-quantum well layer 62, and improve the overall electrical performance and electrostatic tolerance of the LED device. At the same time, the n-type doped GaN layer can improve the transmission efficiency of electrons in the first multi-quantum well layer 61 and the second multi-quantum well layer 62, make the charge distribution of the first multi-quantum well layer 61 and the second multi-quantum well layer 62 more uniform, reduce local charge and static electricity accumulation, reduce the risk of electrostatic discharge, and improve the antistatic performance of the LED.

[0144] Furthermore, in this embodiment, if Figure 8 As shown, the antistatic LED device also includes:

[0145] A first AlN buffer layer 10, located on a surface of the substrate layer 1 facing the first semiconductor layer 2;

[0146] The GaN connecting layer 11 is located on the surface of the first AlN buffer layer 10 facing away from the substrate layer 1 ; the GaN connecting layer includes a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer in sequence in the direction facing away from the first AlN buffer layer 10 .

[0147] Furthermore, in this embodiment, the thickness of the first semiconductor layer 2 is 1 μm to 4 μm, and the doping concentration of the first semiconductor layer 2 is 1E18 / cm 3 To 5E19 / cm 3 ;

[0148] The second semiconductor layer 7 includes a hole injection layer, an electron blocking layer, a lightly doped second semiconductor layer and a heavily doped second semiconductor layer in sequence in a direction facing away from the active layer;

[0149] The thickness of the hole injection layer is 10nm-30nm, the thickness of the electron blocking layer is 10nm-30nm, the thickness of the lightly doped second semiconductor layer is 10nm-100nm, and the thickness of the heavily doped second semiconductor layer is 5nm-20nm.

[0150] Example 2

[0151] refer to Fig. 9 The present invention also provides a method for preparing an antistatic LED device, which is used to prepare the antistatic LED device of the above embodiment 1. The method comprises the following steps:

[0152] S101, providing a substrate layer;

[0153] S102, forming an epitaxial layer: sequentially growing a first semiconductor layer, a first stress release layer, a first antistatic layer, a second stress release layer, an active layer, and a second semiconductor layer on the surface of the substrate layer;

[0154] S103, forming an electrode layer, forming the electrode layer on the second semiconductor layer.

[0155] In a specific implementation, after forming the first stress release layer and before forming the second stress release layer, a first antistatic layer is formed on a surface of the first stress release layer facing away from the first semiconductor layer; and the second stress release layer is formed on a surface of the first antistatic layer facing away from the first stress release layer.

[0156] The method for preparing an antistatic LED device provided in this embodiment can prepare the antistatic LED device provided by the present invention. By inserting a first antistatic layer (n-type doped GaN layer) between the first stress release layer and the second stress release layer, the electrical properties and antistatic (ESD) capabilities of the LED can be effectively improved. On the one hand, since the n-type doped GaN layer has a higher electrical conductivity, the transmission efficiency of electrons in the first stress release layer and the second stress release layer can be improved, thereby reducing static electricity accumulation and improving the antistatic capability of the LED. On the other hand, the inserted n-type doped GaN layer can make the charge more evenly distributed in the first stress release layer and the second stress release layer, reduce local charge accumulation, reduce the risk of electrostatic discharge, and improve the electrical performance of the LED.

[0157] Example 3

[0158] refer to Fig.10 The present invention also provides a specific preparation method of an antistatic LED device, which is used to prepare the antistatic LED device of the above embodiment 1, and specifically comprises the following steps:

[0159] S201, using PVD (physical vapor deposition) to deposit a first AlN buffer layer on a substrate. Generally, a 4-inch, 6-inch or larger sapphire material is used as the substrate, and a silicon or silicon carbide substrate can also be used. The substrate surface is flat or has a graphic design. First, AlN material is deposited on the substrate by PVD, and the thickness of AlN is 10nm to 30nm.

[0160] S202, epitaxially grow a GaN connection layer on the substrate using MOCVD (metal organic chemical vapor deposition). The substrate connection layer includes three layers of materials: 1) low-temperature GaN nucleation layer (GaN Nucleation, growth temperature: 500℃~550℃, TMGa (trimethyl gallium) and NH3 (ammonia) reaction sources); 2) second AlN buffer layer (growth temperature: 900℃~1100℃, TMAl (trimethyl aluminum) and NH3 (ammonia) reaction sources); 3) undoped GaN layer (growth temperature: 1000℃~1100℃, TMGa (trimethyl gallium) and NH3 (ammonia) reaction sources). The thickness of this layer is between 1μm and 2.5μm.

[0161] S203, using MOCVD to grow the first semiconductor layer n-GaN layer. The thickness of n-GaN is between 1μm and 4μm (growth temperature: 1000℃~1200℃, TMGa (trimethylgallium) and NH3 (ammonia) reaction sources are introduced), and silicon is used as the n-type doping atom, and the silicon doping concentration is 1E18 / cm 3 To 5E19 / cm 3 range.

[0162] S204, using MOCVD to grow a first stress release layer. The first stress release layer includes 1 to 20 pairs of In x Ga (1-X) The superlattice is composed of N and GaN (or AlGaN or n-GaN), the Ga source in the material is TMGa (trimethyl gallium) or TEGa (triethyl gallium), the In source is TMIn (trimethyl indium), the indium ratio x is 0.1-5%, and the In x Ga (1-X) N thickness is 1nm to 10nm, GaN (or AlGaN or n-GaN) thickness is 1nm to 40nm;

[0163] S205, using MOCVD to grow a first antistatic layer. The first antistatic layer is an n-type doped GaN layer, the growth temperature is 760 to 900 degrees, and the silicon doping concentration is 2E17 / cm 3 To 1E19 / cm 3 The range of thickness is 2nm~30nm.

[0164] S206, using MOCVD to grow a second stress release layer. The second stress release layer is composed of 2 to 40 pairs of In x Ga (1-X) The superlattice structure is composed of N and GaN (or AlGaN or n-GaN), the Ga source in the material is TMGa (trimethyl gallium) or TEGa (triethyl gallium), the In source is TMIn (trimethyl indium), the indium ratio x is 5-25%, and the In x Ga (1-X) The thickness of N is 1nm to 10nm, and the thickness of GaN (or AlGaN or n-GaN) is 1nm to 40nm.

[0165] S207, using MOCVD to grow a light-emitting active layer structure. The light-emitting active layer is In x Ga (1-X) The multi-quantum well structure composed of N and GaN has a period of 3 to 10, and the indium component is between 10 and 30%. x Ga (1-X) The thickness of N is 2nm~4nm, and the thickness of GaN is 10nm~15nm.

[0166] S208, using MOCVD to grow the second semiconductor layer p-GaN. p-GaN is composed of the following layers in sequence: p-GaN hole injection layer, electron blocking layer, lightly doped p-GaN and heavily doped p-GaN layer. The thickness of the p-GaN hole injection layer is 10nm to 30nm, and the Mg doping concentration is 5E18 / cm 3 ~2E20 / cm 3 The electron blocking layer is composed of Mg-doped AlGaN with a thickness of 10nm to 30nm; the thickness of lightly doped p-GaN is 10nm to 100nm, and the Mg doping concentration is 5E18 / cm 3 ~1E19 / cm 3 ;Heavily doped p-GaN thickness is 5nm~20nm, Mg doping concentration is 5E19 / cm 3 ~5E20 / cm 3 .

[0167] S209, chip manufacturing process. Cleaning → evaporation of transparent electrode layer → transparent electrode pattern lithography → etching → degumming → platform pattern lithography → dry etching → degumming → annealing → SiO2 deposition → window pattern lithography → SiO2 etching → degumming → N-pole pattern lithography → pre-cleaning → coating → stripping → annealing → P-pole pattern lithography → coating → stripping → grinding → cutting → chip → finished product testing.

[0168] S210, chip EL test. Apply different currents and voltages to obtain the chip's electrical properties (such as turn-on voltage, leakage current, etc.) and luminous properties (wavelength, external quantum efficiency EQE, etc.). In addition, the anti-static ability under MM (machine model) and HBM modes will be tested to obtain the anti-static yield of the LED.

[0169] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. An antistatic LED device, characterized in that: include: substrate layer; A first semiconductor layer, located on one side of the substrate layer; A first stress release layer is located on a surface of the first semiconductor layer facing away from the substrate layer; a second stress release layer, located on a side of the first stress release layer facing away from the first semiconductor layer; An active layer is located on a surface of the second stress release layer facing away from the first stress release layer; A second semiconductor layer is located on a surface of the active layer facing away from the second stress release layer; an electrode layer, located on a surface of the second semiconductor layer facing away from the active layer; It also includes: a first antistatic layer, located between the first stress release layer and the second stress release layer, the first antistatic layer being an n-type doped GaN layer; Among them, the first semiconductor layer and the second semiconductor layer are semiconductor layers with opposite conductivity types; the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the first stress release layer, and the silicon doping concentration of the first antistatic layer is different from the silicon doping concentration of the second stress release layer.

2. The antistatic LED device according to claim 1, characterized in that: The doping concentration of the first antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the first antistatic layer is 2nm-30nm.

3. The antistatic LED device according to claim 1, characterized in that: The first stress release layer is a superlattice layer composed of a first sub-stress release layer and a second sub-stress release layer alternately stacked in pairs; the first sub-stress release layer is In x Ga (1-X) N layer, the second stress release sub-layer is a GaN layer, an AlGaN layer or an n-GaN layer; The second stress release layer is a superlattice layer composed of a third sub-stress release layer and a fourth sub-stress release layer alternately stacked in pairs; the third sub-stress release layer is In x Ga (1-X) N layer, the fourth stress release sub-layer is a GaN layer, an AlGaN layer or an n-GaN layer; Among them, the In content in the second stress release layer is greater than the In content in the first stress release layer; the thickness of the second sub-stress release layer is greater than the thickness of the fourth sub-stress release layer; the number of sub-stress release layers stacked in pairs in the second stress release layer is greater than the number of sub-stress release layers stacked in pairs in the first stress release layer.

4. The antistatic LED device according to claim 3, characterized in that: The number of pairs of the first stress release sub-layers and the second stress release sub-layers alternately stacked in pairs is 1 pair to 20 pairs; The number of pairs of the third sub-stress release layer and the fourth sub-stress release layer alternately stacked in pairs is 2 to 40 pairs; The thickness of the first stress release layer is 2nm-1000nm, and the thickness of the second stress release layer is 4nm-2000nm.

5. The antistatic LED device according to claim 4, characterized in that: The silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same; The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first stress release layer; and greater than the silicon doping concentration of the second stress release layer; or: The silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same; The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first stress release layer, and is less than the silicon doping concentration of the second stress release layer; or: The first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration; The silicon doping concentration of the first antistatic layer is greater than the silicon doping concentration of the first stress release sub-layer, and greater than the silicon doping concentration of the third stress release sub-layer; or: The first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration; The silicon doping concentration of the first antistatic layer is less than the silicon doping concentration of the first stress release sub-layer, and is less than the silicon doping concentration of the third stress release sub-layer.

6. The antistatic LED device according to claim 5, characterized in that: When the silicon doping concentration of the first stress release sub-layer, the silicon doping concentration of the second stress release sub-layer, the silicon doping concentration of the third stress release sub-layer and the silicon doping concentration of the fourth stress release sub-layer are the same; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the second stress release layer is 0.1 / cm 3 ~1E3 / cm 3 ; When the first stress release sub-layer and the third stress release sub-layer are doped with silicon, and the second stress release sub-layer and the fourth stress release sub-layer are not doped with silicon; and the first stress release sub-layer and the third stress release sub-layer have the same silicon doping concentration; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the first stress release sub-layer is 0.1 / cm 3 ~1E3 / cm 3 ; The difference between the silicon doping concentration of the first antistatic layer and the doping concentration of the third stress release sub-layer is 0.1 / cm 3 ~1E3 / cm 3 .

7. The antistatic LED device according to claim 1, characterized in that: The antistatic LED device also includes: a second antistatic layer, located between the second stress release layer and the active layer, wherein the second antistatic layer is an n-type doped GaN layer; The doping concentration of the second antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the second antistatic layer is 2 nm to 30 nm.

8. The antistatic LED device according to claim 1, characterized in that: The active layer includes a plurality of alternately stacked first multi-quantum well layers and second multi-quantum well layers, wherein the first multi-quantum well layer is In x Ga (1-X) N, the second multi-quantum well layer is GaN; The period of alternating stacking of the first multi-quantum well layer and the second multi-quantum well layer is 3-10.

9. The antistatic LED device according to claim 8, characterized in that: The antistatic LED device also includes: A third antistatic layer is located between the first multi-quantum well layer and the second multi-quantum well layer; the third antistatic layer is an n-type doped GaN layer; The doping concentration of the third antistatic layer is 2E17 / cm 3 ~1E19 / cm 3 ; The thickness of the third antistatic layer is 2nm-30nm.

10. The antistatic LED device according to claim 1, characterized in that: The antistatic LED device also includes: A first AlN buffer layer is located on a surface of the substrate layer facing the first semiconductor layer; The GaN connecting layer is located on the surface of the first AlN buffer layer facing away from the substrate layer; the GaN connecting layer includes a GaN nucleation layer, a second AlN buffer layer and an undoped GaN layer in sequence in the direction facing away from the first AlN buffer layer.

11. The antistatic LED device according to claim 1, characterized in that: The thickness of the first semiconductor layer is 1 μm to 4 μm, and the doping concentration of the first semiconductor layer is 1E18 / cm 3 ~5E19 / cm 3 ; The second semiconductor layer includes, in sequence in a direction facing away from the active layer, a hole injection layer, an electron blocking layer, a lightly doped second semiconductor layer and a heavily doped second semiconductor layer; The thickness of the hole injection layer is 10nm-30nm, the thickness of the electron blocking layer is 10nm-30nm, the thickness of the lightly doped second semiconductor layer is 10nm-100nm, and the thickness of the heavily doped second semiconductor layer is 5nm-20nm.

12. A method for preparing an antistatic LED device, characterized in that: The following steps are involved: providing a substrate layer; Forming an epitaxial layer: forming a first semiconductor layer, a first stress release layer, a second stress release layer, an active layer, and a second semiconductor layer in sequence on the surface of the substrate layer; forming an electrode layer, wherein the electrode layer is formed on the second semiconductor layer; Also includes: After forming the first stress release layer and before forming the second stress release layer, forming a first antistatic layer on a surface of the first stress release layer facing away from the first semiconductor layer; The second stress release layer is formed on a surface of the first antistatic layer facing away from the first stress release layer.

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