Packaging structure, packaging method and electronic equipment

Abstract

The invention provides a packaging structure, a packaging method and electronic equipment, relates to the technical field of semiconductor chip packaging, and reduces process steps and material types. The packaging structure comprises a chip, a rewiring layer, a definition layer and a first solder ball, the rewiring layer is located on one side of the chip and is electrically connected with the chip; the definition layer is located on one side, far away from the chip, of the rewiring layer, and the definition layer has adhesiveness and can be exposed and etched; the first solder balls are located on the side, away from the rewiring layer, of the definition layer, the definition layer is used for positioning the first solder balls, and the first solder balls are electrically connected with the rewiring layer. The definition layer plays at least two roles, firstly, the definition layer provides support for the rewiring layer obtained through subsequent preparation, and the adhesive force of the definition layer and the rewiring layer is good; and secondly, the definition layer is also used as a definition layer of the first solder ball obtained through subsequent preparation, and the accurate position of the first solder ball is determined. The definition layer replaces two film layers made of different materials in the related technology, and the two film layers made of different materials are prepared by two processes, so that the definition layer is adopted, the process steps and the material types are reduced, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor chip packaging, and in particular to a packaging structure, a packaging method and an electronic device. Background Art

[0002] Semiconductor board-level packaging has the technical advantages of high production efficiency and low process cost. Board-level packaging includes chip post-installation method, which usually processes and rewires the layer on the packaging substrate before soldering the chip. This method is low-cost and the resulting packaging structure has high reliability.

[0003] However, the current chip post-assembly method has problems such as many process steps and complex material types. Summary of the invention

[0004] In order to solve the above technical problems, the present application is proposed. The embodiments of the present application provide a packaging structure, a packaging method and an electronic device, which reduce the process steps and the types of materials.

[0005] In the first aspect, an embodiment of the present application provides a packaging structure, which includes a chip, a rewiring layer, a definition layer and a first solder ball; wherein the rewiring layer is located on one side of the chip, and the rewiring layer and the chip are electrically connected; the definition layer is located on the side of the rewiring layer away from the chip, the definition layer has adhesion, and can be exposed and etched; the first solder ball is located on the side of the definition layer away from the rewiring layer, the definition layer is used to position the first solder ball, and the first solder ball and the rewiring layer are electrically connected.

[0006] In combination with the first aspect, in certain implementations of the first aspect, the definition layer includes a polyimide layer; preferably, the definition layer also includes a silicon compound layer, and the silicon compound layer is located between the polyimide layer and the rewiring layer.

[0007] Preferably, the silicon compound layer includes a silicon oxide layer and / or a silicon nitride layer.

[0008] In combination with the first aspect, in some implementations of the first aspect, the definition layer further includes an opening, and a portion of the first solder ball is located in the opening.

[0009] Preferably, the redistribution layer includes a first soldering terminal, and the first soldering terminal is in contact with the first solder ball.

[0010] Preferably, the film layer in the first welding end that contacts the first solder ball is any one of a first copper layer and a first gold layer.

[0011] Preferably, if the film layer in the first welding end that contacts the first welding ball is a first gold layer, the first welding end further includes a first palladium layer and a first nickel layer, and the first palladium layer is located between the first nickel layer and the first gold layer.

[0012] In combination with the first aspect, in some implementations of the first aspect, the packaging structure also includes a second solder ball, the second solder ball is located on a side of the redistribution layer close to the chip, the redistribution layer includes a second welding end, and the second welding end is in contact with one side of the second solder ball.

[0013] Preferably, the chip comprises a third soldering terminal, and the third soldering terminal is in contact with the other side of the second solder ball.

[0014] Preferably, the film layer in the second welding end that contacts one side of the second solder ball is a second copper layer or a second gold layer.

[0015] Preferably, the packaging structure further includes an insulating layer, the insulating layer is located between the definition layer and the chip, the insulating layer includes a plurality of conductive vias, the redistribution layer includes a plurality of stacked redistribution sub-layers, and adjacent redistribution sub-layers are electrically connected through the conductive vias.

[0016] Preferably, the packaging structure further includes a filling layer, the filling layer is located between the chip and the insulating layer, the filling layer includes a through hole, and the second welding end, the second solder ball and the third welding end are located in the through hole.

[0017] Preferably, the packaging structure further comprises a molding layer, which is located on a side of the chip away from the redistribution layer, and the molding layer at least covers the chip and the filling layer.

[0018] In the second aspect, an embodiment of the present application provides another packaging structure, which includes a chip, a rewiring layer and a first solder ball; wherein the rewiring layer is located on one side of the chip, and the rewiring layer and the chip are electrically connected; the first solder ball is located on the side of the rewiring layer away from the chip, the first solder ball is in contact with the rewiring layer, and the surface of the first solder ball except for the portion in contact with the rewiring layer is exposed.

[0019] In a third aspect, an embodiment of the present application provides a packaging method, which includes: preparing a definition layer and a rewiring layer in sequence on one side of a substrate; mounting a chip on a side of the rewiring layer away from the substrate; removing the substrate to expose the definition layer; removing at least part of the definition layer to expose the rewiring layer; preparing a first solder ball on the exposed surface of the rewiring layer to obtain a packaging structure.

[0020] In combination with the third aspect, in certain implementations of the third aspect, removing at least part of the definition layer to expose the rewiring layer includes: opening in the definition layer, the opening penetrating through the definition layer along the thickness direction of the definition layer, and the opening exposing the rewiring layer; preferably, the definition layer includes a polyimide layer and a silicon compound layer, and the polyimide layer is located between the substrate and the silicon compound layer; opening in the definition layer, the opening penetrating through the definition layer along the thickness direction of the definition layer, and the opening exposing the rewiring layer includes: etching part of the polyimide layer to expose part of the silicon compound layer; etching the exposed silicon compound layer to form an opening, and the opening exposes the rewiring layer.

[0021] Removing the definition layer to expose the rewiring layer includes: etching the entire polyimide layer to expose the silicon compound layer; etching the entire silicon compound layer to expose the rewiring layer.

[0022] In combination with the third aspect, in some implementations of the third aspect, the rewiring layer includes a first titanium layer and a first copper layer, the first titanium layer is located on a side of the first copper layer away from the chip; before preparing the first solder ball on the surface exposed by the rewiring layer, the packaging method further includes: removing the first titanium layer to expose the first copper layer; preparing the first solder ball on the surface exposed by the rewiring layer includes: preparing the first solder ball on the surface exposed by the first copper layer; or

[0023] Before preparing the first solder ball on the surface exposed by the rewiring layer, the packaging method also includes: removing the first titanium layer to expose the first copper layer; sequentially preparing a first nickel layer, a first palladium layer and a first gold layer on the surface exposed by the first copper layer; preparing the first solder ball on the surface exposed by the rewiring layer includes: preparing the first solder ball on the surface of the first gold layer away from the first nickel layer.

[0024] In combination with the third aspect, in certain implementations of the third aspect, preparing a rewiring layer includes: alternately preparing rewiring sub-layers and sub-insulating layers multiple times on the side of the definition layer away from the substrate, adjacent rewiring sub-layers are electrically connected through conductive vias in the sub-insulating layer to form a rewiring layer, and two or more sub-insulating layers constitute an insulating layer.

[0025] Preferably, before mounting the chip on the side of the rewiring layer away from the substrate, the packaging method further comprises: preparing a second solder ball on the side of the rewiring layer away from the substrate; mounting the chip on the side of the rewiring layer away from the substrate comprises: mounting the chip on the side of the second solder ball away from the substrate.

[0026] Preferably, after mounting the chip on the side of the rewiring layer away from the substrate, the packaging method further comprises: preparing a filling layer between the chip and the insulating layer; preparing a molding layer on the side of the chip away from the rewiring layer, the molding layer at least covering the chip and the filling layer.

[0027] Preferably, after preparing the first solder balls on the exposed surface of the redistribution layer, the packaging method further comprises: cutting the chips in units of chips.

[0028] In a fourth aspect, an embodiment of the present application provides an electronic device, and the electronic device includes the packaging structure provided by any of the above embodiments.

[0029] The packaging structure provided by the embodiment of the present application includes a chip, a rewiring layer, a definition layer, and a first solder ball; wherein the rewiring layer is located on one side of the chip, and the rewiring layer and the chip are electrically connected; the definition layer is located on the side of the rewiring layer away from the chip, and the definition layer has adhesiveness and can be exposed and etched; the first solder ball is located on the side of the definition layer away from the rewiring layer, and the definition layer is used to position the first solder ball, and the first solder ball and the rewiring layer are electrically connected. In the packaging structure provided by the present application, the definition layer plays at least two roles. Specifically, first, the definition layer provides support for the rewiring layer prepared subsequently, and the adhesion between the definition layer and the rewiring layer is good, thereby ensuring that the rewiring layer and the chip will not shift or loosen during the packaging process and use; second, the definition layer also serves as the definition layer of the first solder ball prepared subsequently, determines the precise position of the first solder ball, and defines the boundary of the first solder ball. Therefore, the definition layer replaces the two film layers of different materials in the related art, and the two film layers of different materials are prepared by two processes. Therefore, the present application adopts the definition layer, reduces the process steps and material types, and reduces the cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0031] Figure 1 Shown is a schematic structural diagram of a packaging structure provided in one embodiment of the present application.

[0032] Figure 2 Shown is a schematic structural diagram of a packaging structure provided in another embodiment of the present application.

[0033] Figure 3 Shown Figure 1 and 2 Schematic diagram of the structure of the intermediate product of the packaging structure shown.

[0034] Figure 4 Shown Figure 1 and 2 A schematic structural diagram of another intermediate product of the packaging structure shown.

[0035] Figure 5 Shown Figure 1 and 2 A schematic structural diagram of another intermediate product of the packaging structure shown.

[0036] Figure 6 Shown Figure 1A schematic structural diagram of another intermediate product of the packaging structure shown.

[0037] Figure 7 Shown Figure 2 A schematic structural diagram of another intermediate product of the packaging structure shown.

[0038] Figure 8 Shown is a schematic flow chart of a packaging method provided in one embodiment of the present application.

[0039] Fig. 9 Shown is a schematic flow chart of a packaging method provided in another embodiment of the present application.

[0040] Fig.10 Shown is a schematic structural diagram of an electronic device provided in one embodiment of the present application.

[0041] Figure numerals: packaging structure 100; chip 110; redistribution layer 120; first redistribution sub-layer 1201 and second redistribution sub-layer 1202; conductive via H; first conductive via H1; second conductive via H2; definition layer 130; first solder ball 140; second solder ball 150; first welding end 121; second welding end 122; third welding end 111; insulating layer 160; first sub-insulating layer 161; second sub-insulating layer 162; filling layer 170; molding layer 180; substrate A; electronic device 10. DETAILED DESCRIPTION

[0042] In the chip packaging method provided by the related art, a temporary bonding layer is usually used to provide support for the subsequently prepared rewiring layer, and the temporary bonding layer and the rewiring layer are bonded. However, before preparing the first solder ball, due to the low mechanical strength of the temporary bonding layer, it is impossible to open holes and pattern. Therefore, it is necessary to peel off the temporary bonding layer, and then prepare a photoresist layer, and etch the photoresist layer to open holes. The photoresist layer after etching the holes is used as the definition layer of the first solder ball. It can be seen that the packaging method provided by the related art needs to peel off the temporary bonding layer first, and then prepare the photoresist layer, which has the problems of many process steps and complex material types.

[0043] In order to solve the above technical problems, the present application provides a packaging structure, which includes a chip, a rewiring layer, a definition layer, and a first solder ball; wherein the rewiring layer is located on one side of the chip, and the rewiring layer and the chip are electrically connected; the definition layer is located on the side of the rewiring layer away from the chip, the definition layer has adhesion, and can be exposed and etched; and the first solder ball is located on the side of the definition layer away from the rewiring layer, the definition layer is used to define the first solder ball, and the first solder ball is electrically connected to the rewiring layer. In the packaging structure provided by the present application, the definition layer plays at least two roles. Specifically, first, the definition layer provides support for the rewiring layer prepared subsequently, and the definition layer and the rewiring layer have good adhesion, thereby ensuring that the rewiring layer and the chip will not shift or loosen during the packaging process and use; second, the definition layer also serves as a definition layer for the first solder ball prepared subsequently, determines the precise position of the first solder ball, and defines the boundary of the first solder ball. Therefore, the definition layer replaces the two film layers with different materials (temporary bonding layer and photoresist layer) in the related technology. The two film layers with different materials are prepared by two processes. Therefore, the present application adopts the definition layer, which reduces the process steps and material types, and reduces the cost.

[0044] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0045] In addition, in order to better illustrate the present application, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0046] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0047] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0048] Figure 1 FIG. 1 is a schematic diagram of a packaging structure provided by an embodiment of the present application. Figure 1As shown, an embodiment of the present application provides a packaging structure 100, which includes a chip 110, a rewiring layer 120, a definition layer 130, and a first solder ball 140; wherein the rewiring layer 120 is located on one side of the chip 110, and the rewiring layer 120 and the chip 110 are electrically connected; the definition layer 130 is located on the side of the rewiring layer 120 away from the chip 110, the definition layer has adhesion, and can be exposed and etched; the first solder ball 140 is located on the side of the definition layer 130 away from the rewiring layer 120, the definition layer 130 is used to define the first solder ball 140, and the first solder ball 140 and the rewiring layer 120 are electrically connected.

[0049] In the packaging structure 100 provided in the present application, the definition layer 130 plays at least two roles. Specifically, first, the definition layer 130 provides support for the subsequently prepared rewiring layer 120, and the adhesion between the definition layer 130 and the rewiring layer 120 is good, thereby ensuring that the rewiring layer 120 and the chip 110 will not shift or loosen during the packaging process and use; second, the definition layer 130 also serves as the definition layer 130 of the subsequently prepared first solder ball 140, determines the precise position of the first solder ball 140, and defines the boundary of the first solder ball 140. Therefore, the definition layer 130 replaces the two film layers of different materials (temporary bonding glue layer and photoresist layer) in the related art, and the two film layers of different materials are prepared by two processes. Therefore, the present application adopts the definition layer 130, reduces the process steps and material types, and reduces the cost.

[0050] Exemplarily, the definition layer 130 includes a polyimide layer. The polyimide layer is relatively uniform and smooth, and a high-precision metal line structure (such as the rewiring layer 120) can be easily prepared on its surface; at the same time, the polyimide layer can be easily peeled off from the substrate, and the mechanical properties of the peeled polyimide layer are good, so that it can be patterned with holes.

[0051] In some embodiments, the definition layer 130 further includes a silicon compound layer, and the silicon compound layer is located between the polyimide layer and the rewiring layer 120 .

[0052] Specifically, the silicon compound layer has good insulation properties, thereby isolating the rewiring layer 120 and the chip 110 from the external environment, preventing adverse factors of the external environment from interfering with and damaging the rewiring layer 120 and the chip 110; in addition, the silicon compound layer has good dielectric properties, thereby reducing the capacitive coupling effect between the rewiring layer 120 and the chip 110 and other circuit elements.

[0053] Preferably, the silicon compound layer includes a silicon oxide layer and / or a silicon nitride layer.

[0054] refer to Figure 1The definition layer 130 further includes an opening, and a portion of the first solder ball 140 is located in the opening.

[0055] The embodiment of the present application is electrically connected to the redistribution layer 120 via the first solder ball 140 , and the first solder ball 140 is also used to electrically connect to other circuit elements, thereby achieving electrical connection between the chip 110 and other circuit elements.

[0056] refer to Figure 1 Preferably, the redistribution layer 120 includes a first soldering terminal 121 , and the first soldering terminal 121 is in contact with the first solder ball 140 .

[0057] The embodiment of the present application provides a method for realizing electrical connection between the redistribution layer 120 and the first solder ball 140 , and the electrical connection between the two is realized by contacting the first soldering end 121 and the first solder ball 140 .

[0058] Preferably, the film layer in the first welding end 121 that contacts the first solder ball 140 is any one of a first copper layer and a first gold layer.

[0059] Preferably, if the film layer in the first welding end 121 that contacts the first welding ball 140 is a first gold layer, the first welding end 121 further includes a first palladium layer and a first nickel layer, and the first palladium layer is located between the first nickel layer and the first gold layer.

[0060] refer to Figure 1 The package structure 100 further includes a second solder ball 150, which is located on the side of the redistribution layer 120 close to the chip 110. The redistribution layer 120 includes a second solder terminal 122, which contacts one side of the second solder ball 150. Preferably, the chip 110 includes a third solder terminal 111, which contacts the other side of the second solder ball 150.

[0061] The embodiment of the present application provides a method for realizing electrical connection between the rewiring layer 120 and the chip 110 . The rewiring layer 120 and the chip 110 are in contact with the second solder balls 150 respectively, thereby realizing electrical connection between the rewiring layer 120 and the chip 110 .

[0062] Preferably, the film layer in the second welding end 122 that contacts one side of the second solder ball 150 is a second copper layer or a second gold layer.

[0063] refer to Figure 1 Preferably, the packaging structure 100 also includes an insulating layer 160, which is located between the definition layer 130 and the chip 110, and the insulating layer 160 includes a plurality of conductive vias. The rewiring layer 120 includes a plurality of stacked rewiring sublayers, and adjacent rewiring sublayers are electrically connected through the conductive vias H.

[0064] Exemplarily, the rewiring layer 120 includes two rewiring sub-layers, which are respectively defined as a first rewiring sub-layer 1201 and a second rewiring sub-layer 1202. Accordingly, the insulating layer 160 includes a first sub-insulating layer 161 and a second sub-insulating layer 162. During the packaging process, a first welding terminal 121 is first prepared, and then a first sub-insulating material layer is prepared, and a hole is opened in the area of ​​the first sub-insulating material layer corresponding to the first welding terminal 121 to form a first sub-insulating layer 161 and a first conductive via H1; then a first rewiring sub-layer 1201 is prepared, the first rewiring sub-layer 1201 fills the first conductive via H1 and contacts the first welding terminal 121; then a second sub-insulating material layer is prepared on the first rewiring layer 1201, and a hole is opened in the second sub-insulating material layer, the hole exposes part of the first rewiring sub-layer 1201, to form a second sub-insulating layer 162 and a second conductive via H2; then a second rewiring sub-layer 1202 is prepared on the second sub-insulating layer 162, the second rewiring sub-layer 1202 fills the second conductive via H2 to contact the first rewiring sub-layer 1201; then a second welding terminal 122 is prepared above the position of the second sub-wiring layer 1202 corresponding to the second conductive via H2, so that the second welding section 122 and the second sub-wiring layer 1202 are in contact.

[0065] The insulating layer 160 has electrical insulation properties, which prevents other circuit elements or adverse external environmental factors from causing electrical interference and damage to the rewiring layer 120; in addition, the insulating layer 160 also plays a shielding role to prevent external electromagnetic interference from causing adverse effects on the rewiring layer 120, so as to ensure the normal operation of the rewiring layer 120 and the chip 110.

[0066] refer to Figure 1 Preferably, the package structure 100 further includes a filling layer 170, the filling layer 170 is located between the chip 110 and the insulating layer 160, the filling layer 170 includes a through hole, and the second welding end 122, the second solder ball 150 and the third welding end 111 are located in the through hole.

[0067] The filling layer 170 fills the gap between the chip 110 and the insulating layer 160, and plays a role in fixing the chip 110 and other packaging components (such as the insulating layer 160, the second welding end 122, the second solder ball 150 and the third welding end 111, etc.), thereby improving the stability of the packaging structure 100 and reducing the risk of vibration and deformation of the packaging structure 100.

[0068] refer to Figure 1 Preferably, the package structure 100 further includes a molding layer 180 , which is located on a side of the chip 110 away from the redistribution layer 120 , and the molding layer 180 at least covers the chip 110 and the filling layer 170 .

[0069] The molding layer 180 protects the chip 110 from being affected by the external environment (such as dust, moisture, chemicals, etc.), thereby extending the service life of the chip 110 and improving the stability of the chip 110 .

[0070] In some embodiments, the molding layer 180 includes a resin material.

[0071] Figure 2 FIG. 1 is a schematic diagram of a packaging structure provided by another embodiment of the present application. Figure 2 As shown, an embodiment of the present application provides another packaging structure 100, which includes a chip 110, a rewiring layer 120 and a first solder ball 140; wherein the rewiring layer 120 is located on one side of the chip 110, and the rewiring layer 120 and the chip 110 are electrically connected; the first solder ball 140 is located on the side of the rewiring layer 120 away from the chip 110, and the first solder ball 140 is in contact with the rewiring layer 120, and the surface of the first solder ball 140 except for the portion in contact with the rewiring layer 120 is exposed.

[0072] In the packaging structure 100 provided in the embodiment of the present application, a definition layer is not included, so there is no need to prepare a film layer for defining the first solder ball 140, thereby reducing process steps and material types and lowering costs.

[0073] The packaging structure 100 provided in the present application is described in detail above. The packaging method corresponding to the packaging structure 100 is introduced below. The structure mentioned in the packaging method can refer to the content of the above-mentioned packaging structure 100 and will not be repeated here.

[0074] Figure 3 Shown Figure 1 and 2 Schematic diagram of the structure of the intermediate product of the packaging structure shown. Figure 4 Shown Figure 1 and 2 A schematic structural diagram of another intermediate product of the packaging structure shown. Figure 5 Shown Figure 1 and 2 A schematic structural diagram of another intermediate product of the packaging structure shown. Figure 6 Shown Figure 1 A schematic structural diagram of another intermediate product of the packaging structure shown. Figure 7 Shown Figure 2 A schematic structural diagram of another intermediate product of the packaging structure shown.

[0075] Figure 8 FIG. 1 is a flow chart of a packaging method provided by an embodiment of the present application. Figure 8 As shown, an embodiment of the present application provides a packaging method, which includes the following steps.

[0076] Step S801 , preparing a definition layer 130 and a redistribution layer 120 on one side of the substrate A in sequence.

[0077] refer to Figure 3 , on one side of the substrate A, the definition layer 130 and the first welding end 121 of the redistribution layer 120 are sequentially prepared. Figure 4 FIG. 1 is a schematic diagram of the structure after the redistribution layer 120 is obtained.

[0078] In one embodiment, the substrate A may be a glass substrate.

[0079] Step S802, reference Figure 5 , the chip 110 is mounted on the side of the redistribution layer 120 away from the substrate A.

[0080] Step S803, reference Figure 6 , remove the substrate A to expose the definition layer 130. The definition layer has adhesion and can be exposed and etched.

[0081] Step S804, reference Figure 6 , at least a portion of the definition layer 130 is removed, so that the redistribution layer 120 is exposed.

[0082] For example, an opening is formed in the definition layer 130, and the opening penetrates the definition layer 130 along the thickness direction of the definition layer 130, and the opening exposes the rewiring layer 120. For another example, the definition layer 130 is removed to expose the rewiring layer 120 (refer to Figure 7 ).

[0083] It should be noted that the embodiment of the present application does not limit the execution order of step S803 and step S804. Exemplarily, step S804 can be executed after step S803, that is, first remove the substrate A to expose the definition layer; then remove at least part of the definition layer 130 to expose the rewiring layer 120. Alternatively, step S803 and step S804 are executed simultaneously, that is, while removing at least part of the definition layer 130, the substrate A falls off along with the definition layer 130.

[0084] Step S805, reference Figure 1 and 2 , a first solder ball 140 is prepared on the exposed surface of the redistribution layer 120 to obtain the package structure 100 .

[0085] The packaging method provided in the embodiment of the present application has the advantages of fewer process steps, fewer material types and lower cost.

[0086] In addition, since the substrate A is hard and flat, the rewiring layer 120 is prepared on the substrate A. Therefore, the thickness of the rewiring layer 120 is relatively uniform and flat, so that the first solder ball 140 can be easily prepared on the exposed surface of the rewiring layer 120. In this way, the process flow of preparing the first solder ball 140 is simpler and the cost is lower.

[0087] In some embodiments, the definition layer 130 includes a polyimide layer and a silicon compound layer, and the polyimide layer is located between the substrate A and the silicon compound layer; an opening is opened in the definition layer 130, and the opening exposes the rewiring layer 120, including: etching a portion of the polyimide layer to expose a portion of the silicon compound layer; etching the exposed silicon compound layer to form an opening, and the opening exposes the rewiring layer 120.

[0088] Removing the definition layer 130 to expose the rewiring layer 120 includes: etching the entire polyimide layer to expose the silicon compound layer; etching the entire silicon compound layer to expose the rewiring layer 120 .

[0089] In one embodiment, the polyimide layer is etched by laser etching, and the silicon compound layer is etched by dry etching.

[0090] The embodiment of the present application achieves the purpose of exposing the rewiring layer 120 through two etching processes.

[0091] In some embodiments, the rewiring layer 120 includes a first titanium layer and a first copper layer, and the first titanium layer is located on the side of the first copper layer away from the chip; before preparing the first solder ball 140 on the exposed surface of the rewiring layer 120, the packaging method also includes: removing the first titanium layer to expose the first copper layer; preparing the first solder ball 140 on the exposed surface of the rewiring layer 120 includes: preparing the first solder ball 140 on the exposed surface of the first copper layer.

[0092] The first titanium layer and the definition layer 130 have good adhesion, but the first titanium layer and the first solder ball 140 have poor bonding. Therefore, in the embodiment of the present application, the first titanium layer is removed, and the first solder ball 140 is prepared on the exposed surface of the first copper layer, thereby improving the bonding force between the rewiring layer 120 and the first solder ball 140 and improving the firmness of the connection between the rewiring layer 120 and the first solder ball 140.

[0093] Or before preparing the first solder ball 140 on the exposed surface of the re-wiring layer 120, the packaging method also includes: removing the first titanium layer to expose the first copper layer; sequentially preparing a first nickel layer, a first palladium layer and a first gold layer on the exposed surface of the first copper layer; preparing the first solder ball 140 on the exposed surface of the re-wiring layer 120 includes: preparing the first solder ball 140 on the surface of the first gold layer away from the first nickel layer.

[0094] The first gold layer has good stability and is not easily oxidized. Therefore, in the embodiment of the present application, the first solder ball 140 is prepared on the surface of the first gold layer, which improves the stability of the package structure 100, further improves the bonding force between the redistribution layer 120 and the first solder ball 140, and further improves the firmness of the connection between the redistribution layer 120 and the first solder ball 140.

[0095] In some embodiments, preparing the rewiring layer 120 includes: alternately preparing rewiring sublayers 1201 and sub-insulating layers multiple times on the side of the definition layer 130 away from the substrate A, adjacent rewiring sublayers 131 are electrically connected through conductive vias H in the sub-insulating layer to form the rewiring layer 120, and two or more sub-insulating layers constitute the insulating layer 160.

[0096] It should be noted that the rewiring sublayer is a patterned structure, and the orthographic projection of the rewiring sublayer on the substrate A covers a partial area of ​​the substrate A. In this case, the sub-insulating layer adjacent to the rewiring sublayer and located on the side of the rewiring sublayer away from the substrate A will fill the hollow area enclosed by the rewiring sublayer.

[0097] Preferably, before mounting the chip 110 on the side of the re-wiring layer 120 away from the substrate A, the packaging method further includes: preparing a second solder ball 150 on the side of the re-wiring layer 120 away from the substrate A; mounting the chip 110 on the side of the re-wiring layer 120 away from the substrate A includes: mounting the chip 110 on the side of the second solder ball 150 away from the substrate A.

[0098] Preferably, after the chip 110 is mounted on the side of the rewiring layer 120 away from the substrate A, the packaging method further includes: preparing a filling layer 170 between the chip 110 and the insulating layer 160; preparing a molding layer 180 on the side of the chip 110 away from the rewiring layer 120, and the molding layer 180 at least covers the chip 110 and the filling layer 170.

[0099] Preferably, after preparing the first solder balls 140 on the exposed surface of the redistribution layer 120 , the packaging method further comprises: cutting the chips 110 as units.

[0100] Fig. 9 Shown is a schematic flow chart of a packaging method provided in another embodiment of the present application. Fig. 9 The execution order of the above mentioned packaging steps is provided, such as Fig. 9 As shown, the packaging method includes the following steps.

[0101] Step S901 , preparing a definition layer 130 and a redistribution layer 120 on one side of the substrate A in sequence.

[0102] Step S902, reference Figure 4 , a second solder ball 150 is prepared on the side of the redistribution layer 120 away from the substrate A.

[0103] Step S903, reference Figure 5 The chip 110 is mounted on the side of the second solder ball 150 away from the substrate A.

[0104] Step S904, reference Figure 5 , a filling layer 170 is prepared between the chip 110 and the insulating layer 160 .

[0105] Step S905, reference Figure 6 and 7 A molding layer 180 is prepared on a side of the chip 110 away from the redistribution layer 120 , and the molding layer 180 at least covers the chip 110 and the filling layer 170 .

[0106] Step S906 , removing the substrate A to expose the definition layer 130 .

[0107] Step S907 , opening is formed in the definition layer 130 , the opening penetrates the definition layer 130 along the thickness direction of the definition layer 130 , and the opening exposes the rewiring layer 120 ; or the definition layer 130 is removed to expose the rewiring layer 120 .

[0108] Step S908 , removing the first titanium layer to expose the first copper layer.

[0109] Step S909, reference Figure 1 and 2 A first solder ball 140 is prepared on the exposed surface of the first copper layer.

[0110] Alternatively, steps S908 and S909 may also be replaced by the following steps S908' to S9010'.

[0111] Step S908 ′, removing the first titanium layer to expose the first copper layer.

[0112] Step S909 ′, sequentially preparing a first nickel layer, a first palladium layer and a first gold layer on the exposed surface of the first copper layer.

[0113] Step S9010', reference Figure 1 and 2 A first solder ball 140 is prepared on a surface of the first gold layer away from the first nickel layer.

[0114] Step S9011 , cutting the chip 110 as a unit to obtain a package structure 100 .

[0115] Fig.10 FIG. 1 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present application. Fig.10 As shown, an embodiment of the present application provides an electronic device 10, and the electronic device 10 includes a packaging structure 100 provided by any of the above embodiments. The technical principles and effects produced are similar and will not be repeated here.

[0116] The packaging structure 100 can be applied to an electronic device 10, which can be, for example, a mobile terminal, a tablet computer, a computer monitor, a television, a wearable device, an information query machine, or other products or components.

[0117] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0118] It should also be noted that, in the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present application. Although multiple exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize some variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. A packaging structure, It is characterized in that include: chip; A rewiring layer, located at one side of the chip, the rewiring layer being electrically connected to the chip; A definition layer, located on a side of the rewiring layer away from the chip, the definition layer has adhesiveness and can be exposed and etched; as well as The first solder ball is located at a side of the definition layer away from the rewiring layer. The definition layer is used to position the first solder ball. The first solder ball is electrically connected to the rewiring layer.

2. The packaging structure according to claim 1, It is characterized in that The definition layer includes a polyimide layer; Preferably, the definition layer further comprises a silicon compound layer, and the silicon compound layer is located between the polyimide layer and the rewiring layer; Preferably, the silicon compound layer includes a silicon oxide layer and / or a silicon nitride layer.

3. The packaging structure according to claim 1, It is characterized in that The definition layer is provided with an opening, and part of the first solder balls are located in the opening; Preferably, the rewiring layer comprises a first welding end, and the first welding end is in contact with the first solder ball; Preferably, the film layer in the first welding end that contacts the first solder ball is any one of a first copper layer and a first gold layer; Preferably, if the film layer in the first welding end that contacts the first welding ball is the first gold layer, the first welding end further includes a first palladium layer and a first nickel layer, and the first palladium layer is located between the first nickel layer and the first gold layer.

4. The packaging structure according to any one of claims 1 to 3, It is characterized in that Also comprising a second solder ball, the second solder ball is located between the redistribution layer and the chip, the redistribution layer comprises a second soldering end, the second soldering end is in contact with one side of the second solder ball; Preferably, the chip comprises a third welding end, and the third welding end is in contact with a side of the second solder ball away from the rewiring layer; Preferably, the film layer in the second welding end that contacts one side of the second solder ball is a second copper layer or a second gold layer; Preferably, the packaging structure further comprises an insulating layer, the insulating layer is located between the definition layer and the chip, the insulating layer comprises a plurality of conductive vias, the rewiring layer comprises a plurality of stacked rewiring sub-layers, and adjacent rewiring sub-layers are electrically connected through the conductive vias; Preferably, the packaging structure further comprises a filling layer, the filling layer is located between the chip and the insulating layer, the filling layer is provided with a through hole, and the second welding end, the second solder ball and the third welding end are located in the through hole; Preferably, the packaging structure further comprises a molding layer, wherein the molding layer is located on a side of the chip away from the redistribution layer, and the molding layer at least covers the chip and the filling layer.

5. A packaging structure, It is characterized in that include: chip; A rewiring layer, located at one side of the chip, the rewiring layer being electrically connected to the chip; The first solder ball is located at a side of the rewiring layer away from the chip. The first solder ball contacts the rewiring layer. The surface of the first solder ball except the portion in contact with the rewiring layer is exposed.

6. A packaging method, It is characterized in that include: sequentially preparing a definition layer and a redistribution layer on one side of the substrate; Mounting a chip on a side of the redistribution layer away from the substrate; removing the substrate to expose the definition layer; removing at least a portion of the definition layer such that the rewiring layer is exposed; A first solder ball is prepared on the exposed surface of the redistribution layer to obtain a packaging structure.

7. The packaging method according to claim 6, It is characterized in that The removing at least a portion of the definition layer so that the rewiring layer is exposed comprises: An opening is formed in the definition layer, wherein the opening penetrates the definition layer along a thickness direction of the definition layer, and the opening exposes the rewiring layer; Preferably, the definition layer comprises a polyimide layer and a silicon compound layer, the polyimide layer is located between the substrate and the silicon compound layer; an opening is provided in the definition layer, the opening penetrates the definition layer along the thickness direction of the definition layer, and the opening exposes the rewiring layer, comprising: Etching a portion of the polyimide layer to expose a portion of the silicon compound layer; Etching the exposed silicon compound layer to form the opening, wherein the opening exposes the rewiring layer; Removing the definition layer to expose the rewiring layer comprises: Etching the entire polyimide layer to expose the silicon compound layer; The entire silicon compound layer is etched to expose the rewiring layer.

8. The packaging method according to claim 6, It is characterized in that The rewiring layer comprises a first titanium layer and a first copper layer, wherein the first titanium layer is located on a side of the first copper layer away from the chip; Before preparing the first solder ball on the surface exposed by the redistribution layer, the method further comprises: removing the first titanium layer to expose the first copper layer; The step of preparing a first solder ball on the surface exposed by the redistribution layer comprises: preparing the first solder ball on the exposed surface of the first copper layer; Preferably, before preparing the first solder ball on the exposed surface of the rewiring layer, the method further comprises: removing the first titanium layer to expose the first copper layer; Sequentially preparing a first nickel layer, a first palladium layer and a first gold layer on the exposed surface of the first copper layer; The step of preparing a first solder ball on the surface exposed by the redistribution layer comprises: The first solder ball is prepared on a surface of the first gold layer away from the first nickel layer.

9. The packaging method according to any one of claims 6 to 8, It is characterized in that The preparation of the rewiring layer comprises: On the side of the definition layer away from the substrate, rewiring sublayers and sub-insulating layers are alternately prepared multiple times, adjacent rewiring sublayers are electrically connected through conductive vias in the sub-insulating layers to form the rewiring layer, and two or more sub-insulating layers form an insulating layer; Preferably, before mounting a chip on the side of the rewiring layer away from the substrate, the method further comprises: Prepare a second solder ball on a side of the redistribution layer away from the substrate; The step of mounting a chip on the side of the rewiring layer away from the substrate comprises: Mounting a chip on the side of the second solder ball away from the substrate; Preferably, after mounting the chip on the side of the rewiring layer away from the substrate, the method further comprises: preparing a filling layer between the chip and the insulating layer; Preparing a molding layer on a side of the chip away from the rewiring layer, wherein the molding layer at least covers the chip and the filling layer; Preferably, after preparing the first solder ball on the exposed surface of the rewiring layer, the method further comprises: The chips are cut into units.

10. An electronic device, It is characterized in that The invention comprises the packaging structure as claimed in any one of claims 1 to 5.

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