Semiconductor structure and preparation method thereof, and memory

Abstract

The invention provides a semiconductor structure and a preparation method thereof, and a memory, relates to the technical field of semiconductors, and is used for solving the technical problem of poor channel control capability of a grid electrode, the semiconductor structure comprises a columnar first grid electrode, a semiconductor layer and an annular second grid electrode, and the first grid electrode extends along a first direction; the semiconductor layer covers at least part of the peripheral surface of the first grid electrode; the second gate wraps at least part of the peripheral surface of the semiconductor layer; the projection area of the second grid electrode on the semiconductor layer is a channel area; wherein the regions on the two sides of the channel region in the semiconductor layer are respectively a source region and a drain region; and gate dielectric layers are arranged between the first gate and the semiconductor layer and between the second gate and the semiconductor layer. Through the arrangement of the double gates, the control capability of the gates on the channel region can be improved.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for preparing the same, and a memory. Background Art

[0002] Semiconductor structures are usually provided on electronic devices such as memories and controllers. The semiconductor structures include transistors, which are used to implement functions such as switching and amplification. In related technologies, transistors include active structures and gates, wherein the active structure includes a channel region and a source region and a drain region located on both sides of the channel region. The gate is provided on the channel region, and the projection of the gate on the active structure at least covers the channel region. However, the above-mentioned gate has poor control over the channel region. Summary of the invention

[0003] In view of the above problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a memory, which are used to improve the control capability of a gate over a channel region.

[0004] A first aspect of an embodiment of the present disclosure provides a semiconductor structure, comprising: a transistor, wherein the transistor comprises:

[0005] A first columnar gate extending along a first direction;

[0006] A semiconductor layer, wherein the semiconductor layer covers at least a portion of an outer peripheral surface of the first gate;

[0007] A second annular gate, wherein the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer; the projection area of ​​the second gate on the semiconductor layer is a channel region; wherein the regions on both sides of the channel region in the semiconductor layer are a source region and a drain region, respectively; a gate dielectric layer is provided between the first gate and the semiconductor layer, and between the second gate and the semiconductor layer.

[0008] In some embodiments, along the first direction, the first gate includes a first end surface and a second end surface that are oppositely disposed; the semiconductor layer further covers the first end surface of the first gate;

[0009] The semiconductor structure also includes a first contact structure and a second contact structure. Along the first direction, the first contact structure and the second contact structure are respectively located on both sides of the second gate and are insulated from the second gate and the first gate; wherein one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

[0010] In some embodiments, the semiconductor layer includes a main body, a first extension and a second extension, the first extension and the second extension are both connected to the main body; the main body covers at least a portion of the outer circumference of the first gate, the second gate covers at least a portion of the outer circumference of the main body; and the projection area of ​​the second gate on the main body is a channel region;

[0011] The first extension portion covers the first end surface of the first gate;

[0012] The second gate includes a first surface and a second surface opposite to each other along the first direction, and the first surface corresponds to the first end surface; wherein the second extension portion is located on one side of the second surface of the second gate, or, is located on one side of the first surface and the second surface respectively, and is connected to the first contact structure or the second contact structure.

[0013] In some embodiments, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer;

[0014] The first gate dielectric layer is located between the semiconductor layer and the first gate and at least covers the outer peripheral surface of the first gate;

[0015] The second gate dielectric layer is located between the semiconductor layer and the second gate and covers the main body of the semiconductor layer;

[0016] A dielectric layer is disposed between the first contact structure and the second gate, and between the second contact structure and the second gate.

[0017] In some embodiments, materials of the semiconductor layer, the first contact structure, and the second contact structure all include indium gallium zinc oxide.

[0018] A second aspect of the present disclosure provides a method for preparing a semiconductor structure, which comprises the following steps:

[0019] forming a stacked structure, wherein the stacked structure comprises a first material layer, a first conductive material layer, and a second material layer stacked in sequence; the first material layer and the second material layer are both insulated from the first conductive material layer;

[0020] Removing a portion of the first conductive material layer and a portion of the second material layer to form a groove in the stacked structure, wherein the groove exposes a portion of the first material layer; wherein the retained first conductive material layer constitutes a second gate, and one of the first material layer and the retained second material layer forms a first contact structure, and the other forms a second contact structure;

[0021] A semiconductor layer, a gate dielectric layer and a first gate are formed in the groove; wherein the semiconductor layer covers at least a portion of the outer peripheral surface of the first gate, and the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer, and the region opposite to the semiconductor layer and the second gate is a channel region, the regions located on both sides of the channel region are source regions and drain regions, respectively, and the gate dielectric layer is respectively located between the first gate and the second gate and the semiconductor layer; one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

[0022] In some embodiments, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; and the step of forming the semiconductor layer and the gate dielectric layer in the trench includes:

[0023] forming a first gate dielectric layer on the sidewalls of the trench;

[0024] forming a semiconductor layer, wherein the semiconductor layer covers the uncovered bottom wall of the trench, the first gate dielectric layer, and the first contact structure or the second contact structure located above the second gate; wherein the semiconductor layer located on the first gate dielectric layer constitutes a main body, the semiconductor layer located on the bottom wall of the trench constitutes a first extension, and the semiconductor layer located on the first contact structure or the second contact structure located above the second gate constitutes a second extension;

[0025] A second gate dielectric layer is formed, wherein the second gate dielectric layer covers the semiconductor layer.

[0026] In some embodiments, the step of forming the first gate includes:

[0027] forming a second conductive material layer, wherein the second conductive material layer covers the area surrounded by the second gate dielectric layer and fills the area surrounded by the second gate dielectric layer;

[0028] A portion of the second conductive material layer is removed, and the second conductive material layer remaining in the area surrounded by the second gate dielectric layer constitutes the first gate.

[0029] In some embodiments, after the step of forming the stacked structure and before the step of removing a portion of the first conductive material layer and the second material layer, the method further includes:

[0030] The stacked structure is subjected to rapid thermal annealing at a preset temperature.

[0031] A third aspect of the embodiments of the present disclosure provides a memory, comprising the semiconductor structure described in the first aspect.

[0032] In the semiconductor structure and its preparation method and memory provided by the embodiments of the present disclosure, a first gate and a second gate are respectively arranged on both sides of the semiconductor layer perpendicular to the first direction. When voltage is applied to the first gate and the second gate, an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the first gate, and an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the second gate. In this way, the thickness of the inversion layer can be increased, the control ability of the first gate and the second gate over the channel region can be improved, and the power consumption of the transistor can be reduced.

[0033] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and its preparation method, and the memory provided by the embodiments of the present disclosure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0035] Figure 1 Schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 1 ;

[0036] Figure 2 Schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure Figure 2 ;

[0037] Figure 3 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0038] Figure 4 A schematic diagram of a semiconductor structure after a stacked structure is formed in the method for preparing the semiconductor structure provided in an embodiment of the present disclosure;

[0039] Figure 5 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure after a trench is formed;

[0040] Figure 6 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure after a gate dielectric material layer is formed;

[0041] Figure 7A schematic diagram of a semiconductor structure after forming a second gate dielectric layer in the method for preparing the semiconductor structure provided by an embodiment of the present disclosure;

[0042] Figure 8 A schematic diagram of a semiconductor layer after forming the semiconductor layer in the method for preparing the semiconductor structure provided by an embodiment of the present disclosure;

[0043] Fig. 9 A schematic diagram of a method for preparing a semiconductor structure provided in an embodiment of the present disclosure after a first gate dielectric layer is formed;

[0044] Fig.10 This is a schematic diagram of the semiconductor structure manufacturing method provided in an embodiment of the present disclosure after a second conductive material layer is formed.

[0045] Reference numerals:

[0046] 100: transistor; 110: first gate; 111: first end surface; 112: second end surface; 113: second conductive material layer; 120: semiconductor layer; 121: main body; 122: first extension; 123: second extension; 130: second gate; 131: first surface; 132: second surface; 141: first gate dielectric layer; 411: gate dielectric material layer; 142: second gate dielectric layer;

[0047] 200: substrate; 300: first contact structure; 400: second contact structure; 500: dielectric layer; 600: stacked structure; 610: first material layer; 620: dielectric material layer; 630: first conductive material layer; 640: second material layer; 650: groove. DETAILED DESCRIPTION

[0048] As described in the background technology, there is a problem in the related technology that the gate of the transistor has poor control over the channel region. The inventors have found that the reason for this problem is that current transistors are usually single-gate. When a voltage is applied to the gate, an inversion layer of a certain thickness is formed on the side of the channel region close to the gate. The thickness of the inversion layer is small, resulting in poor control of the gate over the channel region, thereby increasing the power consumption of the transistor.

[0049] In response to the above technical problems, an embodiment of the present disclosure provides a semiconductor structure and a method for preparing the same, wherein a first gate and a second gate are respectively arranged on both sides of a semiconductor layer perpendicular to a first direction. When voltage is applied to the first gate and the second gate, an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the first gate, and an inversion layer of a certain thickness is formed on the side of the semiconductor layer close to the second gate. In this way, the thickness of the inversion layer can be increased, the control capability of the first gate and the second gate over the channel region can be improved, and the power consumption of the transistor can be reduced.

[0050] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0051] Please refer to the attached Figure 1 The present disclosure provides a semiconductor structure, including a transistor 100, wherein the transistor 100 includes a first gate 110, a semiconductor layer 120, and a second gate 130. The first gate 110 includes a columnar structure, and the first gate 110 extends along a first direction, that is, the first direction is the axial direction of the first gate 110. It should be noted that if the transistor 100 is arranged in a vertical direction, the first direction is the vertical direction, that is, the first direction is the vertical direction. Figure 1 If the transistor 100 is arranged in the horizontal direction, the first direction is the Z direction. Figure 1 The X direction or Y direction in .

[0052] The semiconductor layer 120 covers at least a portion of the outer circumference of the first gate 110, that is, the semiconductor layer covers a portion of the outer circumference of the first gate 110, and can also cover the entire outer circumference of the first gate 110. In this way, the transistor formed by the first gate 110 and the semiconductor layer 120 can be a gate-channel all-around transistor (GCAA for short).

[0053] The second gate 130 is a ring structure, and the second gate 130 covers at least part of the outer circumference of the semiconductor layer 120; when the second gate 130 covers part of the outer circumference of the semiconductor layer 120, the transistor defined by the second gate 130 and the semiconductor layer 120 is a half-ring gate structure; when the second gate 130 covers the entire outer circumference of the semiconductor layer 120, the transistor defined by the second gate 130 and the semiconductor layer 120 is a full-surround gate transistor (Gate-All-Around, referred to as GAA).

[0054] The region corresponding to the semiconductor layer 120 and the second gate 130 is the channel region. In other words, the projection region of the second gate 130 on the semiconductor layer 120 is the channel region. The regions on both sides of the channel region in the semiconductor layer 120 are the source region and the drain region.

[0055] A gate dielectric layer is disposed between the first gate 110 and the semiconductor layer 120 and between the second gate 130 and the semiconductor layer 120. One gate dielectric layer is used to separate the first gate 110 from the semiconductor layer 120, and the other gate dielectric layer is used to separate the second gate 130 from the semiconductor layer 120.

[0056] The material of the gate dielectric layer can be a conventional insulating material. For example, the material of the gate dielectric layer includes silicon dioxide (SiO 2 ), silicon nitride (SiN) and graphene. The material of the gate dielectric layer may also have a higher dielectric constant. For example, the material of the gate dielectric layer includes hafnium silicon oxide (HfSiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 )、Hafnium oxynitride (HfON), Zirconium oxide (ZrO 2 ), Tantalum Oxide (Ta 2 O 5 ), titanium oxide (TiO 2 ) or strontium titanium oxide (SrTiO 3 Such a configuration can effectively prevent electrons from directly tunneling through the gate dielectric layer to generate gate leakage current, which is conducive to reducing the thickness of the gate dielectric layer, meeting the requirements of process size reduction, and providing a guarantee for the development of semiconductor structures or storage units towards integration.

[0057] In a direction perpendicular to the first direction, that is, perpendicular to the axis direction of the first gate 110, the first gate 110 and the second gate 130 are respectively located on both sides of the semiconductor layer 120. When voltages are applied to the first gate 110 and the second gate 130, an inversion layer of a certain thickness is formed on the side of the semiconductor layer 120 close to the first gate 110, and an inversion layer of a certain thickness is formed on the side of the semiconductor layer 120 close to the second gate 130. In this way, the thickness of the inversion layer can be increased, and even the thickness of the inversion layer is the thickness of the entire semiconductor layer 120, thereby improving the control capabilities of the first gate 110 and the second gate 130 on the channel region and reducing the power consumption of the semiconductor structure.

[0058] In addition, the semiconductor layer 120 can be a metal oxide semiconductor layer. In the first aspect, the carrier mobility in the metal oxide semiconductor layer is high, which can greatly improve the sensitivity of the transistor and reduce the power consumption of the memory cell. When the transistor is in the on state, an inversion layer with a high carrier mobility can be formed in the channel region of the semiconductor layer 120, which improves the switching speed of the transistor, thereby improving the read and write operation rate of the memory cell. In the second aspect, the saturation current of the transistor using the metal oxide semiconductor layer is large, so the volume of the transistor can be reduced, thereby reducing the volume of the memory cell and improving the integration of the memory. In the third aspect, the cut-off current of the transistor using the metal oxide semiconductor layer is small. When the transistor is in the off state, the carrier loss rate in the capacitor is slow. Therefore, the stability of the memory cell is good, and when the carrier loss rate in the capacitor is slow, the time interval between two refreshes of the memory cell can be extended, thereby reducing the power consumption of the memory cell. In the fourth aspect, the switching current of the transistor using the metal oxide semiconductor layer is relatively large, and the current change from the off state to the on state is fast, which can improve the switching speed of the transistor and improve the read and write operation efficiency of the memory cell. In summary, in the embodiments of the present disclosure, when the channel layer includes a metal oxide semiconductor layer, the electrical performance of the transistor can be improved, thereby improving the storage performance of the memory cell, and improving the storage performance and integration of the memory.

[0059] In this example, the material of the semiconductor layer 120 may include at least one of indium gallium zinc oxide (InGaZnO, IGZO for short), indium tin oxide (ITO), indium tungsten oxide (InWO), indium zinc oxide (InZnO), gallium oxide (GaOx), and indium oxide (InOx). In one example, the material of the semiconductor layer 120 is indium gallium zinc oxide (IGZO). In indium gallium zinc oxide, indium and zinc elements can improve the mobility of carriers in the semiconductor layer 120, and gallium elements can also adjust other parameters of the transistor, such as adjusting the threshold voltage of the transistor, so that the transistor obtains better comprehensive performance.

[0060] In some possible examples, along the first direction, the first gate 110 includes a first end surface 111 and a second end surface 112 that are oppositely disposed; when the first gate 110 is disposed vertically, the first end surface 111 may be one of the upper surface and the lower surface of the first gate 110, and the second end surface 112 may be the other of the upper surface and the lower surface of the first gate 110. As an example, the first end surface 111 may be the lower surface of the first gate 110, and the second end surface 112 may be the upper surface of the first gate 110.

[0061] The semiconductor layer 120 also covers the first end surface of the first gate 110 , which can increase the contact area between the semiconductor layer 120 and the first gate 110 and improve the bearing capacity of the semiconductor layer 120 .

[0062] It should be noted that the semiconductor structure further includes a substrate 200, and the first gate 110, the semiconductor layer 120 and the second gate 130 are all arranged on the substrate 200, so that the substrate 200 can be used to provide support for the above structure. Among them, the first end face 111 is located between the substrate 200 and the second end face 112. In this embodiment, the substrate 200 can be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (GeSi) substrate, a silicon carbide (SiC) substrate, a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate, etc.

[0063] The semiconductor structure further includes a first contact structure 300 and a second contact structure 400. In the first direction, the first contact structure 300 and the second contact structure 400 are respectively located on both sides of the second gate 130 and are insulated from the second gate 130 and the first gate 110. The first contact structure 300 may be located above the second gate 130 or below the second gate 130.

[0064] Exemplarily, a dielectric layer 500 is disposed between the first contact structure 300 and the second gate 130 , and between the second contact structure 400 and the second gate 130 , wherein the material of the dielectric layer 500 includes silicon oxide, but is not limited thereto.

[0065] One of the first contact structure 300 and the second contact structure 400 is connected to the source region, and the other is connected to the drain region. In one example, when the first contact structure 300 is connected to the source region, the second contact structure 400 is connected to the drain region accordingly. When the first contact structure 300 is connected to the drain region, the second contact structure 400 is connected to the source region accordingly.

[0066] The first contact structure 300 and the second contact structure 400 are used to apply a signal to the transistor 100. It should be noted that, in this embodiment, the transistor 100 can be used as a part of a memory cell. When the memory cell is a 1T1C structure, one of the first contact structure 300 and the second contact structure 400 is used for bit line connection, and the other of the first contact structure 300 and the second contact structure 400 is used for connection with a capacitor. When the memory cell is a 2T0C structure and the transistor is used as a write transistor, one of the first contact structure 300 and the second contact structure 400 is used for bit line connection, and the other of the first contact structure 300 and the second contact structure 400 is used for connection with the gate of the read-in transistor.

[0067] In this embodiment, the material of the first contact structure 300 and the material of the second contact structure 400 are indium gallium zinc oxide (IGZO), which can increase the signal transmission speed between the first contact structure 300 and the transistor 100, and between the second contact structure 400 and the transistor 100, thereby improving the performance of the semiconductor structure.

[0068] In some possible examples, the semiconductor layer 120 includes a main body portion 121 , a first extension portion 122 , and a second extension portion 123 . The first extension portion 122 and the second extension portion 123 are respectively located on two sides of the main body portion 121 and are both connected to the main body portion 121 .

[0069] The main body 121 may include a hollow cylindrical structure with upper and lower openings, and at least a portion of the first gate 110 is disposed in the main body 121, so that the main body 121 covers at least a portion of the outer circumference of the first gate 110. In other words, the top surface of the first gate 110 may be substantially flush with the top surface of the main body 121, or may be higher than the top surface of the main body 121.

[0070] The second gate 130 covers at least part of the outer circumference of the main body 121; the projection area of ​​the second gate 130 on the main body 121 is the channel area; that is, the area corresponding to the main body 121 and the second gate 130 is the channel area. Figure 1 The area of ​​the middle body portion 121 within the dotted line frame is referred to as the channel region.

[0071] The first extension portion 122 is disposed at the end of the main body 121 close to the substrate 200 and covers the first end surface 111 of the first gate 110, and the second extension portion 123 is disposed at the end of the main body 121 away from the substrate 200. The area of ​​the main body 121 connected to the first extension portion 122 and the first extension portion 122 constitute one of the source region and the drain region, and the area of ​​the main body 121 connected to the second extension portion 123 and the second extension portion 123 constitute the other of the source region and the drain region.

[0072] The second gate 130 includes a first surface 131 and a second surface 132 opposite to each other along a first direction, and the first surface 131 corresponds to the first end surface 111. For example, if the first end surface 111 is the surface of the first gate 110 close to the substrate 200, the first surface 131 is the surface of the second gate 130 close to the substrate 200.

[0073] The second extension portion 123 is located on one side of the second surface 132 of the second gate 130 , or is located on one side of the first surface 131 and the second surface 132 , respectively, and is connected to the first contact structure 300 or the second contact structure 400 .

[0074] For an example, see the attached Figure 1 The second extension portion 123 is located on one side of the second surface 132 of the second gate 130 , that is, the second extension portion 123 is connected to the end of the main body portion 121 facing away from the substrate 200 .

[0075] The second extension portion 123 covers the surface of the first contact structure 300 or the second contact structure 400 located on the second surface 132 that is away from the second gate 130; it should be understood that when the first contact structure 300 is located above the second surface 132 of the second gate 130, the second extension portion 123 covers the surface of the first contact structure 300 that is away from the second gate 130. When the second contact structure 400 is located above the second surface 132 of the second gate 130, the second extension portion 123 covers the surface of the second contact structure 400 that is away from the second gate 130.

[0076] The surface of the second extension portion 123 away from the second gate 130 is lower than the second end face 112. In this way, a gate dielectric layer can be set between the surface of the second extension portion 123 away from the second gate 130 and the second end face 112 to prevent the first gate 110 from being in contact and electrically connected with the second extension portion 123, thereby improving the yield of the transistor.

[0077] For another example, see the attached Figure 2 The second extension portion 123 is respectively located on one side of the first surface 131 and the second surface 132 of the second gate 130 , and is respectively connected to the first contact structure 300 and the second contact structure 400 .

[0078] There are two second extensions 123, and the two second extensions 123 are respectively located on both sides of the second gate 130. For example, one of the second extensions 123 is disposed on the first surface 131 of the second gate 130 and covers a portion of the surface of the first contact structure 300 or the second contact structure 400 facing the second gate 130. The second extension 123 is connected to the first extension 122 and covers the entire surface of the first contact structure 300 or the second contact structure 400 facing the second gate 130. Such an arrangement can increase the contact area between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400, thereby reducing the contact resistance between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400, thereby improving the performance of the semiconductor structure.

[0079] Another second extension portion 123 is arranged on the second surface 132 of the second gate 130 and covers the surface of the first contact structure 300 or the second contact structure 400 located on the second surface 132 that is away from the second gate 130; such a configuration can increase the contact area between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400, thereby reducing the contact resistance between the source region or the drain region of the semiconductor layer 120 and the first contact structure 300 or the second contact structure 400, thereby improving the performance of the semiconductor structure.

[0080] Please continue to refer to the attached Figure 1 In order to facilitate the description of the positional relationship between the gate dielectric layer and the semiconductor layer 120 , the gate dielectric layer may be further refined. Exemplarily, the gate dielectric layer includes a first gate dielectric layer 141 and a second gate dielectric layer 142 .

[0081] The first gate dielectric layer 141 is located between the semiconductor layer 120 and the first gate 110, and covers the outer peripheral surface and the first end surface 111 of the first gate 110; in other words, the shape of the first gate dielectric layer 141 matches the shape of the semiconductor layer 120, that is, the first gate dielectric layer 141 covers the semiconductor layer 120, or the first gate dielectric layer 141 may also include a main body, a first extension portion and a second extension portion, wherein the main body of the first gate dielectric layer 141 corresponds to the main body 121 of the semiconductor layer 120, the first extension portion of the first gate dielectric layer 141 corresponds to the first extension portion 122 of the semiconductor layer 120, and the second extension portion of the first gate dielectric layer 141 corresponds to the second extension portion 123 of the semiconductor layer 120.

[0082] The second gate dielectric layer 142 is located between the semiconductor layer 120 and the second gate 130 , and covers a portion of the outer peripheral surface of the semiconductor layer 120 , that is, the second gate dielectric layer 142 covers the outer peripheral surface of the main body 121 of the semiconductor layer 120 .

[0083] Please refer to the attached Figure 3 The present disclosure also provides a method for preparing a semiconductor structure, comprising the following steps:

[0084] Step S100: forming a stacked structure, the stacked structure comprising a first material layer, a first conductive material layer and a second material layer stacked in sequence; the first material layer and the second material layer are both insulated from the first conductive material layer.

[0085] It should be noted that the laminated structure 600 in this step can be disposed on the substrate 200 , and the substrate 200 provides support for the laminated structure.

[0086] For example, please refer to the attached Figure 4A deposition process can be used to sequentially form a first material layer 610 , a dielectric material layer 620 , a first conductive material layer 630 , a dielectric material layer 620 and a second material layer 640 which are stacked in sequence on the substrate 200 , wherein the first material layer 610 is disposed on the substrate 200 .

[0087] The material of the first material layer 610 and the material of the second material layer 640 are the same, both comprising indium gallium zinc oxide (IGZO). The material of the first conductive material layer 630 may comprise a metal material, for example, metal tungsten.

[0088] At a preset temperature, the substrate 200 and the stacked structure 600 are subjected to rapid thermal annealing. At 350°C-450°C, for example, at 400°C, the substrate 200 and the stacked structure 600 are subjected to rapid thermal annealing to refine the grains of each film layer in the stacked structure 600 and improve the density of each film layer in the stacked structure 600. In this embodiment, the stacked structure 600 can be subjected to rapid thermal annealing for about one minute to avoid excessive oxidation of the stacked structure 600 and the substrate 200, thereby improving the performance of the formed semiconductor structure.

[0089] Step S200: remove part of the first conductive material layer and the second material layer to form a groove in the stacked structure, wherein the groove exposes the first material layer; wherein the retained first conductive material layer constitutes a second gate, and one of the first material layer and the retained second material layer forms a first contact structure, and the other forms a second contact structure.

[0090] For example, please refer to the attached Figure 5 , a portion of the second material layer 640, the dielectric material layer 620, the first conductive material layer 630, and the dielectric material layer 620 located below the first conductive material layer 630 are removed by a patterning process to form a groove 650 in the stacked structure 600, wherein the groove 650 exposes the first material layer 610. The bottom of the groove 650 is located on the top surface of the first material layer 610, and may also be inside the first material layer 610.

[0091] Among them, the retained first conductive material layer 630 constitutes the second gate 130, one of the first material layer 610 and the retained second material layer 640 forms the first contact structure 300, and the other forms the second contact structure 400; the retained dielectric material layer 620 respectively constitutes two dielectric layers 500, one of which is arranged between the second gate 130 and the first contact structure 300, and the other dielectric layer 500 is arranged between the second gate 130 and the second contact structure 400.

[0092] Step S300: forming a semiconductor layer, a gate dielectric layer and a first gate in the groove; wherein the semiconductor layer covers at least a portion of the outer peripheral surface of the first gate, and the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer, and the area opposite to the semiconductor layer and the second gate is a channel region, the areas on both sides of the channel region are the source region and the drain region, respectively, and the gate dielectric layer is respectively located between the first gate and the second gate and the semiconductor layer; one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

[0093] In this embodiment, the gate dielectric layer includes a first gate dielectric layer 141 and a second gate dielectric layer 142. The first gate dielectric layer 141 is located between the second gate electrode 130 and the semiconductor layer 120 (see the attached Figure 1 ), the second gate dielectric layer 142 is located between the semiconductor layer 120 and the first gate 110 (please refer to the attached Figure 1 )between.

[0094] Please refer to the attached Figure 6 and attached Figure 7 , a first gate dielectric layer 141 is formed on the sidewall of the trench 650. Exemplarily, a gate dielectric material layer 411 is formed on the inner wall of the trench 650 by an atomic layer deposition process, and the gate dielectric material layer 411 also covers the top surface of the first contact structure 300 or the second contact structure 400. In one example, the gate dielectric material layer 411 covers the top surface of the first contact structure 300.

[0095] Afterwards, an etching process is used to remove the top surface of the first contact structure 300 or the second contact structure 400 and the gate dielectric material layer 411 on the bottom wall of the trench 650 , and the gate dielectric material layer 411 on the side wall of the trench 650 is retained to form the first gate dielectric layer 141 .

[0096] Afterwards, please refer to the attached Figure 8 , a semiconductor layer 120 is formed by an atomic layer deposition process, wherein the semiconductor layer covers the uncovered bottom wall of the trench 650, the first gate dielectric layer 141, and the first contact structure 300 or the second contact structure 400 located above the second gate 130. That is, when the first contact structure 300 is located above the second gate 130, the semiconductor layer 120 covers the first contact structure 300 accordingly; when the second contact structure 400 is located above the second gate 130, the semiconductor layer 120 covers the second contact structure 400 accordingly.

[0097] Among them, the semiconductor layer 120 located on the first gate dielectric layer 141 constitutes the main body 121, the semiconductor layer 120 located on the bottom wall of the groove 650 constitutes the first extension portion 122, and the semiconductor layer 120 located on the first contact structure 300 or the second contact structure 400 above the second gate 130 constitutes the second extension portion 123.

[0098] The area of ​​the main body 121 corresponding to the second gate 130 is the channel area, that is, the projection area of ​​the second gate 130 on the semiconductor layer 120 is the channel area. Figure 8 The area of ​​the main body 121 located in the dotted box is the channel area, and the areas on both sides of the channel area are the source area and the drain area. In one example, the source area can be composed of the second extension part 123 and the part of the main body 121 connected to the second extension part 123, and the drain area can be composed of the first extension part 122 and the part of the main body 121 connected to the first extension part 122.

[0099] Afterwards, please refer to the attached Fig. 9 , a second gate dielectric layer 142 is formed by an atomic layer deposition process, and the second gate dielectric layer 142 covers the semiconductor layer 120 , that is, the second gate dielectric layer 142 conformally covers the semiconductor layer 120 .

[0100] Afterwards, please refer to the attached Fig.10 , forming a second conductive material layer 113, the second conductive material layer 113 covers the area surrounded by the second gate dielectric layer 142, and fills the area surrounded by the second gate dielectric layer 142.

[0101] Please continue to refer to the attached Figure 1 , remove part of the second conductive material layer 113, for example, by using an etching process or a chemical mechanical polishing process, remove the second conductive material layer 113 located on the top surface of the second gate dielectric layer 142, and the second conductive material layer 113 remaining in the area surrounded by the second gate dielectric layer 142 constitutes the first gate 110. The top surface of the first gate 110 is flush with the top surface of the second gate dielectric layer 142.

[0102] The semiconductor structure formed by the preparation method provided in the embodiment of the present disclosure has a dual gate, that is, it has a first gate 110 and a second gate 130 at the same time, and the first gate 110 and the second gate 130 are respectively located on both sides of the semiconductor layer 120. When voltages are applied to the first gate 110 and the second gate 130, an inversion layer of a certain thickness is formed on the side of the semiconductor layer 120 close to the first gate 110, and an inversion layer of a certain thickness is formed on the side of the semiconductor layer 120 close to the second gate 130. In this way, the thickness of the inversion layer can be increased, the control capability of the first gate 110 and the second gate 130 over the channel region can be improved, and the power consumption can be reduced.

[0103] It should be noted that when there are two second extension portions 123, which need to cover both the first contact structure 300 and the second contact structure 400, the structure thereof can refer to the attached Figure 2 At this time, when depositing the stacked structure 600, it is necessary to deposit a semiconductor material layer of a certain thickness between the first material layer 610 and the dielectric material layer 620, and then form a semiconductor structure according to the above-mentioned preparation method.

[0104] The disclosed embodiments further disclose a memory, which may include a plurality of repeated memory cells, wherein each memory cell includes at least one semiconductor structure described in any of the above embodiments.

[0105] It should be understood that the storage unit of the memory in the embodiment of the present disclosure may include a transistor and a capacitor (1T1C structure), and the transistor is a semiconductor structure described in any of the above embodiments.

[0106] The storage unit of the memory may further include two transistors (2T0C), at least one of the two transistors adopts the semiconductor structure described in any of the above embodiments.

[0107] Since the memory includes the semiconductor structure described in any of the above embodiments, the memory has the beneficial effects of the semiconductor structure described in any of the above embodiments, and this embodiment will not be described in detail herein.

[0108] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0109] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0110] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that: A transistor is included, the transistor comprising: A first columnar gate extending along a first direction; A semiconductor layer, wherein the semiconductor layer covers at least a portion of an outer peripheral surface of the first gate; A second annular gate, wherein the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer; the projection area of ​​the second gate on the semiconductor layer is a channel region; wherein the regions on both sides of the channel region in the semiconductor layer are a source region and a drain region, respectively; a gate dielectric layer is provided between the first gate and the semiconductor layer, and between the second gate and the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: Along the first direction, the first gate includes a first end surface and a second end surface that are oppositely disposed; the semiconductor layer also covers the first end surface of the first gate; The semiconductor structure also includes a first contact structure and a second contact structure. Along the first direction, the first contact structure and the second contact structure are respectively located on both sides of the second gate and are insulated from the second gate and the first gate; wherein one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

3. The semiconductor structure according to claim 2, characterized in that: The semiconductor layer includes a main body, a first extension and a second extension, wherein the first extension and the second extension are both connected to the main body; the main body covers at least a portion of the outer circumference of the first gate, and the second gate covers at least a portion of the outer circumference of the main body; and the projection area of ​​the second gate on the main body is a channel area; The first extension portion covers the first end surface of the first gate; The second gate includes a first surface and a second surface opposite to each other along the first direction, and the first surface corresponds to the first end surface; wherein the second extension portion is located on one side of the second surface of the second gate, or, is located on one side of the first surface and the second surface respectively, and is connected to the first contact structure or the second contact structure.

4. The semiconductor structure according to claim 3, characterized in that: The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; The first gate dielectric layer is located between the semiconductor layer and the first gate and at least covers the outer peripheral surface of the first gate; The second gate dielectric layer is located between the semiconductor layer and the second gate and covers the main body of the semiconductor layer; A dielectric layer is disposed between the first contact structure and the second gate, and between the second contact structure and the second gate.

5. The semiconductor structure according to claim 4, characterized in that: The materials of the semiconductor layer, the first contact structure and the second contact structure all include indium gallium zinc oxide.

6. A method for preparing a semiconductor structure, characterized in that: The steps include: forming a stacked structure, wherein the stacked structure comprises a first material layer, a first conductive material layer, and a second material layer stacked in sequence; the first material layer and the second material layer are both insulated from the first conductive material layer; Removing a portion of the first conductive material layer and a portion of the second material layer to form a groove in the stacked structure, wherein the groove exposes a portion of the first material layer; wherein the retained first conductive material layer constitutes a second gate, and one of the first material layer and the retained second material layer forms a first contact structure, and the other forms a second contact structure; A semiconductor layer, a gate dielectric layer and a first gate are formed in the groove; wherein the semiconductor layer covers at least a portion of the outer peripheral surface of the first gate, and the second gate covers at least a portion of the outer peripheral surface of the semiconductor layer, and the region opposite to the semiconductor layer and the second gate is a channel region, the regions located on both sides of the channel region are source regions and drain regions, respectively, and the gate dielectric layer is respectively located between the first gate and the second gate and the semiconductor layer; one of the first contact structure and the second contact structure is connected to the source region, and the other is connected to the drain region.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer; The step of forming the semiconductor layer and the gate dielectric layer in the trench comprises: forming a first gate dielectric layer on the sidewalls of the trench; forming a semiconductor layer, wherein the semiconductor layer covers the uncovered bottom wall of the trench, the first gate dielectric layer, and the first contact structure or the second contact structure located above the second gate; wherein the semiconductor layer located on the first gate dielectric layer constitutes a main body, the semiconductor layer located on the bottom wall of the trench constitutes a first extension, and the semiconductor layer located on the first contact structure or the second contact structure located above the second gate constitutes a second extension; A second gate dielectric layer is formed, wherein the second gate dielectric layer covers the semiconductor layer.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that: The step of forming the first gate includes: forming a second conductive material layer, wherein the second conductive material layer covers the area surrounded by the second gate dielectric layer and fills the area surrounded by the second gate dielectric layer; A portion of the second conductive material layer is removed, and the second conductive material layer remaining in the area surrounded by the second gate dielectric layer constitutes the first gate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that: After the step of forming the stacked structure and before the step of removing a portion of the first conductive material layer and the second material layer, the method further includes: The stacked structure is subjected to rapid thermal annealing at a preset temperature.

10. A memory, characterized in that: A semiconductor structure comprising any one of claims 1 to 5.

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