Semiconductor structure and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a semiconductor structure and a preparation method thereof, a memory and electronic equipment. The semiconductor structure comprises a substrate, a source electrode, a drain electrode, a semiconductor layer, a ferroelectric gate dielectric layer and a grid electrode, the source electrode and the drain electrode are respectively in contact with the semiconductor layer, and the work functions of the source electrode and the drain electrode are intermediate forbidden band work functions; the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer, and the ferroelectric gate dielectric layer comprises a ferroelectric material. According to the invention, the source electrode and the channel are Schottky junctions, and the channel and the drain electrode are Schottky junctions, and formed electron barriers and hole barriers are basically equal. The bipolar current characteristic of the Schottky source-drain field effect transistor is utilized, the polarization characteristic of the ferroelectric gate medium is combined, bipolar channel conductance controlled by gate voltage and ferroelectric polarization intensity at the same time is obtained, the complete function of the ternary content addressable memory can be achieved, and the ternary content addressable memory is simple in structure and low in cost. The three-state content addressable memory is more compact in structure and simple to operate.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and more specifically, to a semiconductor structure and a method for preparing the same, a memory, and an electronic device. Background Art

[0002] Ternary Content Addressable Memory (TCAM) can classify and forward data with high parallel search efficiency and low latency of less than nanoseconds. It has attracted much attention in fields such as network routers, pattern matching, cache controllers and various other artificial intelligence applications.

[0003] Traditional SRAM (static random access memory)-based TCAM memory cells are usually composed of 16 transistors. The TCAM memory cell area is very large and the cost of TCAM products is very high. Summary of the invention

[0004] The present application provides a semiconductor structure and a manufacturing method thereof, a memory, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor structure, including:

[0006] substrate;

[0007] A source electrode, a drain electrode, a semiconductor layer, a ferroelectric gate dielectric layer and a gate electrode located on one side of the substrate;

[0008] The source electrode and the drain electrode are in contact with the semiconductor layer respectively, and the work functions of the source electrode and the drain electrode are both intermediate bandgap work functions;

[0009] The ferroelectric gate dielectric layer is located between the gate and the semiconductor layer, and the ferroelectric gate dielectric layer includes ferroelectric material.

[0010] In a second aspect, an embodiment of the present application provides a memory including the semiconductor structure as described above.

[0011] In a third aspect, an embodiment of the present application provides an electronic device, comprising the memory as described above.

[0012] In a fourth aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0013] Providing a substrate, the substrate comprising an insulating substrate and a semiconductor film layer stacked in sequence;

[0014] A portion of the semiconductor film layer is formed into a source electrode and a first sub-semiconductor layer through a patterning process;

[0015] A gate, a second sub-semiconductor layer, a drain and a ferroelectric gate dielectric layer are sequentially formed on an insulating substrate through a patterning process; wherein: the work functions of the source and the drain are both intermediate bandgap work functions, and the ferroelectric gate dielectric layer includes ferroelectric material.

[0016] The technical solution provided in the embodiments of the present application has at least the following beneficial effects:

[0017] The semiconductor structure provided by the embodiment of the present application is applied to TCAM, and each TCAM storage unit includes only one transistor, and the semiconductor structure of the transistor includes a source, a drain, a semiconductor layer, a ferroelectric gate dielectric layer and a gate located on one side of the substrate, and the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer. The work functions of the source and the drain are both intermediate bandgap work functions, that is, the source and the channel, and the channel and the drain are Schottky junctions, and the electron barrier and the hole barrier formed are substantially equal. The embodiment of the present application utilizes the bipolar current characteristics of the Schottky source-drain field effect transistor, and combines the polarization characteristics of the ferroelectric gate dielectric to obtain a bipolar channel conductance controlled by both the gate voltage and the ferroelectric polarization intensity. Each TCAM storage unit uses only one transistor to realize the complete function of the three-state content addressable memory (TCAM), the area of ​​the TCAM storage unit is reduced, the cost of the TCAM product is reduced, and its structure is simple, which can realize a three-state content addressable memory with a more compact structure and simple operation. Moreover, since the ferroelectric Schottky source-drain field effect transistor has the potential advantage of ultra-steep subthreshold swing (SS), it can operate at a lower voltage, which can further reduce the search energy consumption.

[0018] Additional aspects and advantages of the present application will be partially given in the following description, which will become apparent from the following description, or will be understood through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0020] Figure 1 A circuit schematic diagram and a structural schematic diagram of a semiconductor structure provided in an embodiment of the present application;

[0021] Figure 2 for Figure 1 Schematic diagram of the functional realization principle of the semiconductor structure;

[0022] Figure 3 A schematic diagram of a process for preparing a semiconductor structure provided in an embodiment of the present application;

[0023] Figure 4-Figure 18 A schematic diagram of the structures of different preparation processes in the method for preparing a semiconductor structure provided in an embodiment of the present application. DETAILED DESCRIPTION

[0024] The present application is described in detail below, and examples of embodiments of the present application are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar components or components with the same or similar functions. In addition, if the detailed description of the known technology is unnecessary for the features of the present application shown, it will be omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limiting the present application.

[0025] It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. It should also be understood that terms such as those defined in general dictionaries should be understood to have meanings consistent with those in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0026] It will be understood by those skilled in the art that, unless expressly stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present application refers to the presence of the features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should be understood that when we refer to an element as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0027] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0028] The present application embodiment provides a semiconductor structure, such as Figure 1 As shown, Figure 1 (a) is the circuit schematic diagram of the semiconductor structure. Figure 1 (b) is a schematic diagram of the structure of the semiconductor structure. It can be applied to a ternary content addressable memory (TCAM), which may include a word line driver, a read amplifier, a search buffer, and a plurality of TCAM storage cells distributed in an array (not shown in the figure). Figure 1 As shown in (a), each memory cell includes a transistor. Figure 1 As shown in (b), each transistor adopts Figure 1 (b) Semiconductor structure.

[0029] like Figure 1 As shown in (a), the transistor is a ferroelectric Schottky source-drain field effect transistor. It uses the non-volatile ferroelectric polarization state for storage (entry) and the bipolar current characteristics for search (query) to realize the "XNOR" memory logic operation based on a single vertical ferroelectric Schottky source-drain field effect transistor, where the drain, gate, and source of the transistor serve as the ML end, BL / SL end, and ScL end of the TCAM storage unit, respectively.

[0030] The ML terminal is used to detect whether the search (query) and storage (entry) in the search operation match, and is used to connect to the readout amplifier.

[0031] The BL / SL terminal is used to program or remove the transistor by applying a voltage pulse during a write operation to obtain a corresponding storage (entry) state, and is used to connect to the search buffer.

[0032] The ScL terminal cooperates with the BL to apply a corresponding potential to complete programming or erasing of the transistor during a write operation, and is used to connect to the word line driver.

[0033] In the search operation, the SL terminal applies a voltage V corresponding to the search (query) SL , detect the current I at the ML terminal ML , if I ML If it is lower than the reference threshold, it indicates a match; otherwise, it indicates a mismatch, and the ScL terminal is grounded during the search operation.

[0034] like Figure 2 As shown, from left to right, the I storages "0", "1" and "X" are respectively ML -V SL The pulse changes the ferroelectric polarization state, making the V OFF Move "V OFF0 ” and “V OFF1 ”, representing the storage (entry) by applying different programming voltages “0” and “1”, corresponding to the search voltages “Search-0” and “Search-1” for searching (query) “0” and “1”, and “X” is programmed to the intermediate state “V OFFX During the search process, apply V of "Search-0" and "Search-1" respectively. SLTo search for "0" and "1", for storage (entry) "0" and "1", when the search voltage is equal to the V of the storage state OFF When the transistor is completely off, I ML is the extremely low off-state current of the transistor; when the search voltage and the storage state do not match, the transistor is in the on state, I ML For the storage (entry) "X", when searching for "0" and "1", the transistor is in the subthreshold region state, with a smaller subthreshold current I ML .

[0035] like Figure 1 (b) is shown. The semiconductor structure includes an insulating substrate 101, and a source 106, a drain 115, a semiconductor layer 117, a ferroelectric gate dielectric layer 116 and a gate 109 located on one side of the insulating substrate 101. The source 106 and the drain 115 are in contact with the semiconductor layer 117, respectively, and the work functions of the source 106 and the drain 115 are both intermediate bandgap work functions. The ferroelectric gate dielectric layer 116 is located between the gate 109 and the semiconductor layer 117, and the ferroelectric gate dielectric layer 116 includes a ferroelectric material.

[0036] The semiconductor structure provided by the embodiment of the present application is applied to TCAM, and each TCAM storage unit includes only one transistor, and the semiconductor structure of the transistor includes a source, a drain, a semiconductor layer, a ferroelectric gate dielectric layer and a gate located on one side of the substrate, and the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer. The work functions of the source and the drain are both intermediate bandgap work functions, that is, the source and the channel, and the channel and the drain are Schottky junctions, and the electron barrier and the hole barrier formed are substantially equal. The embodiment of the present application utilizes the bipolar current characteristics of the Schottky source-drain field effect transistor, and combines the polarization characteristics of the ferroelectric gate dielectric to obtain a bipolar channel conductance controlled by both the gate voltage and the ferroelectric polarization intensity. Each TCAM storage unit uses only one transistor to realize the complete function of the three-state content addressable memory (TCAM), the area of ​​the TCAM storage unit is reduced, the cost of the TCAM product is reduced, and its structure is simple, which can realize a three-state content addressable memory with a more compact structure and simple operation. Moreover, since the ferroelectric Schottky source-drain field effect transistor has the potential advantage of ultra-steep subthreshold swing (SS), it can operate at a lower voltage, which can further reduce the search energy consumption.

[0037] In some embodiments, Figure 1As shown in (b), the semiconductor layer 117, the ferroelectric gate dielectric layer 116 and the gate 109 are all located on the side of the source 106 away from the insulating substrate 101; the drain 115 and the source 106 are respectively located on both sides of the semiconductor layer 117 and are connected to the semiconductor layer 117. The ferroelectric gate dielectric layer 116 surrounds part of the side wall of the semiconductor layer 117; and the gate 109 surrounds part of the side wall of the ferroelectric gate dielectric layer 116.

[0038] In some embodiments, Figure 1 As shown in (b), the channel of the semiconductor layer 117 is a vertical channel, and the semiconductor layer 117 and the ferroelectric gate dielectric layer 116 both extend in a direction perpendicular to the insulating substrate 101, that is, Figure 1 The first direction of the extension. Figure 1 In (b), the first direction intersects with the second direction, the first direction is a direction perpendicular to the insulating substrate 101 , and the second direction is a direction parallel to the insulating substrate 101 .

[0039] In this application, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0040] In some embodiments, Figure 1 As shown in (b), the semiconductor layer 117 includes a first sub-semiconductor layer 102b and a second sub-semiconductor layer 114; the first sub-semiconductor layer 102b and the second sub-semiconductor layer 114 are stacked and connected; the first sub-semiconductor layer 102b is located on a side close to the source 106 and connected to the source 106; the second sub-semiconductor layer 114 is located on a side close to the drain 115 and connected to the drain 115; the orthographic projection of the ferroelectric gate dielectric layer 116 on the insulating substrate 101 is located within the orthographic projection of the first sub-semiconductor layer 102b on the insulating substrate 101, and the orthographic projection of the ferroelectric gate dielectric layer 116 on the insulating substrate 101 does not overlap with the orthographic projection of the second sub-semiconductor layer 114 on the insulating substrate 101. The semiconductor structure of this embodiment adopts a vertical epitaxial channel, which can be more compact in space, save area, and facilitate high-density integration and manufacturing. This embodiment can be manufactured using gate-first (making the gate first), FE last (making the ferroelectric gate dielectric layer last), post-epitaxial channel and other processes. There are not too many doping and activation processes in the process, and the process is relatively simple.

[0041] In some embodiments, Figure 1As shown in (b), the ferroelectric gate dielectric layer 116 is located on a side of the first sub-semiconductor layer 102 b away from the insulating substrate 101 , and is connected to both the first sub-semiconductor layer 102 b and the second semiconductor layer 114 ; the ferroelectric gate dielectric layer 116 surrounds the side wall of the second sub-semiconductor layer 114 .

[0042] In some embodiments, Figure 1 As shown in (b), the ferroelectric gate dielectric layer 116 surrounds the drain 115. In some embodiments, the transistor is an n-type transistor, and the semiconductor layer 117 includes silicon, germanium, germanium silicon, etc. When the material of the semiconductor layer 117 includes silicon, the materials of the source and the drain are both metal silicide. When the material of the semiconductor layer 117 includes germanium, the materials of the source and the drain are both metal germanide.

[0043] Based on the same inventive concept, an embodiment of the present application provides a memory, which may be a ternary content addressable memory (TCAM). The ternary content addressable memory includes a word line driver, a read amplifier, a search buffer, and a plurality of memory cells distributed in an array, each memory cell using a semiconductor structure as described above. The source of the semiconductor structure is connected to the word line driver, the drain of the semiconductor structure is connected to the read amplifier, and the gate of the semiconductor structure is connected to the search buffer.

[0044] The memory provided by the embodiment of the present application may have the following beneficial effects:

[0045] In the memory provided by the embodiment of the present application, each TCAM storage unit includes only one transistor, and the semiconductor structure of the transistor includes a source, a drain, a semiconductor layer, a ferroelectric gate dielectric layer and a gate located on one side of the substrate, the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer, and the work functions of the source and the drain are both intermediate bandgap work functions, that is, the source and the channel, and the channel and the drain are Schottky junctions, and the electron potential barrier and the hole potential barrier formed by them are basically equal.

[0046] The embodiment of the present application utilizes the bipolar current characteristics of the Schottky source-drain field effect transistor and combines the polarization characteristics of the ferroelectric gate medium to obtain a bipolar channel conductance that is controlled by both the gate voltage and the ferroelectric polarization strength. Each TCAM storage cell uses only one transistor to realize the complete functions of a three-state content addressable memory (TCAM), the area of ​​the TCAM storage cell is reduced, the cost of the TCAM product is reduced, and the structure is simple, so a three-state content addressable memory with a more compact structure and simple operation can be realized.

[0047] The semiconductor structure of this embodiment adopts a vertical epitaxial channel, which can be more compact in space, save area, and facilitate high-density integration and manufacturing.

[0048] Based on the same inventive concept, an embodiment of the present application provides an electronic device, including a memory provided in any of the above embodiments. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence, a wearable device or a smart mobile terminal.

[0049] The electronic device provided in the embodiment of the present application has the same inventive concept and the same beneficial effects as the previous embodiments. The contents not shown in detail in the electronic device can be referred to the previous embodiments and will not be repeated here.

[0050] Based on the same inventive concept, the present application embodiment provides a method for preparing a semiconductor structure, such as Figure 3 As shown, the method for preparing the semiconductor structure includes:

[0051] S10: providing a substrate, wherein the substrate comprises an insulating substrate and a semiconductor film layer stacked in sequence;

[0052] S11: forming a source electrode and a first sub-semiconductor layer through a patterning process on a portion of the semiconductor film layer;

[0053] S12: forming a gate, a second sub-semiconductor layer, a drain and a ferroelectric gate dielectric layer in sequence on the insulating substrate through a patterning process; wherein: the work functions of the source and the drain are both intermediate bandgap work functions, and the ferroelectric gate dielectric layer includes ferroelectric material.

[0054] The preparation method of the semiconductor structure provided in the embodiment of the present application is relatively simple. By adopting a substrate including an insulating substrate and a semiconductor film layer, a source electrode, a first sub-semiconductor layer, a gate electrode, a second sub-semiconductor layer, a drain electrode and a ferroelectric gate dielectric layer are formed on the substrate, which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

[0055] In some embodiments, a patterning process is performed to form a source electrode and a first sub-semiconductor layer on a portion of the semiconductor film layer, including:

[0056] depositing a first insulating dielectric film layer;

[0057] By patterning, a portion of the first insulating dielectric film layer and a portion of the semiconductor film layer are removed, so that a portion of the semiconductor film layer is used to form a source electrode, and another portion of the semiconductor film layer is used to form a first sub-semiconductor layer;

[0058] Depositing a second insulating dielectric film layer, and forming a sidewall by a self-aligned etching process, wherein the sidewall covers the retained first insulating dielectric film layer and the semiconductor film layer;

[0059] Removing part of the semiconductor film layer by an etching process, so that the orthographic projection of the remaining semiconductor film layer on the insulating substrate overlaps with the orthographic projection of the sidewall on the insulating substrate;

[0060] Depositing a first metal film layer, and performing annealing and wet etching processes so that a portion of the semiconductor film layer is retained to form a source electrode;

[0061] The sidewall spacer and the first insulating dielectric film layer are removed to form a first sub-semiconductor layer.

[0062] In some embodiments, forming the gate includes:

[0063] A third insulating dielectric film layer, a fourth insulating dielectric film layer, a second metal film layer and a fifth insulating dielectric film layer are sequentially formed on a side of the first sub-semiconductor layer away from the insulating substrate, wherein the upper surface of the third insulating dielectric film layer is flush with the upper surface of the first sub-semiconductor layer, and the fourth insulating dielectric film layer covers the first sub-semiconductor layer and the source electrode;

[0064] By patterning, a portion of the fifth insulating dielectric film layer and the second metal film layer is removed, and the orthographic projection of the retained fifth insulating dielectric film layer on the insulating substrate overlaps with the orthographic projection of the second metal film layer on the insulating substrate, and the orthographic projection covers the orthographic projection of the source electrode on the insulating substrate;

[0065] Depositing a sixth insulating dielectric film layer and performing surface planarization, wherein the sixth insulating dielectric film layer covers the retained fifth insulating dielectric film layer;

[0066] A channel groove is formed by an etching process, the channel groove exposes the first sub-semiconductor layer, and the second metal film layer remaining after etching forms a gate.

[0067] In some embodiments, after forming the gate, a second sub-semiconductor layer and a drain are sequentially formed by a patterning process, including:

[0068] A sacrificial gate dielectric layer is formed on the inner sidewall of the trench through a patterning process;

[0069] Growing a semiconductor film layer in the trench, wherein the semiconductor film layer fills the trench and contacts the sacrificial gate dielectric layer;

[0070] A third metal film layer is deposited, and through annealing and wet etching processes, a portion of the semiconductor film layer in the channel groove forms a drain, and another portion of the semiconductor film layer in the channel groove forms a second sub-semiconductor layer.

[0071] In some embodiments, after forming the drain, a ferroelectric gate dielectric layer is formed by a patterning process, including:

[0072] removing the sacrificial gate dielectric layer to form a gate dielectric layer accommodating portion;

[0073] A ferroelectric gate dielectric film layer is deposited in the gate dielectric layer receiving portion to form a ferroelectric gate dielectric layer.

[0074] Combine the following Figure 4-Figure 18 , Figure 1 (b) A detailed description of the preparation process of the semiconductor structure in one embodiment of the present application.

[0075] Specifically, Figure 4 As shown, a substrate 100 is provided, and the substrate 100 includes an insulating substrate 101 and a semiconductor film layer 102 stacked in sequence. The insulating substrate 101 may include a semiconductor film layer (dark gray film layer) and an insulating dielectric film layer (white film layer) stacked in layers. Optionally, an SOI (Silicon-On-Insulator) silicon liner may be used as the substrate 100. The substrate 100 includes an insulating substrate 101 and a semiconductor film layer 102 stacked in layers. The material of the semiconductor film layer 102 may be Si (silicon) material. By using an SOI silicon liner as the substrate, the principle of the SOI silicon liner is to add an insulating material between silicon transistors, which can reduce the parasitic capacitance between the two by half than the original. The advantage is that it is easier to increase the clock frequency and reduce current leakage to become a power-saving IC. In terms of process, some photomasks can be omitted to save costs. Therefore, it has advantages both in process and circuit.

[0076] like Figure 5 As shown, a first insulating dielectric film layer 103 is deposited; the first insulating dielectric film layer 103 can be made of SiO2 (silicon dioxide). Part of the first insulating dielectric film layer 103 and part of the semiconductor film layer 102 are removed by photolithography and etching processes, and the semiconductor film layer 102 forms an inverted T-shaped silicon step structure after etching. The retained first part of the semiconductor film layer 102a is used to form a source electrode, and the retained second part of the semiconductor film layer 102b is used to form a first sub-semiconductor layer. Along the direction perpendicular to the junction substrate 101 (first direction), the first part of the semiconductor film layer 102a and the second part of the semiconductor film layer 102b are stacked in sequence. The first part of the semiconductor film layer 102a is located below the second part of the semiconductor film layer 102b.

[0077] like Figure 6 As shown, a second insulating dielectric film layer 104 is deposited, and a sidewall is formed by a self-aligned etching process, wherein the sidewall covers the retained first insulating dielectric film layer 103 and the semiconductor film layer 102b.

[0078] like Figure 7 As shown, with the sidewall as a hard mask, a portion of the semiconductor film layer 102a is removed through an etching process, so that the orthographic projection of the retained semiconductor film layer 102a on the insulating substrate overlaps with the orthographic projection of the sidewall on the insulating substrate.

[0079] like Figure 8 and Fig. 9As shown, a first metal film layer 105 is deposited, and through annealing and wet etching processes, the semiconductor film layer 102a forms a metal silicide source 106; the electron and hole potential barriers formed by the metal silicide source 106 and the channel are close to half the silicon bandgap width. In one embodiment, the deposited metal can be Ni (nickel), and the annealing temperature is 450°C to 550°C, and the time is 60s (seconds).

[0080] like Fig.10 As shown, the sidewall spacers and the first insulating dielectric film layer 103 are removed to form a first sub-semiconductor layer 102 b.

[0081] like Fig.11 As shown, a third insulating dielectric film layer 107 is deposited, and a CMP (Chemical Mechanical Polishing) process is used to planarize the surface.

[0082] like Fig.12 As shown, the fourth insulating dielectric film layer 108, the second metal film layer 109' and the fifth insulating dielectric film layer 110 are sequentially grown, and the fourth insulating dielectric film layer 108 covers the first sub-semiconductor layer 102b and the source 106. The material of the fourth insulating dielectric film layer 108 and the fifth insulating dielectric film layer 110 can be SiO2 (silicon dioxide). The material of the second metal film layer 109' can be TiN (titanium nitride), and the second metal film layer 109' is used as the gate 109 of the transistor.

[0083] like Fig.13 As shown, a portion of the fifth insulating dielectric film layer 110 and the second metal film layer 109' is removed by photolithography and etching processes, and the orthographic projection of the retained fifth insulating dielectric film layer 110 on the insulating substrate 100 overlaps with the orthographic projection of the second metal film layer 109' on the insulating substrate 100, and the orthographic projection covers the orthographic projection of the source 106 on the insulating substrate 100.

[0084] like Fig.14 As shown, a sixth insulating dielectric film layer 111 is deposited, and a CMP (Chemical Mechanical Polishing) process is used to planarize the surface, and the sixth insulating dielectric film layer 111 covers the retained fifth insulating dielectric film layer 110 .

[0085] like Fig.15 As shown, a channel groove 112 is formed by an etching process, and the channel groove 112 exposes the first sub-semiconductor layer 102 b . The remaining second metal film layer 109 ′ after etching forms a gate 109 .

[0086] like Fig.16As shown, an insulating dielectric film layer is deposited through a patterning process, and a sacrificial gate dielectric layer 113 disposed on the inner sidewall of the trench 112 is formed through a self-aligned etching process; the material of the sacrificial gate dielectric layer 113 is Si3N4 (silicon nitride).

[0087] like Fig.17 As shown, a semiconductor film layer 114 is grown in the channel groove 112, the semiconductor film layer 114 fills the channel groove 112 and contacts the sacrificial gate dielectric layer 113; the material of the semiconductor film layer 114 is silicon. That is, the channel silicon is epitaxially grown. In one embodiment, the channel silicon is approximately an intrinsic channel with a doping concentration of approximately 1×10 15 cm -3 .

[0088] like Fig.18 As shown, a third metal film layer is deposited, and through annealing and wet etching processes, a portion of the semiconductor film layer in the channel groove 112 forms a metal silicide drain 115, and another portion of the semiconductor film layer in the channel groove 112 forms a second sub-semiconductor layer 114. In one embodiment, the deposited metal can be Ni (nickel), and the annealing temperature is 450° C. to 550° C., and the time is 60 seconds (seconds). The electron and hole barriers formed by Ni (nickel) silicide and the intrinsic channel are 0.6 eV (electron volts) and 0.4 eV (electron volts), respectively, which is close to half of the silicon bandgap width.

[0089] like Figure 1 As shown in (b), the sacrificial gate dielectric layer 113 is removed to form a gate dielectric layer accommodating portion, and a ferroelectric gate dielectric film layer is deposited in the gate dielectric layer accommodating portion to form a ferroelectric gate dielectric layer 116. The ferroelectric gate dielectric layer 116 can be HfO2 doped with Zr, HfO2 doped with Al, or other HfO2 doped ferroelectric materials. Excess ferroelectric gate dielectrics are removed by etching, and thus the semiconductor structure of the transistor is formed. Subsequently, an interconnection through hole preparation process is performed to lead out the gate, drain, and source of the transistor (the interconnection through hole is not shown).

[0090] In summary, the semiconductor structure provided in the embodiment of the present application is manufactured by gate-first (making the gate first), FE last (making the ferroelectric gate dielectric layer last), post-epitaxial channel and other processes. There are not many doping and activation processes in the process, and the process is relatively simple.

[0091] By using the embodiments of the present application, at least the following beneficial effects can be achieved:

[0092] 1) The semiconductor structure provided in the embodiment of the present application is applied to TCAM, and each TCAM storage unit includes only one transistor, and the semiconductor structure of the transistor includes a source, a drain, a semiconductor layer, a ferroelectric gate dielectric layer and a gate located on one side of the substrate, and the ferroelectric gate dielectric layer is located between the gate and the semiconductor layer. The work functions of the source and the drain are both intermediate bandgap work functions, that is, the source and the channel, and the channel and the drain are Schottky junctions, and the electron potential barrier and the hole potential barrier formed are substantially equal. The embodiment of the present application utilizes the bipolar current characteristics of the Schottky source-drain field effect transistor, and combines the polarization characteristics of the ferroelectric gate dielectric to obtain a bipolar channel conductance controlled by both the gate voltage and the ferroelectric polarization intensity. Each TCAM storage unit uses only one transistor to realize the complete function of the three-state content addressable memory (TCAM), the area of ​​the TCAM storage unit is reduced, the cost of the TCAM product is reduced, and its structure is simple, which can realize a three-state content addressable memory with a more compact structure and simple operation. Moreover, since the ferroelectric Schottky source-drain field effect transistor has the potential advantage of ultra-steep subthreshold swing (SS), it can operate at a lower voltage, which can further reduce the search energy consumption.

[0093] 2) The preparation method of the semiconductor structure provided in the embodiment of the present application is relatively simple. By adopting a substrate including an insulating substrate and a semiconductor film layer, a source electrode, a first sub-semiconductor layer, a gate electrode, a second sub-semiconductor layer, a drain electrode and a ferroelectric gate dielectric layer are formed on the substrate, which can achieve a more compact space, save area, and facilitate high-density integration and manufacturing.

[0094] 3) The semiconductor structure of this embodiment adopts a vertical epitaxial channel, which can be more compact in space, save area, and facilitate high-density integration and manufacturing.

[0095] 4) The semiconductor structure of this embodiment can be manufactured by gate-first (making the gate first), FE last (making the ferroelectric gate dielectric layer last), post-epitaxial channel and other processes. There are not too many doping and activation processes in the process, and the process is relatively simple.

[0096] Those skilled in the art will appreciate that the various operations, methods, steps, measures, and schemes in the processes discussed in this application may be alternated, altered, combined, or deleted. Further, other steps, measures, and schemes in the various operations, methods, and processes discussed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted. Further, the steps, measures, and schemes in the prior art that are similar to those disclosed in this application may also be alternated, altered, rearranged, decomposed, combined, or deleted.

[0097] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0098] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0099] The above description is only a partial implementation method of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A source electrode, a drain electrode, a semiconductor layer, a ferroelectric gate dielectric layer and a gate electrode located on one side of the substrate; The source electrode and the drain electrode are in contact with the semiconductor layer respectively, and the work functions of the source electrode and the drain electrode are both intermediate bandgap work functions; The ferroelectric gate dielectric layer is located between the gate and the semiconductor layer, and the ferroelectric gate dielectric layer includes ferroelectric material.

2. The semiconductor structure according to claim 1, characterized in that: The semiconductor layer, the ferroelectric gate dielectric layer and the gate are all located on the side of the source electrode away from the substrate; the drain electrode and the source electrode are respectively located on both sides of the semiconductor layer and are connected to the semiconductor layer; The ferroelectric gate dielectric layer surrounds a portion of the sidewall of the semiconductor layer; The gate surrounds a portion of the sidewall of the ferroelectric gate dielectric layer.

3. The semiconductor structure according to claim 2, characterized in that: The semiconductor layer and the ferroelectric gate dielectric layer both extend in a direction perpendicular to the substrate.

4. The semiconductor structure according to claim 3, characterized in that: The semiconductor layer includes a first sub-semiconductor layer and a second sub-semiconductor layer; The first semiconductor sub-layer and the second semiconductor sub-layer are stacked and connected; The first sub-semiconductor layer is located at a side close to the source electrode and connected to the source electrode; The second sub-semiconductor layer is located at a side close to the drain electrode and connected to the drain electrode; The orthographic projection of the ferroelectric gate dielectric layer on the substrate is located within the orthographic projection of the first sub-semiconductor layer on the substrate, and the orthographic projection of the ferroelectric gate dielectric layer on the substrate does not overlap with the orthographic projection of the second sub-semiconductor layer on the substrate.

5. The semiconductor structure according to claim 4, characterized in that: The ferroelectric gate dielectric layer is located on a side of the first sub-semiconductor layer away from the substrate, and is connected to both the first sub-semiconductor layer and the second semiconductor layer; The ferroelectric gate dielectric layer surrounds the side wall of the second sub-semiconductor layer.

6. The semiconductor structure according to claim 5, characterized in that: The ferroelectric gate dielectric layer surrounds the drain; The source is configured to be connected to a word line driver; The drain is configured to be connected to a sense amplifier; The gate is configured to be connected to a search buffer.

7. The semiconductor layer structure according to claim 1, characterized in that: The material of the semiconductor layer includes at least one of silicon and germanium.

8. The semiconductor structure according to claim 7, characterized in that: The material of the source and the drain includes at least one of metal silicide and metal germanide.

9. A memory, characterized in that: Comprising the semiconductor structure according to any one of claims 1 to 8.

10. An electronic device, characterized in that: Comprising the memory as claimed in claim 9.

11. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an insulating substrate and a semiconductor film layer stacked in sequence; A patterning process is used to form a source electrode and a first semiconductor sub-layer on a portion of the semiconductor film layer; A gate, a second sub-semiconductor layer, a drain and a ferroelectric gate dielectric layer are sequentially formed on the insulating substrate through a patterning process; wherein: the work functions of the source and the drain are both intermediate bandgap work functions, and the ferroelectric gate dielectric layer includes ferroelectric material.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The method of forming a source electrode and a first sub-semiconductor layer by a patterning process includes: depositing a first insulating dielectric film layer; By patterning, a portion of the first insulating dielectric film layer and a portion of the semiconductor film layer are removed, so that the retained first portion of the semiconductor film layer is used to form a source electrode, and the retained second portion of the semiconductor film layer is used to form a first sub-semiconductor layer; Depositing a second insulating dielectric film layer, and forming a sidewall by a self-aligned etching process, wherein the sidewall covers the retained first insulating dielectric film layer and the semiconductor film layer; Removing part of the semiconductor film layer by an etching process, so that the orthographic projection of the remaining semiconductor film layer on the insulating substrate overlaps with the orthographic projection of the sidewall on the insulating substrate; Depositing a first metal film layer, and performing annealing and wet etching processes so that a portion of the semiconductor film layer is retained to form a source electrode; The sidewall spacer and the first insulating dielectric film layer are removed to form a first sub-semiconductor layer.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: Forming the gate includes: A third insulating dielectric film layer, a fourth insulating dielectric film layer, a second metal film layer and a fifth insulating dielectric film layer are sequentially formed on a side of the first sub-semiconductor layer away from the insulating substrate, wherein the upper surface of the third insulating dielectric film layer is flush with the upper surface of the first sub-semiconductor layer, and the fourth insulating dielectric film layer covers the first sub-semiconductor layer and the source electrode; By patterning, a portion of the fifth insulating dielectric film layer and the second metal film layer is removed, and the orthographic projection of the retained fifth insulating dielectric film layer on the insulating substrate overlaps with the orthographic projection of the second metal film layer on the insulating substrate, and the orthographic projection covers the orthographic projection of the source electrode on the insulating substrate; Depositing a sixth insulating dielectric film layer and performing surface planarization, wherein the sixth insulating dielectric film layer covers the retained fifth insulating dielectric film layer; A channel is formed by an etching process, wherein the channel exposes the first sub-semiconductor layer, and the second metal film layer remaining after etching forms the gate.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that: After forming the gate, sequentially forming the second sub-semiconductor layer and the drain electrode through a patterning process includes: A sacrificial gate dielectric layer is formed on the inner sidewall of the trench through a patterning process; Growing a semiconductor film layer in the trench, wherein the semiconductor film layer fills the trench and contacts the sacrificial gate dielectric layer; A third metal film layer is deposited, and through annealing and wet etching processes, a portion of the semiconductor film layer in the trench forms a drain, and another portion of the semiconductor film layer in the trench forms a second sub-semiconductor layer.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: After forming the drain electrode, forming a ferroelectric gate dielectric layer by a patterning process comprises: removing the sacrificial gate dielectric layer to form a gate dielectric layer accommodating portion; A ferroelectric gate dielectric film layer is deposited in the gate dielectric layer accommodating portion to form a ferroelectric gate dielectric layer.

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