Transistor structure using multiple two-dimensional channels

Abstract

A transistor structure includes a plurality of groups of heterojunction layers, each group of heterojunction layers generating a two-dimensional electron gas (2DEG) such that the transistor structure has a stack of 2DEG that can be used for conduction between a source and a drain. A terminal is provided near the uppermost 2DEG to control whether the uppermost 2DEG is continuous between the source contact and the source plug. The source plug connects the uppermost 2DEG with the next 2DEG, and the drain plug also connects the uppermost 2DEG with the next 2DEG. Thus, the gate terminal can control the flow of current in the sub-surface 2DEG between the source and drain.

Description

Technical Field

[0001] The present application relates to the field of high electron mobility transistors (or HEMTs), and in particular to a HEMT comprising multiple heterojunctions and multiple two-dimensional electron gas (2DEG) layers. Background Art

[0002] Electronic circuits often include transistors, which act as electronic switches that regulate or control the flow of current in part of the circuit. One type of transistor is a field effect transistor, in which a voltage is applied to a gate terminal to turn the transistor on and off. A semiconductor channel region is disposed between a drain terminal and a source terminal. When the transistor is on, current flows through the semiconductor channel region between the source terminal and the drain terminal. When the transistor is off, less or no current flows through the semiconductor channel region between the source terminal and the drain terminal. A gate terminal is disposed across the semiconductor channel region between the source terminal and the drain terminal. The voltage on the gate terminal creates a field that affects whether the semiconductor channel region conducts current, hence the term "field effect transistor."

[0003] Traditionally, silicon has been used to make transistors. However, wider bandgap semiconductor materials can be used to make transistors that conduct higher power and operate at higher efficiency than silicon transistors. Silicon carbide (SiC), aluminum nitride (AlN), zinc oxide (ZnO), and gallium nitride (GaN) are all examples of wide bandgap semiconductor materials that can be used in power electronics. One way to use such wider bandgap semiconductor materials is to form two layers of different semiconductor materials to form a heterojunction between them.

[0004] The two semiconductor materials can have sufficiently different band gaps so that when brought together, the band gap of the junction just drops below the Fermi level within the channel layer. This means that electrons can flow freely in this region. This region is thinner in depth and forms a plane parallel to the upper surface of the channel region. Therefore, this region is called the "2DEG" region to emphasize its planar form. In addition, due to the high mobility of electrons in this region, this region is also called "two-dimensional electron gas" (or "2DEG"). Therefore, 2DEG is highly conductive. 2DEG can form the channel region of a power semiconductor to allow high current to pass with relatively low resistance.

[0005] 2DEG can be formed in heterostructures of certain semiconductor pairs with different band gaps and energy band alignment. These semiconductor pairs usually include wide band gap materials and narrow band gap materials. The formation of 2DEG depends on the specific properties of the materials, such as lattice constant, electron affinity and energy band offset.

[0006] The subject matter claimed herein is not limited to implementations that solve any disadvantages or that operate only in environments such as those described above.Rather, this background is provided merely to illustrate one exemplary technology area where some embodiments described herein may be practiced. Summary of the invention

[0007] This summary is provided to introduce some concepts in a simplified form that are further described in the following detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0008] Embodiments described herein relate to a transistor structure including a plurality of heterojunction layer groups. For example, a first heterojunction layer group includes a first barrier semiconductor layer and a first channel semiconductor layer, and a first heterojunction formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer. The first heterojunction induces a first two-dimensional electron gas (2DEG) in the first channel semiconductor layer. A second heterojunction layer group includes a second barrier semiconductor layer and a second channel semiconductor layer, and a second heterojunction formed at an interface between the second barrier semiconductor layer and the second channel semiconductor layer. The second heterojunction induces a second 2DEG in the second channel semiconductor layer.

[0009] The source contact is in conductive contact with the first 2DEG at a portion of the first 2DEG. In addition, a conductive source plug extends between the first 2DEG and the second 2DEG so as to connect the first 2DEG to the second 2DEG. The gate terminal is close to the first 2DEG so that the voltage applied to the gate terminal controls whether the first 2DEG is continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact. The transistor structure also has a drain contact and a conductive drain plug extending from the drain contact through the first heterojunction layer group, through the first 2DEG and reaching the second 2DEG. Therefore, when a voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the second 2DEG and the conductive drain plug.

[0010] Thus, a transistor structure can utilize a conductive path in one or more 2DEGs below the most surface level 2DEG, while still allowing gate control just above the most surface level 2DEG. This has the potential to provide a number of technical benefits, depending on how the sub-surface 2DEGs are used. For example, a transistor structure can use multiple 2DEGs to conduct current between the source and drain, thereby significantly reducing the on-resistance. Furthermore, the transistor structure can even perform the function of two or more independently controllable transistors, each sharing a source and drain.

[0011] Additional features and advantages will be set forth in the following description, and in part will be apparent from the description, or may be learned by practicing the teachings herein. The features and advantages of the present invention may be realized and obtained by the instruments and combinations particularly pointed out in the appended claims. The features of the present invention will become more apparent from the following description and the appended claims, or may be learned by practicing the present invention as set forth below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to describe the manner in which the above-recited and other advantages and features can be obtained, a more particular description of the subject matter briefly described above will be rendered by reference to specific embodiments illustrated in the accompanying drawings. Understanding that these drawings depict only typical embodiments and are therefore not to be considered limiting of scope, the embodiments will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0013] Figure 1 A transistor structure is shown which is only a very specific example of the broader aspects described herein and comprises a transistor using two sub-surface 2DEGs for communication between source and drain.

[0014] Figure 2 Shows something like Figure 1 An alternative transistor structure to the transistor structure, except having an additional gate terminal that allows the transistor structure to act as two transistors sharing a common source and a common drain.

[0015] Figure 3 An environment including a transistor structure and a control circuit is shown, which can be used to control Figure 2 transistor structure to operate as a single transistor.

[0016] Figure 4 Shown by Figure 3 Flowchart of a method performed by a control circuit in response to determining that a transistor is to be turned on.

[0017] Figure 5 Shows that it can be used Figure 1 The transistor structure or Figure 2 Example component layer distribution in a transistor structure. DETAILED DESCRIPTION

[0018] Embodiments described herein relate to a transistor structure comprising a plurality of heterojunction layer groups, each heterojunction layer group comprising a respective barrier semiconductor layer and a channel semiconductor layer, with a heterojunction between them. For example, if there are at least two heterojunction layer groups, there will be a "first" heterojunction layer group and a "second" heterojunction layer group. In the following, the terms "first", "second", "third", etc. are used only to identify items and distinguish one of the items from another in the item, without implying any type of item ordering. In addition, the elements of the first heterojunction layer group will also use the modifier "first" to simply indicate that the element is part of the first heterojunction layer group. Similar terms will be used for the second heterojunction layer, and if applicable, for the third heterojunction layer, and so on.

[0019] One heterojunction layer group (referred to herein as the "first" heterojunction layer group) includes a first barrier semiconductor layer and a first channel semiconductor layer. A first heterojunction is formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer. The first heterojunction induces a first two-dimensional electron gas (2DEG) in the first channel semiconductor layer. Another heterojunction layer group (referred to herein as the "second" heterojunction layer group) includes a second barrier semiconductor layer and a second channel semiconductor layer. In addition, a second heterojunction is formed at an interface between the second barrier semiconductor layer and the second channel semiconductor layer. The second heterojunction induces a second 2DEG in the second channel semiconductor layer.

[0020] Although there may be precisely two heterojunction layer groups, the principles described herein extend to any multiple heterojunction layer groups, and therefore to any number of 2DEGs. Thus, the transistor structure uses a heterojunction to induce a stack of 2DEGs, each 2DEG extending parallel to the layers and perpendicular to the plane stacking of each 2DEG extending.

[0021] The source contact is in conductive contact with the first 2DEG at a portion of the first 2DEG. In addition, a conductive source plug extends between the first 2DEG and the second 2DEG to connect the first 2DEG with the second 2DEG (and if there are more heterojunction layer groups, the first 2DEG may be connected to more 2DEGs). The gate terminal is close to the first 2DEG so that the voltage applied to the gate terminal controls whether the first 2DEG is continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact. The transistor structure also has a drain contact and a conductive drain plug extending from the drain contact through the first heterojunction layer group, through the first 2DEG and reaching the second 2DEG (and if there are more heterojunction layer groups, it may reach another 2DEG).

[0022] Therefore, when a voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the second 2DEG, and the conductive drain plug. If there are more than two heterojunction layer groups and more than two 2DEGs, and the conductive source plug and the conductive drain plug each extend to contact an additional 2DEG, and a voltage is applied to the gate terminal, then for each additional 2DEG, an additional current path will be formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the respective 2DEG, and the conductive drain plug.

[0023] Thus, a transistor structure can utilize a conductive path in one or more 2DEGs below the most surface level 2DEG, while still allowing gate control just above the most surface level 2DEG. This has the potential to provide a number of technical benefits, depending on how the sub-surface 2DEGs are used. For example, a transistor structure can use multiple 2DEGs to conduct current between the source and drain, thereby significantly reducing the on-resistance. Furthermore, the transistor structure can even perform as two or more independently controllable transistors, each sharing a source and drain.

[0024] Figure 1 A transistor structure 100 is shown, which is only a very specific example of the broader aspects described herein. The transistor structure 100 includes a plurality of heterojunction layer groups. Figure 1 In the specific example of the present invention, the transistor structure 100 includes three heterojunction layer groups 101, 102 and 103. However, the principles described here are also applicable to transistor structures having any plurality of heterojunction layer groups. Although not shown, the heterojunction layer groups 101, 102 and 103 can be fabricated on other semiconductor layers, such as a silicon substrate and an intermediate strain protection layer.

[0025] Each of the heterojunction layer groups 101, 102, and 103 includes a respective barrier semiconductor layer and a respective channel semiconductor layer, and a heterojunction inducing a respective 2DEG is formed therebetween. Figure 1, the heterojunction layer group 101 includes a barrier semiconductor layer 111 and a channel semiconductor layer 112 having a heterojunction 113 formed at an interface between the barrier semiconductor layer 111 and the channel semiconductor layer 112. The heterojunction 113 induces a 2DEG 114 in the channel semiconductor layer 112. Turning to the next heterojunction layer group, the heterojunction layer group 102 includes a barrier semiconductor layer 121 and a channel semiconductor layer 122 having a heterojunction 123 formed at an interface between the barrier semiconductor layer 121 and the channel semiconductor layer 122. The heterojunction 123 induces a 2DEG 124 in the channel semiconductor layer 122. Continuing to another heterojunction layer group, the heterojunction layer group 103 includes a barrier semiconductor layer 131 and a channel semiconductor layer 132 having a heterojunction 133 formed at an interface between the barrier semiconductor layer 131 and the channel semiconductor layer 132. The heterojunction 133 induces a 2DEG 134 within the channel semiconductor layer 132 .

[0026] Figure 1 Barrier semiconductor layers 111, 121, and 131 and channel semiconductor layers 112, 122, and 132 are shown, each of which is composed of AlGaN and each of which is composed of GaN. This is an appropriate choice of materials because, at least for some choices of the composition of AlN and GaN within the AlGaN barrier layer, GaN and AlGaN will form a heterojunction between them, which will include 2DEG in the GaN channel layer. However, the principles described herein are not limited to what the barrier semiconductor layer and the channel semiconductor layer are composed of, because other semiconductor combinations will also form heterojunctions sufficient to induce 2DEG. By way of example only, each of the barrier semiconductor layers can be AlInGaN or possibly AlInGaN, and each of the channel semiconductor layers can be GaN. As another example, each of the barrier semiconductor layers can be AlGaAs, and each of the channel semiconductor layers can be GaAs. In addition, for either or both of the channel semiconductor layer or the barrier semiconductor layer, one or more or all of the heterojunction layer groups can have a different material than other heterojunction layer groups. The principles described herein will operate at a given set of heterojunction layers as long as a 2DEG is induced by the respective heterojunction.

[0027] The p-doped GaN portion 191 (which is in the SiO2 layer) makes the first 2DEG 114 discontinuous below the p-doped GaN portion 191. The source contact 141 is in conductive contact with the first 2DEG 114 at a portion 143 of the first 2DEG 114. In addition, a conductive source plug 142 extends between the first 2DEG 114 and the second 2DEG 124 to connect the first 2DEG 114 to the second 2DEG 124. Although not required, the conductive source plug 142 extends perpendicular to the plane of the first 2DEG 114 and the second 2DEG 124. Figure 1 In the example of FIG. 1 , there is also a third 2DEG 134 . Therefore, the conductive power plug 142 also extends to the third 2DEG 134 so as to connect the first 2DEG 114 , the second 2DEG 124 , and the third 2DEG 134 .

[0028] The transistor structure 100 also has a drain contact 151 and a conductive drain plug 152 extending from the drain contact 151 through the first heterojunction layer group 101, through the first 2DEG 114 and to the second 2DEG 124. Although not required, the conductive drain plug 152 extends perpendicular to the planes of the first 2DEG 114 and the second 2DEG 124. Figure 1 In the example of FIG. 1 , there is also a third 2DEG 134 . Therefore, the conductive drain plug 152 also extends to the third 2DEG 134 so as to connect the first 2DEG 114 , the second 2DEG 124 , and the third 2DEG 134 .

[0029] The transistor structure 100 also includes a gate terminal 161 proximate to the first 2DEG 114, such that a voltage applied to the gate terminal 161 controls whether the first 2DEG 114 is continuous between the conductive source plug 142 and a portion 143 of the first 2DEG 114 that is in conductive contact with the source contact 141. The p-doped GaN portion 192 causes a discontinuity in the first 2DEG 114 below the gate terminal 161 unless a positive voltage is applied to the gate terminal 161. Thus, the transistor structure 100 shown is an enhancement mode transistor. However, the principles described herein also apply to depletion mode transistors, in which case the p-doped GaN portion 192 would not be present.

[0030] Therefore, when a voltage sufficient to make the first 2DEG 114 continuous between the conductive source plug 142 and the portion 143 of the first 2DEG 114 that is in conductive contact with the source contact 141 is applied to the gate terminal 161, a current path (see arrows 171A, 171B, 171C, and 171D) is formed between the source contact 141 and the drain contact 151 via the first 2DEG 114 (see arrow 171A), the conductive source plug 142 (see arrow 171B), the second 2DEG 124 (see arrow 171C), and the conductive drain plug 152 (see arrow 171D). The current path represented by the combination of arrows 171A, 171B, 171C, and 171D is referred to herein as a current path 171.

[0031] exist Figure 1 In the example of FIG. 1 , there is also a third 2DEG 134, the source plug 142 also extends to the third 2DEG 134, and the drain plug 152 also extends to the third 2DEG 134. Therefore, when a voltage sufficient to make the first 2DEG 114 continuous between the conductive source plug 142 and the portion 143 of the first 2DEG 114 that is in conductive contact with the source contact 141 is applied to the gate terminal 161, another current path (see arrows 172A, 172B, 172C, and 172D) is formed between the source contact 141 and the drain contact 151 via the first 2DEG 114 (see arrow 172A), the conductive source plug 142 (see arrow 172B), the third 2DEG 134 (see arrow 172C), and the conductive drain plug 152 (see arrow 172D). The current path represented by the combination of arrows 172A, 172B, 172C, and 172D is referred to herein as current path 172 .

[0032] This general principle can be extended to additional heterojunction layer groups. If there are more heterojunction layer groups, if the source plug 142 extends further down to the respective 2DEG of each additional heterojunction layer group, and the drain plug 152 extends down to the respective 2DEG of each additional heterojunction layer group, then each additional 2DEG can complete another current path between the source contact 141 and the drain contact 151, which is also controlled by the voltage at the gate terminal 161. By providing multiple parallel paths through respective parallel high electron mobility 2DEGs, the total on-resistance between the source terminal and the drain terminal can be significantly reduced compared to having only one 2DEG between the source terminal and the drain terminal.

[0033] The specific transistor structure 100 may also include other surrounding elements. However, the principles described herein are not limited to what those surrounding elements are. Figure 1In a very specific example of, the surrounding structure includes metallization that allows electrical contact to each of the source contact 141, the drain contact 151, and the gate terminal 161, elements for electrically isolating the transistor structure from the surrounding circuitry, and layers that provide structural, electrical, chemical, and mechanical protection. For example, vias 181A, 181B, and 181C and metallization portions 182A, 182B, and 182C allow voltage and / or signals to be applied between the source contact 141 and the external environment. Vias 183A, 183B, and 183C and metallization portions 184A, 184B, and 184C allow voltage and / or signals to be applied between the drain contact 151 and the external environment. Vias 185 and metallization portions 186 facilitate application of electrical signals to the gate terminal 161. Isolation regions are provided on the left and right sides of the heterojunction layer group to provide electrical isolation from adjacent circuitry. The SiN / SiO2 stack passivates the structure.

[0034] exist Figure 1 In the embodiment, the conductive source plug 142 is farther from the conductive drain plug 152 than the source contact 141. Also, the gate terminal 161 is farther from the conductive drain plug 152 than the source contact 141. However, in an alternative embodiment, the conductive source plug and the gate terminal are on the other side of the source contact 141, each closer to the conductive drain plug 152 than the source contact 141.

[0035] Figure 2 An alternative transistor structure 200 is shown. Figure 2 The transistor structure 200 is similar to Figure 1 A transistor structure 100 in which similar elements share the Figure 1 The same reference numerals as those described in the previous section are used. Figure 1 As shown, a voltage applied to terminal 161 controls whether current flows from source contact 141 to drain contact 151 via first current flow path 171 and second current flow path 172. Thus, gate terminal 161 serves as the gate terminal of one transistor (referred to herein as the "first" transistor).

[0036] In addition, there is a second gate terminal 201 near the first 2DEG 114. The second gate terminal 201 can serve as a gate terminal of a second transistor that shares the source contact 141 and the drain contact 151. The P-doped portion 202 makes the 2DEG 114 discontinuous between the source contact 141 and the drain contact 151 unless an appropriate voltage is applied to the second gate terminal 201. Therefore, the gate terminal 201 serves as a gate terminal of the second transistor that shares the source and drain with the first transistor.

[0037] Thus, transistor structure 200 may represent two independent transistors that share a common source and drain. On the other hand, transistor structure 200 may coordinate control of each of the first transistor and the second transistor so that the first transistor and the second transistor are turned on and off at the same time, thereby acting as a single transistor. In this case, to ensure that the transistors are turned on and off at the same time, the transistor structure may be controlled by a corresponding control circuit. Figure 3 An environment 300 including a transistor structure 301 and a control circuit is shown. For example, the transistor structure 301 may be, for example Figure 2 The transistor structure 200 of FIG. 301 includes two transistors 311 and 312 , each of which shares a common source and drain. The control circuit 310 applies a gate voltage to the gate of each of the transistors 311 and 312 .

[0038] Figure 4 A method 400 is shown that is performed by the control circuit 310 in response to determining that a transistor is to be turned on. Specifically, the control circuit 310 applies a turn-on voltage to one of the gate terminals (action 401), and then applies a turn-on voltage to the other of the gate terminals (action 403) after a certain delay (action 402). The amount of delay and which gate terminal is turned on first will depend on the turn-on response time of each of the gate terminals. The amount of delay can be, for example, a fine-tuned value customized for manufacturing variations between devices, and / or can even be fine-tuned to take into account the temperature or aging of the transistor.

[0039] The turn-off transistor can be similarly used Figure 4 400, except that a turn-off voltage is applied instead of a turn-on voltage. Specifically, the control circuit 310 applies a turn-off voltage to one of the gate terminals (action 401), and then applies a turn-off voltage to the other of the gate terminals (action 403) after a certain delay (action 402). The amount of turn-off delay and which gate terminal is turned off first will depend on the turn-off response time of each of the gate terminals. In addition, the amount of delay for turning on the transistor can be different compared to turning off the transistor. In addition, the turn-off delay can be a fine-tuned value to take into account manufacturing variations between devices, and / or can even be fine-tuned to take into account the temperature or aging of the transistor.

[0040] Figure 5 Shows that it can be used Figure 1 The transistor structure 100 or Figure 2 Example composition layer distribution 500 in transistor structure 200. The topmost layer 501 is a 100 nm thick p-GaN layer doped with p-type atoms at a density of 1e17 atoms per cubic centimeter. This layer 501 may be, for example, Figure 1 The P-doped GaN portion 191 or Figure 2The next layer 502 is an example of a barrier semiconductor layer 111, 20 nm thick, and composed of Al(0.15)GaN (or in other words, 15% GaN and 85% GaN). The next layer 503 is an example of a channel semiconductor layer 112, and is 20 nm thick GaN with an n-type doping concentration of 1e16 atoms per cubic centimeter.

[0041] Thus, layers 502 and 503 constitute a heterojunction layer group, and a 2DEG can be formed just within layer 503. Layers 502 and 503 can be repeated for additional lower heterojunction layer groups. Layer 504 represents a barrier semiconductor layer of 20 nm thick and composed of Al(0.15)GaN. The bottommost layer 505 is a bottommost channel semiconductor layer of 100 nm GaN with an n-type doping concentration of 1e16 atoms per cubic centimeter.

[0042] Therefore, the entire heterojunction layer group can be made very thin, possibly on the order of nanometers. For example, layers 502 and 503 form a heterojunction layer group that is only 40 nm thick. Therefore, many heterojunction layer groups (possibly 10s or hundreds) can be stacked on top of each other, thereby creating 10s or hundreds of stacked 2DEGs, each of which can be a parallel path between the source and drain.

[0043] Thus, the principles described herein provide a unique transistor structure that utilizes a conductive path in one or more 2DEGs below the most surface level 2DEG, while still allowing gate control just above the most surface level 2DEG. This has the potential to provide a number of technical benefits, depending on how the sub-surface 2DEGs are used. For example, a transistor structure can use multiple 2DEGs to conduct current between the source and drain, thereby significantly reducing the on-resistance. Furthermore, the transistor structure can even be implemented as two or more independently controllable transistors, each sharing a source and drain.

[0044] Text support part

[0045] Item 1. A transistor structure comprising: a first heterojunction layer group comprising a first barrier semiconductor layer and a first channel semiconductor layer, and a first heterojunction formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer, the first heterojunction inducing a first two-dimensional electron gas (2DEG) in the first channel semiconductor layer; a second heterojunction layer group comprising a second barrier semiconductor layer and a second channel semiconductor layer, and a second heterojunction formed at an interface between the second barrier semiconductor layer and the second channel semiconductor layer, the second heterojunction inducing a second 2DEG in the second channel semiconductor layer; a source contact in conductive contact with the first 2DEG at a portion of the first 2DEG; and a conductive source plug in contact with the first 2DEG and the second 2DEG. A first 2DEG extending between the heterojunction layers so as to connect the first 2DEG with the second 2DEG; a gate terminal, which is close to the first 2DEG so that a voltage applied to the gate terminal controls whether the first 2DEG is continuous between a conductive source plug and a portion of the first 2DEG that is in conductive contact with the source contact; a drain contact; and a conductive drain plug, which extends from the drain contact through the first heterojunction layer group, through the first 2DEG and to the second 2DEG, wherein when a voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the second 2DEG and the conductive drain plug.

[0046] Item 2. According to the transistor structure of Item 1, the current path is a first current path, and the transistor also includes: a third heterojunction layer group, which includes a third barrier semiconductor layer and a third channel semiconductor layer, and a third heterojunction formed at the interface between the third barrier semiconductor layer and the third channel semiconductor layer, the third heterojunction induces a third 2DEG in the third channel semiconductor layer, a conductive source plug extends between the first 2DEG, the second 2DEG and the third 2DEG so as to connect the first 2DEG, the second 2DEG and the third 2DEG; a conductive drain plug extends from the drain contact through the first 2DEG, through the second 2DEG and to the third 2DEG, wherein when a voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a second current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the third 2DEG and the conductive drain plug.

[0047] Item 3. A transistor structure according to Item 1, wherein the conductive source plug is further away from the conductive drain plug than the source contact, and the gate terminal is also further away from the conductive drain plug than the source contact.

[0048] Item 4. According to the transistor structure of Item 3, the current path is a first current path, the gate terminal is a first gate terminal, and the transistor structure also includes: a second gate terminal, which is close to the first 2DEG and closer to the conductive drain plug than the source contact, so that the voltage applied to the second gate terminal controls whether the first 2DEG is continuous between the source contact and the conductive drain plug that is in conductive contact with the source contact, wherein when a voltage sufficient to make the first 2DEG continuous between the source contact and the conductive drain plug is applied to the second gate terminal, a second current path is formed between the source contact and the drain contact via the first 2DEG and the conductive drain plug.

[0049] Item 5. The transistor structure of Item 4, the first gate terminal being for the first transistor and the second gate terminal being for the second transistor, the second transistor sharing a source contact with the first transistor and sharing a drain contact with the first transistor.

[0050] Item 6. The transistor structure according to Item 4, further comprising: a control circuit configured to apply a first gate voltage to the first gate terminal and a second gate voltage to the second gate terminal so as to simultaneously create a first current path and a second current path, and to simultaneously cut off the first current path and the second current path.

[0051] Item 7. The transistor structure of Item 4, further comprising a control circuit configured to: in response to determining that a transistor of the transistor structure is to be turned on, apply a turn-on voltage to the first gate terminal and then, after a delay, apply a turn-on voltage to the second gate terminal.

[0052] Item 8. The transistor structure of Item 4, further comprising a control circuit configured to: in response to determining that a transistor of the transistor structure is to be turned on, apply a turn-on voltage to the second gate terminal and then, after a delay, apply a turn-on voltage to the first gate terminal.

[0053] Item 9. The transistor structure of Item 1, wherein the first channel semiconductor layer is composed of the same semiconductor material as the second channel semiconductor layer.

[0054] Item 10. The transistor structure according to Item 1, wherein the first barrier semiconductor layer is composed of the same semiconductor material as the second barrier semiconductor layer.

[0055] Item 11. The transistor structure of Item 1, wherein the first channel semiconductor layer is composed of a different semiconductor material than the second channel semiconductor layer.

[0056] Item 12. The transistor structure according to Item 1, wherein the first barrier semiconductor layer is composed of a semiconductor material different from that of the second barrier semiconductor layer.

[0057] Item 13. The transistor structure according to Item 1, wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlGaN layer.

[0058] Item 14. The transistor structure according to Item 1, wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlInGaN layer.

[0059] Item 15. The transistor structure according to Item 1, wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlInN layer.

[0060] Item 16. The transistor structure according to Item 1, wherein the first channel semiconductor layer is a GaAs layer, and the first barrier semiconductor layer is an AlGaAs layer.

[0061] Clause 17. The transistor structure of Clause 1, wherein the first 2DEG and the second 2DEG are parallel.

[0062] Item 18. The transistor structure of Item 1, wherein the conductive drain plug extends perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

[0063] Item 19. The transistor structure of Item 16, wherein the conductive source plug also extends perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

[0064] Item 20. The transistor structure of Item 1, wherein the conductive source plug extends perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

[0065] Although the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the features or actions described above, or the order of the actions described above. Instead, the described features and actions are disclosed as example forms of implementing the claims.

[0066] The present disclosure may be implemented in other specific forms without departing from its essential features. The described embodiments should be considered in all aspects as illustrative rather than restrictive. All changes within the equivalent meaning and range of the claims are included within their scope.

[0067] When introducing elements in the appended claims, the articles "a," "an," "the," and "said" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements.

Claims

1. A transistor structure comprising: a first heterojunction layer group including a first barrier semiconductor layer and a first channel semiconductor layer, and a first heterojunction formed at an interface between the first barrier semiconductor layer and the first channel semiconductor layer, the first heterojunction inducing a first two-dimensional electron gas (2DEG) in the first channel semiconductor layer; a second heterojunction layer group including a second barrier semiconductor layer and a second channel semiconductor layer, and a second heterojunction formed at an interface between the second barrier semiconductor layer and the second channel semiconductor layer, the second heterojunction inducing a second 2DEG in the second channel semiconductor layer; a source contact in conductive contact with the first 2DEG at a portion of the first 2DEG; a conductive power plug extending between the first 2DEG and the second 2DEG so as to connect the first 2DEG with the second 2DEG; a gate terminal proximate to the first 2DEG such that a voltage applied to the gate terminal controls whether the first 2DEG is continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact; Drain contact; as well as A conductive drain plug extends from the drain contact through the first heterojunction layer group, through the first 2DEG and to the second 2DEG, wherein when a voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the second 2DEG and the conductive drain plug.

2. The transistor structure according to claim 1, wherein the current path is a first current path, and the transistor further comprises: a third heterojunction layer group including a third barrier semiconductor layer and a third channel semiconductor layer, and a third heterojunction formed at an interface between the third barrier semiconductor layer and the third channel semiconductor layer, the third heterojunction inducing a third 2DEG in the third channel semiconductor layer, The conductive source plug extends between the first 2DEG, the second 2DEG and the third 2DEG so as to connect the first 2DEG, the second 2DEG and the third 2DEG; The conductive drain plug extends from the drain contact through the first 2DEG, through the second 2DEG and to the third 2DEG, wherein when the voltage sufficient to make the first 2DEG continuous between the conductive source plug and the portion of the first 2DEG that is in conductive contact with the source contact is applied to the gate terminal, a second current path is formed between the source contact and the drain contact via the first 2DEG, the conductive source plug, the third 2DEG and the conductive drain plug.

3. The transistor structure according to claim 1, wherein the conductive source plug is farther from the conductive drain plug than the source contact, and the gate terminal is also farther from the conductive drain plug than the source contact.

4. The transistor structure according to claim 3, wherein the current path is a first current path, the gate terminal is a first gate terminal, and the transistor structure further comprises: a second gate terminal proximate to the first 2DEG and closer to the conductive drain plug than the source contact, such that a voltage applied to the second gate terminal controls whether the first 2DEG is continuous between the source contact and the conductive drain plug in conductive contact with the source contact, When a voltage sufficient to make the first 2DEG continuous between the source contact and the conductive drain plug is applied to the second gate terminal, a second current path is formed between the source contact and the drain contact via the first 2DEG and the conductive drain plug.

5. The transistor structure of claim 4, the first gate terminal being for a first transistor and the second gate terminal being for a second transistor, the second transistor sharing the source contact with the first transistor and sharing the drain contact with the first transistor.

6. The transistor structure according to claim 4, further comprising: A control circuit is configured to apply a first gate voltage to the first gate terminal and a second gate voltage to the second gate terminal so as to simultaneously create the first current path and the second current path and to simultaneously cut off the first current path and the second current path.

7. The transistor structure according to claim 4, further comprising a control circuit, wherein the control circuit is configured to: In response to determining that a transistor of the transistor structure is to be turned on, a turn-on voltage is applied to the first gate terminal, and then after a delay, a turn-on voltage is applied to the second gate terminal.

8. The transistor structure according to claim 4, further comprising a control circuit, wherein the control circuit is configured to: In response to determining that a transistor of the transistor structure is to be turned on, a turn-on voltage is applied to the second gate terminal, and then after a delay, a turn-on voltage is applied to the first gate terminal. 9 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is made of the same semiconductor material as that of the second channel semiconductor layer. 10 . The transistor structure according to claim 1 , wherein the first barrier semiconductor layer is composed of the same semiconductor material as that of the second barrier semiconductor layer. 11 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is composed of a semiconductor material different from that of the second channel semiconductor layer. 12 . The transistor structure according to claim 1 , wherein the first barrier semiconductor layer is composed of a semiconductor material different from that of the second barrier semiconductor layer. 13 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlGaN layer. 14 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlInGaN layer. 15 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is a GaN layer, and the first barrier semiconductor layer is an AlInN layer. 16 . The transistor structure according to claim 1 , wherein the first channel semiconductor layer is a GaAs layer, and the first barrier semiconductor layer is an AlGaAs layer.

17. The transistor structure of claim 1, the first 2DEG and the second 2DEG are parallel. 18 . The transistor structure of claim 1 , the conductive drain plug extending perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

19. The transistor structure of claim 16, wherein the conductive source plug also extends perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

20. The transistor structure of claim 1, the conductive source plug extending perpendicular to a plane of the first 2DEG and a plane of the second 2DEG.

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