Efficient thermal isolation structure for SiC VDMOSFET

Abstract

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses an efficient thermal isolation structure for a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor), which comprises a plurality of parallel MOS cells, and is characterized in that each MOS cell comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; wherein the bottom layers of the plurality of MOS cells are in ohmic connection with drain electrodes, the top layers of the plurality of MOS cells are in ohmic connection with metal source electrodes, and grid electrodes are embedded between the MOS cells and the metal source electrodes; six equidistant rectangular grooves are etched in a substrate layer of a single MOS cell, drain metal is deposited in the rectangular grooves, and the drain metal is in ohmic connection with a drain electrode. According to the invention, the substrate layer is designed to be convex in the middle, the drain metal is embedded in the convex region, and the distance from the top end of the drain metal to the diffusion layer is consistent with the distance from the drain electrodes at the two ends to the diffusion layer, so that the on-resistance between the drain electrode and the source electrode of the MOS semiconductor can be reduced, and meanwhile, heat in the silicon crystal can be diffused to the drain electrode from the drain metal.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and more particularly to a high-efficiency thermal isolation structure for SiC VDMOSFET. Background Art

[0002] SiC VDMOSFET is a vertical metal oxide semiconductor field effect transistor (VDMOSFET) based on silicon carbide (SiC) material. It is a power semiconductor device with high voltage, high frequency and high temperature characteristics, and is usually used in high power applications such as power electronic converters, electric vehicles, photovoltaic inverters, etc. SiC VDMOSFET has some significant advantages over traditional silicon (Si) devices: low on-resistance, high breakdown electric field strength, high temperature performance, and high frequency characteristics.

[0003] Now the patent discloses a semiconductor device with a thermal isolation structure (publication number CN116057692A), the semiconductor device includes a first die assembly, the first die assembly includes a semiconductor substrate and a plurality of active circuit elements at the first surface of the semiconductor substrate, the device also includes a second die assembly, the second die assembly includes a carrier substrate and a redistribution structure on or above the first surface of the carrier substrate. The device further includes a thermal buffer structure between the first and second die assemblies, the thermal buffer structure is coupled to the second surface of the semiconductor substrate and the second surface of the carrier substrate. In the technology disclosed in the patent, the heat generated and accumulated by the flow of charges in the silicon crystal is diffused outward layer by layer; and there is a lack of heat dissipation channels between adjacent cell structures, which makes it easy for the heat between adjacent MOS cells to diffuse each other, which further increases the accumulation and generation of heat. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a high-efficiency thermal isolation structure for SiC VDMOSFET, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a high-efficiency thermal isolation structure for SiCVDMOSFET includes a plurality of mutually parallel MOS cells, wherein the MOS cells include a substrate layer, a diffusion layer, a P-well layer, and an N-well layer;

[0006] Among them, the bottom layers of several MOS cells are ohmically connected to drain electrodes, the top layers of several MOS cells are ohmically connected to metal sources, and gate electrodes are embedded between the MOS cells and the metal sources;

[0007] Six equidistant rectangular grooves are etched inside the substrate layer of a single MOS cell, and drain metal is deposited inside the rectangular grooves, and the drain metal is ohmically connected to the drain electrode;

[0008] The P-well layer includes a heavily doped P-well layer 1, a lightly doped P-well layer 1 and a lightly doped P-well layer 2;

[0009] The N-well layer includes a heavily doped N-well layer 1, a heavily doped N-well layer 2, a lightly doped N-well layer 1 and a lightly doped N-well layer 2.

[0010] Furthermore, the substrate layer of a single MOS cell is prepared by ion implantation with more ions in the middle and less ions on both sides, wherein the cross section of the substrate layer is convex in the middle and concave on both sides.

[0011] Furthermore, a U-groove is etched inside the adjacent heavily-doped P-well layer 1, and a gate-shaped partition is embedded inside the U-groove.

[0012] Furthermore, the gate spacers between adjacent MOS cells are shared, and the gate spacers are made of metal silver and are in ohmic contact with the metal source.

[0013] Furthermore, the N-well layer is in two layers, the heavily doped N-well layer 2 and the lightly doped N-well layer 1 are located in the upper layer, and the heavily doped N-well layer 1 and the lightly doped N-well layer 2 are located in the lower layer.

[0014] Furthermore, the width of the heavily doped N-well layer 2 is three times the width of the lightly doped N-well layer 1, and the width of the lightly doped N-well layer 2 is three times the width of the heavily doped N-well layer 1.

[0015] Furthermore, when the gate is connected to a gate voltage, a charge channel is formed inside the lightly doped P-well layer 2, and the charge channel connects the diffusion layer and the N-well layer.

[0016] Furthermore, the heavily doped N-well layer 1 and the heavily doped N-well layer 2 are doped with high-concentration phosphorus ions by ion implantation; and the lightly doped N-well layer 1 and the lightly doped N-well layer 2 are doped with low-concentration phosphorus ions by ion implantation.

[0017] Furthermore, an oxide insulating layer is deposited on the outer surface of the gate, and the oxide insulating layer isolates the gate from the metal source and the ohmic contact of the MOS cell.

[0018] Furthermore, when a voltage is applied to the gate, a depletion layer of a JFET region is formed in the diffusion layer, and the JFET region is located between two heavily doped P-well layers.

[0019] The beneficial effects of the high-efficiency thermal isolation structure for SiC VDMOSFET of the present invention are:

[0020] 1. The present invention embeds a gate-shaped spacer between adjacent MOS cells, and the gate-shaped spacer is made of metal silver, so that the heat accumulated in the silicon crystal of a single MOS cell can be quickly transferred to the metal source through the gate-shaped spacer and diffused.

[0021] 2. The present invention designs the substrate layer to be convex in the middle, and the drain metal is embedded in the convex area, and the distance from the top of the drain metal to the diffusion layer is consistent with the distance from the drain to the diffusion layer at both ends. In this way, the on-resistance between the drain and the source of the MOS semiconductor can be reduced, and the heat in the silicon crystal can also be diffused from the drain metal to the drain.

[0022] 3. The present invention designs the N-well layer into two layers, each layer having two doping concentration regions, which can effectively suppress the parasitic phenomenon of charges in the N-well layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0024] Figure 1 Schematic diagram of the efficient thermal isolation structure of SiC VDMOSFET;

[0025] Figure 2 for Figure 1 A schematic diagram of a local enlarged detail;

[0026] Figure 3 It is a schematic diagram of the double-cell parallel structure of the present invention.

[0027] In the figure: 1. drain; 2. substrate layer; 3. drain metal; 4. metal source; 5. gate; 6. diffusion layer; 7. gate spacer; 8. heavily doped P well layer 1; 9. heavily doped N well layer 1; 10. heavily doped N well layer 2; 11. lightly doped N well layer 1; 12. lightly doped P well layer 1; 13. lightly doped N well layer 2; 14. lightly doped P well layer 2; 15. oxide insulating layer; 16. charge channel; 17. JFET region. DETAILED DESCRIPTION

[0028] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0029] like Figure 1-3As shown, according to one aspect of the present invention, a high-efficiency thermal isolation structure for SiC VDMOSFET is provided, comprising a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a substrate layer 2, a diffusion layer 6, a P-well layer and an N-well layer. Among them, the bottom layers of the plurality of MOS cells are ohmically connected to a drain 1, the top layers of the plurality of MOS cells are ohmically connected to a metal source 4, a gate 5 is embedded between the MOS cell and the metal source 4, and when the gate 5 is connected to a gate voltage, a charge channel 16 (such as Figure 2 As shown), the charge channel 16 will connect the diffusion layer 6 and the N-well layer, so that a path will be formed between the metal source 4 and the drain 1.

[0030] In this embodiment, the P well layer includes a heavily doped P well layer 18, a lightly doped P well layer 12 and a lightly doped P well layer 2 14; the N well layer includes a heavily doped N well layer 19, a heavily doped N well layer 2 10, a lightly doped N well layer 11 and a lightly doped N well layer 2 13.

[0031] Among them, the heavily doped N well layer is doped with 8.3~9×10 18 mol / cm 3 Phosphorus;

[0032] The heavily doped N-well layer is doped with 2 to 3×10 18 mol / cm 3 Phosphorus;

[0033] Among them, the lightly doped N well layer 11 is doped with 1.2~2.5×10 15 mol / cm 3 Phosphorus;

[0034] The lightly doped N-well layer 13 is doped with 7.8~9.5×10 15 mol / cm 3 Phosphorus element.

[0035] Furthermore, when the gate 5 is connected to a gate voltage, a charge channel 16 is formed inside the lightly doped P-well layer 14 , and the charge channel 16 connects the diffusion layer 6 and the N-well layer.

[0036] In this embodiment, six equidistant rectangular grooves are etched inside the substrate layer 2 of a single MOS cell, and drain metal 3 is deposited inside the rectangular grooves. The drain metal 3 is connected to the drain electrode 1 in ohms. The substrate layer 2 of a single MOS cell is prepared by ion implantation with a large amount in the middle and a small amount on both sides, wherein the cross section of the substrate layer 2 is a shape of a protrusion in the middle and depressions on both sides. This design of designing the substrate layer 2 to be a protrusion in the middle and embedding the drain metal 3 in the protruding area can greatly increase the heat dissipation properties. In addition, the distance from the top of the drain metal 3 to the diffusion layer 6 is consistent with the distance from the drain electrode 1 to the diffusion layer 6 at both ends, which can reduce the on-resistance between the drain and source of the MOS semiconductor.

[0037] In this embodiment, a U-groove is etched inside the adjacent heavily doped P-well layer 8, and a gate-shaped spacer 7 is embedded inside the U-groove. The gate-shaped spacers 7 between adjacent MOS cells are together, and the gate-shaped spacers 7 are made of metal silver and are in ohmic contact with the metal source 4. In this way, the gate-shaped spacers 7 are embedded between adjacent MOS cells, and the gate-shaped spacers 7 are made of metal silver, so that the heat accumulated in the silicon crystal of a single MOS cell can be quickly transferred to the metal source 4 through the gate-shaped spacers 7 and diffused.

[0038] In this embodiment, the N-well layer is in two layers, the heavily doped N-well layer 2 10 and the lightly doped N-well layer 1 1 are located in the upper layer, and the heavily doped N-well layer 1 9 and the lightly doped N-well layer 2 13 are located in the lower layer. The width of the heavily doped N-well layer 2 10 is three times the width of the lightly doped N-well layer 1 1, and the width of the lightly doped N-well layer 2 13 is three times the width of the heavily doped N-well layer 1 9 (as shown in FIG. Figure 2 As shown), after the charge channel 16 is formed, the charges mainly flow from the doped N-well layer 10 to the metal source 4; wherein, the lightly doped N-well layer 11 can reduce the charge to move closer to the lightly doped P-well layer 12 region, and the doped N-well layer 9 inhibits the charge from drifting toward the doped P-well layer 14.

[0039] In this embodiment, an oxide insulating layer 15 is deposited on the outer surface of the gate 5 , and the oxide insulating layer 15 isolates the gate 5 from the metal source 4 and the ohmic contact of the MOS cell.

[0040] In this embodiment, when the gate 5 is under voltage application, a depletion layer of the JFET region 17 is formed in the diffusion layer 6 thereof. The JFET region 17 is located between two heavily doped P well layers 18 (eg, Figure 3 As shown), by controlling the gate voltage, the conductive properties of the JFET region 17 can be controlled, thereby controlling the conduction current between the drain and the source.

[0041] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions or substitutions made by ordinary technicians in this technical field within the essential scope of the present invention also fall within the protection scope of the present invention.

Claims

1. A high-efficiency thermal isolation structure for SiC VDMOSFET, characterized in that: It comprises a plurality of mutually parallel MOS cells, wherein the MOS cells comprise a substrate layer (2), a diffusion layer (6), a P-well layer and an N-well layer; The bottom layers of several MOS cells are ohmically connected to drain electrodes (1), the top layers of several MOS cells are ohmically connected to metal sources (4), and gate electrodes (5) are embedded between the MOS cells and the metal sources (4); Six equidistant rectangular grooves are etched inside the substrate layer (2) of a single MOS cell, a drain metal (3) is deposited inside the rectangular groove, and the drain metal (3) is ohmically connected to the drain electrode (1); The P-well layer includes a heavily doped P-well layer 1 (8), a lightly doped P-well layer 1 (12) and a lightly doped P-well layer 2 (14); The N-well layer includes a heavily doped N-well layer 1 (9), a heavily doped N-well layer 2 (10), a lightly doped N-well layer 1 (11) and a lightly doped N-well layer 2 (13).

2. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: The substrate layer (2) of a single MOS cell is prepared by ion implantation with more ions in the middle and less ions on both sides, wherein the cross section of the substrate layer (2) is in the shape of a protrusion in the middle and depressions on both sides.

3. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: A U-groove is etched inside the adjacent heavily doped P-well layer 1 (8), and a gate-shaped partition (7) is embedded inside the U-groove.

4. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 3, characterized in that: The gate-shaped spacers (7) between adjacent MOS cells are shared together, and the gate-shaped spacers (7) are made of metal silver and are in ohmic contact with the metal source electrode (4).

5. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: The N-well layer is in two layers, with the heavily doped N-well layer 2 (10) and the lightly doped N-well layer 1 (11) located in the upper layer, and the heavily doped N-well layer 1 (9) and the lightly doped N-well layer 2 (13) located in the lower layer.

6. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 5, characterized in that: The width of the heavily doped N-well layer 2 (10) is three times the width of the lightly doped N-well layer 1 (11), and the width of the lightly doped N-well layer 2 (13) is three times the width of the heavily doped N-well layer 1 (9).

7. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: When the gate (5) is connected to a gate voltage state, a charge channel (16) is formed inside the lightly doped P well layer 2 (14), and the charge channel (16) connects the diffusion layer (6) and the N well layer.

8. The high-efficiency thermal isolation structure for SiC VDMOSFET according to any one of claims 1 to 7, characterized in that: The heavily doped N-well layer 1 (9) and the heavily doped N-well layer 2 (10) are doped with high concentration of phosphorus ions by ion implantation; The lightly doped N-well layer 1 (11) and the lightly doped N-well layer 2 (13) are doped with low-concentration phosphorus ions by ion implantation.

9. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: An oxidized insulating layer (15) is deposited on the outer surface of the gate (5), and the oxidized insulating layer (15) isolates the gate (5) from ohmic contact with the metal source (4) and the MOS cell.

10. The high-efficiency thermal isolation structure for SiC VDMOSFET according to claim 1, characterized in that: When a voltage is applied to the gate (5), a depletion layer of a JFET region (17) is formed in the diffusion layer (6), and the JFET region (17) is located between two heavily doped P well layers (8).

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