Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a semiconductor device, a manufacturing method thereof and electronic equipment, the semiconductor device comprises a first electrode, a second electrode and a metal oxide layer, and the first electrode is connected with the second electrode through the metal oxide layer; at least one of the first electrode and the second electrode is provided with a passivation layer, and the metal oxide layer is connected with at least one of the first electrode and the second electrode through the passivation layer; and the contact resistance between the electrode and the metal oxide layer is reduced.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to but are not limited to semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] The application of oxide thin film transistors in emerging fields is becoming increasingly important, such as flexible display, Internet of Things, wearable electronics, memory, etc. However, oxide semiconductor materials are unstable. For example, H atoms can easily diffuse into oxide materials, inducing oxygen vacancies, causing degradation and instability of the device's electrical performance, and the device's driving current is largely limited by the source-drain contact resistance and is difficult to increase. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The present disclosure provides a semiconductor device, comprising: a substrate, and a first electrode, a second electrode, and a metal oxide layer disposed on the substrate, wherein the first electrode is connected to the second electrode through the metal oxide layer;

[0005] At least one of the first electrode and the second electrode is provided with a passivation layer, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

[0006] In an exemplary embodiment, the passivation layer is at least one of fluoride and nitride.

[0007] In an exemplary embodiment, the thickness of the passivation layer is less than 1 nanometer.

[0008] In an exemplary embodiment, a first passivation layer is disposed between the first electrode and the metal oxide layer.

[0009] In an exemplary embodiment, the first passivation layer and the first electrode are connected as one body.

[0010] In an exemplary embodiment, it also includes a hole, which at least penetrates the first electrode to expose the side wall of the corresponding hole on the first electrode, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the first electrode through the first passivation layer.

[0011] In an exemplary embodiment, a second passivation layer is disposed between the second electrode and the metal oxide layer.

[0012] In an exemplary embodiment, the second passivation layer and the second electrode are connected as one body.

[0013] In an exemplary embodiment, a hole is further included, wherein the hole exposes at least a portion of the second electrode, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the second electrode through the second passivation layer.

[0014] In an exemplary embodiment, a second insulating layer is further included, the second insulating layer is located between the first electrode and the second electrode, a first barrier layer is disposed on the second insulating layer, and the second insulating layer is connected to the metal oxide layer through the first barrier layer.

[0015] In an exemplary embodiment, it also includes a hole, which at least penetrates the second insulating layer to expose the side wall of the second insulating layer, the first barrier layer is arranged on the side wall of the second insulating layer, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the second insulating layer through the first barrier layer.

[0016] In an exemplary embodiment, the first barrier layer is at least one of fluoride and nitride.

[0017] In an exemplary embodiment, the first barrier layer and the second insulating layer are connected as one body.

[0018] In an exemplary embodiment, a third insulating layer is further included, the first electrode is located on a side of the second electrode away from the substrate, the third insulating layer is located on a side of the first electrode away from the substrate, a second blocking layer is arranged on the third insulating layer, and the third insulating layer is connected to the metal oxide layer through the second blocking layer.

[0019] In an exemplary embodiment, it also includes a hole, which at least penetrates the third insulating layer to expose the side wall of the third insulating layer, the second barrier layer is arranged on the side wall of the third insulating layer, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the third insulating layer through the second barrier layer.

[0020] In an exemplary embodiment, the second barrier layer is at least one of fluoride and nitride.

[0021] In an exemplary embodiment, the second barrier layer and the third insulating layer are connected as one body.

[0022] The present disclosure also provides a method for manufacturing a semiconductor device, including:

[0023] forming a second electrode and a first electrode in sequence on the substrate;

[0024] forming a passivation layer on at least one of the second electrode and the first electrode;

[0025] A metal oxide layer is formed on the substrate, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

[0026] In an exemplary embodiment, a method for manufacturing a semiconductor device includes:

[0027] forming a second conductive layer, a second insulating film, a first conductive layer and a third insulating film in sequence on the substrate;

[0028] By using an etching process, a hole extending in a direction perpendicular to the substrate is formed in the third insulating film, the first conductive layer, the second insulating film and the second conductive layer, so that the second conductive layer forms a second electrode, the second insulating film forms a second insulating layer, the first conductive layer forms a first electrode, and the third insulating film forms a third insulating layer, wherein the hole at least exposes the side wall of the third insulating layer, the side wall of the first electrode, the side wall of the second insulating layer, and the side wall and bottom wall of the second electrode;

[0029] Plasma treatment is used to dope at least one of fluorine and nitrogen into the side walls of the third insulating layer, the side walls of the first electrode, the side walls of the second insulating layer, and the side walls and bottom walls of the second electrode, so that a second barrier layer is formed on the side walls of the third insulating layer, a first passivation layer is formed on the side walls of the first electrode, a first barrier layer is formed on the side walls of the second insulating layer, and a second passivation layer is formed on the side walls and bottom walls of the second electrode.

[0030] An embodiment of the present disclosure also provides an electronic device, comprising any of the semiconductor devices described above.

[0031] The embodiment of the present disclosure reduces the contact resistance between the first electrode and the metal oxide layer through the first passivation layer, inhibits the formation of oxide on the surface of the first electrode, and solves the problem that metal oxide is formed on the surface of the first electrode during the process of forming the metal oxide layer, thereby increasing the resistance of the first electrode.

[0032] The disclosed embodiment dopes the surface of the side wall of the first electrode with fluorine (or fluorine and nitrogen) through plasma treatment, thereby avoiding damage to the side wall of the first electrode and ensuring the integrity of the morphology of the first electrode.

[0033] The embodiment of the present disclosure reduces the contact resistance between the second electrode and the metal oxide layer through the second passivation layer, inhibits the formation of oxide on the surface of the second electrode, and solves the problem that metal oxide is formed on the surface of the second electrode during the process of forming the metal oxide layer, thereby increasing the resistance of the second electrode.

[0034] The disclosed embodiment dopes the surface of the side wall of the second electrode with fluorine (or fluorine and nitrogen) through plasma treatment, thereby avoiding damage to the side wall of the second electrode and ensuring the integrity of the morphology of the second electrode.

[0035] The disclosed embodiment uses the first barrier layer to prevent hydrogen atoms in the second insulating layer, or external water vapor, from entering the metal oxide layer through the second insulating layer, causing unstable device performance. In addition, fluorine (F) or nitrogen (N) in the first barrier layer will form MF bonds or MN bonds with metal atoms (M) in the metal oxide layer. The bond energies of MF bonds and MN bonds are both greater than MO bonds, so that the first barrier layer can inhibit the formation of oxygen vacancies in the metal oxide layer and improve the stability of device performance.

[0036] The disclosed embodiment dopes the surface of the side wall of the second insulating layer with fluorine (or fluorine and nitrogen) through plasma treatment, thereby avoiding damage to the side wall of the second insulating layer and ensuring the integrity of the morphology of the second insulating layer.

[0037] The disclosed embodiment uses the second barrier layer to prevent hydrogen atoms in the third insulating layer, or external water vapor, from entering the metal oxide layer through the third insulating layer, causing unstable device performance. In addition, fluorine (F) or nitrogen (N) in the second barrier layer will form MF bonds or MN bonds with metal atoms (M) in the metal oxide layer. The bond energies of MF bonds and MN bonds are both greater than MO bonds, so that the second barrier layer can inhibit the formation of oxygen vacancies in the metal oxide layer and improve the stability of device performance.

[0038] In the embodiment of the present disclosure, fluorine (or fluorine and nitrogen) is doped on the surface of the side wall of the third insulating layer through plasma treatment, thereby avoiding damage to the side wall of the third insulating layer and ensuring the integrity of the morphology of the third insulating layer.

[0039] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The objects and advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description and the drawings.

[0040] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution.

[0042] Figure 1 A schematic cross-sectional view of a semiconductor device along a direction perpendicular to a substrate provided by an exemplary embodiment;

[0043] Figure 2A A schematic diagram of a semiconductor device after an insulating film and a conductive layer are formed in a manufacturing process of an exemplary embodiment;

[0044] Figure 2B A schematic diagram of a semiconductor device after holes are formed in a manufacturing process provided for an exemplary embodiment;

[0045] Figure 2C A schematic diagram of a semiconductor device after a passivation layer and a barrier layer are formed in a manufacturing process of an exemplary embodiment is provided. DETAILED DESCRIPTION

[0046] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other arbitrarily.

[0047] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the common meanings understood by one of ordinary skill in the art to which the present invention belongs.

[0048] The embodiments of the present disclosure are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect the true proportions. In addition, the drawings schematically show ideal examples, and the embodiments of the present disclosure are not limited to the shapes or values ​​shown in the drawings.

[0049] The ordinal numbers such as “first”, “second” and “third” in the present disclosure are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0050] In the present disclosure, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing the present specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the disclosure and can be appropriately replaced according to the circumstances.

[0051] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0052] In the present disclosure, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, a channel region refers to a region where current mainly flows.

[0053] In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" may be interchanged.

[0054] In the present disclosure, "electrical connection" includes the case where components are connected together through an element having some kind of electrical function. There is no particular limitation on the "element having some kind of electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some kind of electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0055] In the present disclosure, "parallel" means approximately parallel or almost parallel, for example, the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, the angle is greater than -5° and less than 5°. In addition, "perpendicular" means approximately perpendicular, for example, the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, the angle is greater than 85° and less than 95°.

[0056] In the present disclosure, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film" in some cases. Similarly, "insulating film" may be replaced with "insulating layer" in some cases.

[0057] The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0058] In the embodiments of the present disclosure, "A and B are an integrated structure" may mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer patterned to form a connection is an integrated structure. For example, A and B use the same material to form a film layer and form a structure with a connection relationship at the same time through the same patterning process.

[0059] The present disclosure provides a semiconductor device, comprising: a substrate, and a first electrode, a second electrode, and a metal oxide layer disposed on the substrate, wherein the first electrode is connected to the second electrode through the metal oxide layer;

[0060] At least one of the first electrode and the second electrode is provided with a passivation layer, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

[0061] The semiconductor device disclosed in the present invention is described below by way of some exemplary embodiments.

[0062] Figure 1 A schematic diagram of a cross section of a semiconductor device provided in accordance with an exemplary embodiment along a direction perpendicular to the substrate Figure 1 .like Figure 1 As shown, the semiconductor device may include: a first insulating layer 51, a second electrode 32, a second insulating layer 52, a first electrode 31, a third insulating layer 53, which are arranged in sequence along the vertical direction of the substrate 1, a gate electrode 34 extending in a direction perpendicular to the substrate, and a metal oxide layer 33 surrounding the gate electrode 34 and insulated from the gate electrode 34.

[0063] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate.

[0064] In an exemplary embodiment, the semiconductor device may further include: a hole 61, which extends in a direction perpendicular to the substrate 1. The hole 61 is formed from the surface of the third insulating layer 53 away from the substrate 1, and in a direction perpendicular to the substrate 1, sequentially penetrates the third insulating layer 53, the first electrode 31, and the second insulating layer 52, and extends to the second electrode 32. The hole 61 does not completely penetrate the second electrode 32, and a groove 62 is formed at the second electrode 32. The hole 61 exposes at least part of the sidewalls of the third insulating layer 53, the sidewalls of the first electrode 31, the sidewalls of the second insulating layer 52, and the sidewalls and bottom wall of the groove 62 of the second electrode 32.

[0065] In some embodiments, the hole may extend from the surface of the third insulating layer away from the substrate, in a direction perpendicular to the substrate, through the third insulating layer, the first electrode, and the second insulating layer in sequence, to the surface of the second electrode away from the substrate 1. The hole exposes at least part of the sidewall of the third insulating layer, the sidewall of the first electrode, the sidewall of the second insulating layer, and the sidewall and bottom wall of the groove 62 of the second electrode.

[0066] In an exemplary embodiment, the main portion of the gate electrode 34 is filled in the hole 61. The main portion of the gate electrode 34 is a line extending along the second direction Y, that is, the main portion of the gate electrode 34 is a line extending perpendicular to the substrate direction.

[0067] In an exemplary embodiment, the top of the main body of the gate electrode 34 is provided with a horizontal segment extending in a direction parallel to the substrate 1, and the horizontal segment is located on the side of the third insulating layer 53 away from the substrate 1. For example, the top of the main body of the gate electrode 34 is provided with a first horizontal segment extending in a first direction X, and a second horizontal segment extending in the opposite direction of the first direction X. The first direction X is a direction parallel to the substrate 1, the second direction Y is a direction perpendicular to the substrate 1, and the first direction X and the second direction Y are perpendicular to each other.

[0068] In an exemplary embodiment, the material composition of different regions of the gate electrode 34 extending in a direction perpendicular to the substrate is the same, which can be understood as being formed using the same film manufacturing process. The same material composition can be understood as the same main elements tested in the material, for example, they are all made of transparent conductive materials such as metal or ITO, but the atomic number ratio of different regions is not limited.

[0069] In an exemplary embodiment, the gate electrode 34 extends only in a direction perpendicular to the substrate (second direction Y). The gate electrode 34 includes a side surface and end surfaces at its upper and lower ends, and the side surface is perpendicular to the substrate 1 as a whole. In the actual process of manufacturing products, the side surface may be partially curved, which is also included in the above-mentioned situation of the present application.

[0070] In an exemplary embodiment, the material of the gate electrode 34 may include but is not limited to at least one of the following: indium tin oxide (ITO), metal tungsten, titanium nitride, titanium aluminum alloy, tantalum nitride, aluminum doped zinc oxide (AZO), indium zinc oxide (IZO).

[0071] In an exemplary embodiment, the main part of the metal oxide layer 33 is located in the hole 61. The main part of the metal oxide layer 33 includes at least a side wall and a top and a bottom located at both ends of the side wall. The side wall of the metal oxide layer 33 surrounds the gate electrode 34 and is insulated from the gate electrode 34. Among them, the metal oxide layer 33 can be understood as a film layer. The side wall of the metal oxide layer 33 extends along the side surface of the gate electrode 34, the thickness direction of the side wall is parallel to the substrate, the length of the side wall extending up and down the side surface of the gate electrode 34 is the height of the side wall, and the length of the side wall surrounding the side surface of the gate electrode 34 is the width of the side wall.

[0072] In an exemplary embodiment, the side wall of the main part of the metal oxide layer 33 extends on the side surface of the gate electrode 34 to form a ring extending in a direction perpendicular to the substrate; the top of the main part of the metal oxide layer 33 may be provided with an extension portion extending in a direction parallel to the substrate, and the extension portion is located on the side of the third insulating layer 53 away from the substrate 1, and is located between the horizontal section of the gate electrode 34 and the third insulating layer 53. For example, the top of the main part of the metal oxide layer 33 is provided with a first extension portion extending in the first direction X, and a second extension portion extending in the opposite direction of the first direction X. Alternatively, the metal oxide layer 33 is only a ring-shaped film layer extending in a direction perpendicular to the substrate.

[0073] The sidewall surrounding of the metal oxide layer 33 can be understood as partially or completely surrounding the gate electrode 34. In some embodiments, the surrounding can be completely surrounded as a whole, and the cross section of the metal oxide layer 33 after the surrounding is a closed ring. The interception direction of the cross section is intercepted along the direction parallel to the substrate. In some embodiments, the surrounding can be partially surrounded, and the cross section after the surrounding is not closed, but presents a ring shape. For example, a ring with an opening.

[0074] In an exemplary embodiment, the material of the metal oxide layer 33 may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO , IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO) and other materials. As long as the leakage current of the transistor can meet the requirements, the specific details can be adjusted according to the actual situation.

[0075] In an exemplary embodiment, the transistor may further include a gate insulating layer 21, and a main portion of the gate insulating layer 21 is located in the hole 61. The main portion of the gate insulating layer 21 surrounds the sidewall of the gate electrode 34. The gate insulating layer 21 is disposed between the metal oxide layer 33 and the gate electrode 34 to separate the metal oxide layer 33 from the gate electrode 34.

[0076] In an exemplary embodiment, the material of the gate insulating layer 21 may be a high-K dielectric material. The high-K dielectric material may include but is not limited to at least one of the following: aluminum oxide, hafnium oxide, hafnium aluminum oxide, and hafnium lanthanum oxide. In some embodiments, the material of the gate insulating layer 21 may be a low-K material, silicon dioxide.

[0077] In an exemplary embodiment, the first electrode 31 and the second electrode 32 are located in different film layers, and both the first electrode 31 and the second electrode 32 extend in a direction parallel to the substrate and are arranged perpendicular to the gate electrode 34. The first electrode 31 is located on the side of the second electrode 32 opposite to the second direction Y, and is insulated from the second electrode 32 by the second insulating layer 52. The first electrode 31 is electrically connected to the side wall of the main part of the metal oxide layer 33, and the second electrode 32 is connected to the bottom end of the main part of the metal oxide layer 33.

[0078] In an exemplary embodiment, the metal oxide layer 33 extends on the sidewall of the gate electrode 34 to form a ring-shaped film layer extending in a direction perpendicular to the substrate; wherein the metal oxide layer 33 between the first electrode 51 and the second electrode 52 is a channel 41, and the channel is a horizontal channel. The first electrode 31 and the second electrode 32 are connected to each other through the channel 41.

[0079] A horizontal channel is a channel in which the carrier transmission direction is in a plane parallel to the substrate, but the carrier transmission direction is not limited to one direction. In practical applications, the carrier transmission direction extends in one direction as a whole, but locally, it is related to the shape of the metal oxide layer. In other words, a horizontal channel does not mean that it must extend in one direction in the horizontal plane, and may extend in different directions. For example, when the metal oxide layer is annular, the source contact area and the drain contact area on the annular metal oxide layer are part of the ring. At this time, the carriers extend from the source contact area to the drain contact area in one direction as a whole, and may not be in a certain direction locally. Of course, the carrier transmission direction in a plane parallel to the substrate is also a macroscopic concept, and is not limited to being absolutely parallel to the substrate. The present application protects the channel between the first electrode and the second electrode as a channel that is not perpendicular to the substrate.

[0080] In an exemplary embodiment, the materials of the first electrode 31 and the second electrode 32 may be selected from metal materials with low resistivity, such as titanium nitride (TiN), tungsten, molybdenum, and the like.

[0081] In an exemplary embodiment, the first insulating layer 51 is located between the substrate 1 and the second electrode 32 , the second insulating layer 52 is located between the second electrode 32 and the first electrode 31 , and the third insulating layer 53 is located on a side of the first electrode 31 away from the substrate 1 .

[0082] In an exemplary embodiment, the first insulating layer 51 , the second insulating layer 52 and the third insulating layer 53 may all be low-k materials, or silicon oxides, such as silicon dioxide (SiO 2 ).

[0083] In an exemplary embodiment, the first electrode 31, the second electrode 32, the gate electrode 34, and the channel 41 of the present application may constitute a transistor. The transistor of the present application may form a 1T1C memory with a capacitor, or form a 2T0C memory with other transistors, and so on.

[0084] In an exemplary embodiment, if Figure 1 As shown, the storage unit may also include: a first passivation layer 71, the first passivation layer 71 is on the side wall of the hole 61, and the first passivation layer 71 is arranged on the side wall of the first electrode 31 exposed in the hole 61, and the first passivation layer 71 is located between the side wall of the first electrode 31 and the side wall of the metal oxide layer 33.

[0085] In an exemplary embodiment, the first passivation layer 71 is connected to the first electrode 31 as a whole. The sidewall of the first electrode 31 may be treated by plasma treatment, so that the first passivation layer 71 is formed on the sidewall surface of the first electrode 31 .

[0086] In an exemplary embodiment, the first passivation layer 71 may be at least one of fluoride and nitride. The surface of the sidewall of the first electrode 31 may be doped with fluorine (or fluorine and nitrogen) by plasma treatment to form the first passivation layer 71 on the surface of the sidewall of the first electrode 31.

[0087] In the embodiment of the present disclosure, fluorine (or fluorine and nitrogen) is doped on the surface of the side wall of the first electrode 31 through plasma treatment, which can avoid damage to the side wall of the first electrode 31 and ensure the integrity of the morphology of the first electrode 31.

[0088] In an exemplary embodiment, the thickness of the first passivation layer 71 is less than 1 nanometer. For example, the thickness of the first passivation layer 71 may be 0.2 nanometers, 0.4 nanometers, 0.6 nanometers, 0.8 nanometers, etc.

[0089] The embodiment of the present disclosure reduces the contact resistance between the first electrode 31 and the metal oxide layer 33 through the first passivation layer 71, inhibits the formation of oxide on the surface of the first electrode 31, and solves the problem that metal oxide is formed on the surface of the first electrode 31 during the process of forming the metal oxide layer 33, thereby increasing the resistance of the first electrode 31.

[0090] In an exemplary embodiment, if Figure 1 As shown, the storage unit may also include: a second passivation layer 72, the second passivation layer 72 is on the side walls and bottom walls of the hole 61, that is, the second passivation layer 72 is arranged on the side walls and bottom walls of the groove 62 of the second electrode 31, and the second passivation layer 72 is located between the side walls of the second electrode 31 and the side walls of the metal oxide layer 33.

[0091] In an exemplary embodiment, the second passivation layer 72 is integrally connected to the second electrode 31. The second electrode 31 may be made of metal, and the sidewalls and bottom wall of the groove 62 of the second electrode 31 may be treated by plasma treatment to form the second passivation layer 72 on the sidewalls and bottom wall of the groove 62 of the second electrode 31.

[0092] In an exemplary embodiment, the second passivation layer 72 may be at least one of fluoride and nitride. The surface of the sidewall of the second electrode 31 may be doped with fluorine (or fluorine and nitrogen) by plasma treatment to form the second passivation layer 72 on the surface of the sidewall of the second electrode 31.

[0093] In the embodiment of the present disclosure, fluorine (or fluorine and nitrogen) is doped on the surface of the side wall of the second electrode 31 through plasma treatment, which can avoid damage to the side wall of the second electrode 31 and ensure the integrity of the morphology of the second electrode 31.

[0094] In an exemplary embodiment, the thickness of the second passivation layer 72 is less than 1 nanometer. For example, the thickness of the second passivation layer 72 can be 0.2 nanometers, 0.4 nanometers, 0.6 nanometers, 0.8 nanometers, etc.

[0095] The embodiment of the present disclosure reduces the contact resistance between the second electrode 31 and the metal oxide layer 33 through the second passivation layer 72, inhibits the formation of oxide on the surface of the second electrode 31, and solves the problem that metal oxide is formed on the surface of the second electrode 31 during the process of forming the metal oxide layer 33, thereby increasing the resistance of the second electrode 31.

[0096] In an exemplary embodiment, if Figure 1 As shown, the storage unit may further include: a first barrier layer 81, the first barrier layer 81 is on the side wall of the hole 61, that is, the first barrier layer 81 is arranged on the side wall of the second insulating layer 52, and the first barrier layer 81 is located between the side wall of the second insulating layer 52 and the side wall of the metal oxide layer 33.

[0097] In an exemplary embodiment, the first barrier layer 81 is integrally connected with the second insulating layer 52. The sidewall of the second insulating layer 52 may be treated by plasma treatment, so that the first barrier layer 81 is formed on the sidewall surface of the second insulating layer 52.

[0098] In an exemplary embodiment, the first barrier layer 81 may be at least one of fluoride and nitride. The surface of the sidewall of the second insulating layer 52 may be doped with fluorine (or fluorine and nitrogen) by plasma treatment to form the first barrier layer 81 on the surface of the sidewall of the second insulating layer 52.

[0099] In the embodiment of the present disclosure, fluorine (or fluorine and nitrogen) is doped on the surface of the side wall of the second insulating layer 52 through plasma treatment, which can avoid damage to the side wall of the second insulating layer 52 and ensure the integrity of the morphology of the second insulating layer 52.

[0100] In an exemplary embodiment, the thickness of the first barrier layer 81 is less than 1 nanometer. For example, the thickness of the first barrier layer 81 may be 0.2 nanometers, 0.4 nanometers, 0.6 nanometers, 0.8 nanometers, etc.

[0101] The embodiment of the present disclosure uses the first barrier layer 81 to prevent hydrogen atoms in the second insulating layer 52 or external water vapor from entering the metal oxide layer 33 through the second insulating layer 52, causing unstable device performance. In addition, fluorine (F) or nitrogen (N) in the first barrier layer 81 and metal atoms (M) in the metal oxide layer 33 will form MF bonds or MN bonds, and the bond energies of MF bonds and MN bonds are both greater than MO bonds, so that the first barrier layer 81 can inhibit the formation of oxygen vacancies in the metal oxide layer 33 and improve the stability of device performance.

[0102] In an exemplary embodiment, if Figure 1 As shown, the storage unit may further include: a second barrier layer 82 , the second barrier layer 82 is on the side wall of the hole 61 , that is, the second barrier layer 82 is arranged on the side wall of the third insulating layer 53 , and the second barrier layer 82 is located between the side wall of the third insulating layer 53 and the side wall of the metal oxide layer 33 .

[0103] In an exemplary embodiment, the second barrier layer 82 is integrally connected to the third insulating layer 53. The sidewall of the third insulating layer 53 may be treated by plasma treatment, so that the second barrier layer 82 is formed on the sidewall surface of the third insulating layer 53.

[0104] In an exemplary embodiment, the second barrier layer 82 may be at least one of a fluoride and a nitride. The surface of the sidewall of the third insulating layer 53 may be doped with fluorine (or fluorine and nitrogen) by plasma treatment to form the second barrier layer 82 on the surface of the sidewall of the third insulating layer 53.

[0105] In the embodiment of the present disclosure, fluorine (or fluorine and nitrogen) is doped on the surface of the side wall of the third insulating layer 53 through plasma treatment, which can avoid damage to the side wall of the third insulating layer 53 and ensure the integrity of the morphology of the third insulating layer 53.

[0106] In an exemplary embodiment, the thickness of the second barrier layer 82 is less than 1 nanometer. For example, the thickness of the second barrier layer 82 can be 0.2 nanometers, 0.4 nanometers, 0.6 nanometers, 0.8 nanometers, etc.

[0107] The embodiment of the present disclosure forms a second barrier layer 82 between the third insulating layer 53 and the metal oxide layer 33 to prevent hydrogen atoms in the third insulating layer 53 or external water vapor from entering the metal oxide layer 33 through the third insulating layer 53, thereby causing unstable device performance. In addition, fluorine (F) or nitrogen (N) in the second barrier layer 82 and metal atoms (M) in the metal oxide layer 33 form MF bonds or MN bonds, and the bond energies of the MF bonds and the MN bonds are both greater than the MO bonds, so that the second barrier layer 82 can inhibit the formation of oxygen vacancies in the metal oxide layer 33 and improve the stability of device performance.

[0108] The technical solution of this embodiment is further explained below through the manufacturing process of the semiconductor device of this embodiment. The "patterning process" mentioned in this embodiment includes deposition of film layer, coating of photoresist, mask exposure, development, etching, stripping of photoresist and other processes, which are mature manufacturing processes in related technologies. The "photolithography process" mentioned in this embodiment includes coating of film layer, mask exposure and development, which are mature manufacturing processes in related technologies. Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not specifically limited here. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require a patterning process or a photolithography process during the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" still requires a patterning process or a photolithography process during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process contains at least one "pattern".

[0109] In an exemplary embodiment, the semiconductor device may be any of the semiconductor devices described above, and the manufacturing process of the semiconductor device may include:

[0110] Step 101, forming an insulating film and a conductive layer.

[0111] The forming of the insulating film and the conductive layer includes: sequentially forming a first insulating film 91, a second conductive layer 94, a second insulating film 93, a first conductive layer 92 and a third insulating film 95 on the substrate 1, such as Figure 2A shown.

[0112] In an exemplary embodiment, the first insulating film 91, the second conductive layer 94, the second insulating film 93, the first conductive layer 92 and the third insulating film 95 may be deposited using a chemical vapor deposition method (CVD), an atomic layer deposition method (ALD) or a physical vapor deposition method (PVD).

[0113] In an exemplary embodiment, the substrate may be a semiconductor substrate, such as a silicon substrate. Of course, it may be any substrate that plays a supporting role, not just a base, but may be a substrate formed by peripheral circuits on the substrate.

[0114] In an exemplary embodiment, the first insulating film 91, the second insulating film 93 and the third insulating film 95 play an isolation role between devices. The first insulating film 91, the second insulating film 93 and the third insulating film 95 can all be low-k materials, or silicon oxides, such as silicon dioxide (SiO2), etc. In addition, the thickness of the second insulating film 93 determines the length of the transistor channel.

[0115] In an exemplary embodiment, the materials of the first insulating film 91 , the second insulating film 93 , and the third insulating film 95 may be the same or different.

[0116] In an exemplary embodiment, the first conductive layer 92 and the second conductive layer 94 may be made of a metal material with low resistivity to reduce the influence of parasitic resistance, such as titanium nitride (TiN), tungsten, molybdenum, etc.

[0117] In an exemplary embodiment, the materials of the first conductive layer 92 and the second conductive layer 94 may be the same or different.

[0118] Step 102: forming holes.

[0119] The hole formation includes: on the basis of the substrate 1 formed with the aforementioned pattern, a hole 61 is formed in the third insulating film, the first conductive layer, the second insulating film and the second conductive layer by using photolithography and etching processes, and the hole 61 extends in a direction perpendicular to the substrate 1. The first insulating film forms the first insulating layer 51, the second conductive layer 94 forms the second electrode 32, the second insulating film forms the second insulating layer 52, the first conductive layer forms the first electrode 31, and the third insulating film forms the third insulating layer 53. The hole 61 extends from the surface of the third insulating layer 53 away from the substrate 1, and penetrates the third insulating layer 53, the first electrode 31, and the second insulating layer 52 in sequence along the direction perpendicular to the substrate 1 to the second electrode 32. The hole 61 does not completely penetrate the second electrode 32, and a groove 62 is formed at the second electrode 32. The hole 61 exposes at least part of the sidewalls of the third insulating layer 53, the sidewalls of the first electrode 31, the sidewalls of the second insulating layer 52, and the sidewalls and bottom walls of the groove 62 of the second electrode 32, such as Figure 2B shown.

[0120] Step 103: forming a passivation layer and a barrier layer.

[0121] The formation of the passivation layer and the barrier layer includes: on the basis of the substrate 1 formed with the aforementioned pattern, a plasma treatment is performed to dope fluorine (or fluorine and nitrogen) into the sidewalls of the third insulating layer 53, the sidewalls of the first electrode 31, the sidewalls of the second insulating layer 52, and the sidewalls and bottom walls of the groove 62 of the second electrode 32, so that a second barrier layer 82 is formed on the sidewalls and surface of the third insulating layer 53, and the second barrier layer 82 may be a fluoride (or fluorine and nitride); a first passivation layer 71 is formed on the sidewalls of the first electrode 31, and the first passivation layer 71 may be a fluoride (or fluorine and nitride); a first barrier layer 81 is formed on the sidewalls of the second insulating layer 52, and the first barrier layer 81 may be a fluoride (or fluorine and nitride); a second passivation layer 72 is formed on the sidewalls and bottom walls of the groove 62 of the second electrode 32, and the second passivation layer 72 may be a fluoride (or fluorine and nitride), such as Figure 2C shown.

[0122] In some embodiments, multiple plasma treatments may be used to dope fluorine (or fluorine and nitrogen) into the sidewalls of the third insulating layer 53 in the hole 61, the sidewalls of the first electrode 31, the sidewalls of the second insulating layer 52, and the sidewalls and bottom walls of the groove 62 of the second electrode 32.

[0123] In an exemplary embodiment, the power of the plasma treatment is less than 100 W, and the treatment time is less than 60 s. By adopting the low-power short-time plasma treatment, the side walls of the third insulating layer 53, the side walls of the first electrode 31, the side walls of the second insulating layer 52, and the side walls and bottom walls of the groove 62 of the second electrode 32 are almost not damaged, and the morphology of the side walls of the third insulating layer 53, the side walls of the first electrode 31, the side walls of the second insulating layer 52, and the side walls and bottom walls of the groove 62 of the second electrode 32 can be ensured to be intact.

[0124] In an exemplary embodiment, the thickness of the first passivation layer 71 , the second passivation layer 72 , the first barrier layer 81 , and the second barrier layer 82 is less than 1 nm.

[0125] Step 104 , forming a metal oxide layer 33 , a gate insulating layer 21 and a gate electrode 34 .

[0126] The metal oxide layer, the gate insulating layer and the gate electrode are formed by using an atomic layer deposition (ALD) method on the substrate 1 having the aforementioned pattern, and sequentially forming a metal oxide layer 33, a gate insulating layer 21 and a gate electrode 34 on the first passivation layer 71, the second passivation layer 72, the first barrier layer 81 and the second barrier layer 82 of the hole 61, such as Figure 1 shown.

[0127] The present disclosure also provides a method for manufacturing a semiconductor device, wherein the semiconductor device may be any of the semiconductor devices described above; the method for manufacturing the semiconductor device comprises:

[0128] forming a second electrode and a first electrode in sequence on the substrate;

[0129] forming a passivation layer on at least one of the second electrode and the first electrode;

[0130] A metal oxide layer is formed on the substrate, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

[0131] In an exemplary embodiment, the method for manufacturing a semiconductor device further comprises:

[0132] forming a second conductive layer, a second insulating film, a first conductive layer and a third insulating film in sequence on the substrate;

[0133] By using an etching process, a hole extending in a direction perpendicular to the substrate is formed in the third insulating film, the first conductive layer, the second insulating film and the second conductive layer, so that the second conductive layer forms a second electrode, the second insulating film forms a second insulating layer, the first conductive layer forms a first electrode, and the third insulating film forms a third insulating layer, wherein the hole at least exposes the side wall of the third insulating layer, the side wall of the first electrode, the side wall of the second insulating layer, and the side wall and bottom wall of the second electrode;

[0134] Plasma treatment is used to dope at least one of fluorine and nitrogen into the side walls of the third insulating layer, the side walls of the first electrode, the side walls of the second insulating layer, and the side walls and bottom walls of the second electrode, so that a second barrier layer is formed on the side walls of the third insulating layer, a first passivation layer is formed on the side walls of the first electrode, a first barrier layer is formed on the side walls of the second insulating layer, and a second passivation layer is formed on the side walls and bottom walls of the second electrode.

[0135] The present disclosure also provides an electronic device, including the semiconductor device described in any of the above embodiments. The electronic device may be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply. The storage device may include a memory in a computer, etc., which is not limited here.

[0136] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, and a first electrode, a second electrode, and a metal oxide layer disposed on the substrate, wherein the first electrode is connected to the second electrode through the metal oxide layer; At least one of the first electrode and the second electrode is provided with a passivation layer, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

2. The semiconductor device according to claim 1, wherein: The passivation layer is at least one of fluoride and nitride.

3. The semiconductor device according to claim 1, wherein: The thickness of the passivation layer is less than 1 nanometer.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that: A first passivation layer is disposed between the first electrode and the metal oxide layer.

5. The semiconductor device according to claim 4, characterized in that The first passivation layer is connected to the first electrode as a whole.

6. The semiconductor device according to claim 4, characterized in that It also includes a hole, which at least penetrates the first electrode to expose the side wall of the corresponding hole on the first electrode, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the first electrode through the first passivation layer.

7. The semiconductor device according to any one of claims 1 to 3, characterized in that: A second passivation layer is disposed between the second electrode and the metal oxide layer.

8. The semiconductor device according to claim 7, characterized in that The second passivation layer is connected to the second electrode as a whole.

9. The semiconductor device according to claim 7, characterized in that The invention also includes a hole, wherein the hole exposes at least a portion of the second electrode, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the second electrode through the second passivation layer.

10. The semiconductor device according to any one of claims 1 to 3, characterized in that: The invention also includes a second insulating layer, wherein the second insulating layer is located between the first electrode and the second electrode, a first blocking layer is arranged on the second insulating layer, and the second insulating layer is connected to the metal oxide layer through the first blocking layer.

11. The semiconductor device according to claim 10, characterized in that It also includes a hole, which at least penetrates the second insulating layer to expose the side wall of the second insulating layer, the first barrier layer is arranged on the side wall of the second insulating layer, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the second insulating layer through the first barrier layer.

12. The semiconductor device according to claim 10, characterized in that The first barrier layer is at least one of fluoride and nitride.

13. The semiconductor device according to claim 10, characterized in that The first barrier layer and the second insulating layer are connected as one body.

14. The semiconductor device according to any one of claims 1 to 3, characterized in that: It also includes a third insulating layer, the first electrode is located on the side of the second electrode away from the substrate, the third insulating layer is located on the side of the first electrode away from the substrate, a second blocking layer is arranged on the third insulating layer, and the third insulating layer is connected to the metal oxide layer through the second blocking layer.

15. The semiconductor device according to claim 14, characterized in that It also includes a hole, which at least penetrates the third insulating layer to expose the side wall of the third insulating layer, the second barrier layer is arranged on the side wall of the third insulating layer, the metal oxide layer is located in the hole, and the metal oxide layer is connected to the side wall of the third insulating layer through the second barrier layer.

16. The semiconductor device according to claim 14, characterized in that The second barrier layer is at least one of fluoride and nitride.

17. The semiconductor device according to claim 14, characterized in that The second barrier layer and the third insulating layer are connected as one body.

18. A method for manufacturing a semiconductor device, characterized in that: include: forming a second electrode and a first electrode in sequence on the substrate; forming a passivation layer on at least one of the second electrode and the first electrode; A metal oxide layer is formed on the substrate, and the metal oxide layer is connected to at least one of the first electrode and the second electrode through the passivation layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: include: forming a second conductive layer, a second insulating film, a first conductive layer and a third insulating film in sequence on the substrate; By using an etching process, a hole extending in a direction perpendicular to the substrate is formed in the third insulating film, the first conductive layer, the second insulating film and the second conductive layer, so that the second conductive layer forms a second electrode, the second insulating film forms a second insulating layer, the first conductive layer forms a first electrode, and the third insulating film forms a third insulating layer, wherein the hole at least exposes the side wall of the third insulating layer, the side wall of the first electrode, the side wall of the second insulating layer, and the side wall and bottom wall of the second electrode; Plasma treatment is used to dope at least one of fluorine and nitrogen into the side walls of the third insulating layer, the side walls of the first electrode, the side walls of the second insulating layer, and the side walls and bottom walls of the second electrode, so that a second barrier layer is formed on the side walls of the third insulating layer, a first passivation layer is formed on the side walls of the first electrode, a first barrier layer is formed on the side walls of the second insulating layer, and a second passivation layer is formed on the side walls and bottom walls of the second electrode.

20. An electronic device, characterized in that: Comprising the semiconductor device according to any one of claims 1 to 17.

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