DDR module packaging structure and preparation method thereof

Abstract

The invention relates to the technical field of semiconductor device packaging, in particular to a DDR module packaging structure and a preparation method thereof. The DDR module packaging structure provided by the invention comprises a plurality of DDR chip sets which are arranged on the same layer; the DDR chip set comprises a plurality of DDR chips which are arranged in a stacked manner; the packaging layer is used for coating each DDR chip set; the IPD wafer is arranged on one side of the packaging layer; at least an IPD chip is arranged in the IPD wafer; the IVR chip is arranged on the other side of the packaging layer; the IVR chip is electrically connected with the IPD wafer; a part of the DDR chip is electrically connected with the IPD chip; and a part of the DDR chip is electrically connected with the IVR chip.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device packaging, and in particular to a DDR module packaging structure and a preparation method thereof. Background Art

[0002] As AI is developing rapidly in application scenarios such as PCs, mobile terminals, and small aircraft, the market demand for smaller, lower power consumption, and higher performance memory chips is becoming increasingly urgent. In the operation of memory chips, power modules and passive devices are required to provide stable power and pull-up voltage to DDR chips. The common power modules and passive device integrated transmission paths are long, and the power supply and signal integrity need to be further improved. The IPD wafer contains passive devices such as IPD chips, resistors, and capacitors, which can be used for pull-up and filtering noise reduction of DDR chip address lines and control lines. It is also commonly used in DDR chip stacking integration solutions. Shortening the transmission distance of the integrated power regulator IVR (Integrated Voltage Regulator) chip, passive devices, DDR chips, and IPD chips is an important way to reduce VCC noise, improve crosstalk and return loss, and thus improve power integrity and signal integrity.

[0003] Most of the existing DDR chip stacking integration solutions are board-mounted. The integration of DDR chips, passive devices, and IVR is not high, and the transmission distance is long. Correspondingly, there will be problems such as poor signal and power integrity. Specifically, the signal transmission will deviate from its original characteristics such as amplitude, phase, and waveform due to the impedance, delay reflection, and crosstalk of the transmission line. The power supply will also be affected by various factors, causing the current provided to be poorly stable and contain noise. In addition, the DDR module packaging based on board-mounting also has defects such as inflexible substrate design, long process cycle, and high cost. Therefore, a solution is needed to improve the integration of DDR chips, passive devices, and IVR chips, and to achieve the purpose of improving design flexibility, shortening production cycle, and reducing manufacturing costs. Summary of the invention

[0004] Therefore, the present invention provides a DDR module packaging structure and a preparation method thereof to solve the problems of low integration of DDR chips, passive devices and IVR in existing memory chip integration solutions, and low signal and power integrity due to long transmission distance. At the same time, the defects of inflexible substrate design, long process cycle and high cost in existing integrated technology are improved.

[0005] The present invention provides a DDR module packaging structure, comprising: a plurality of DDR chipsets arranged in the same layer; the DDR chipsets comprising a plurality of DDR chips arranged in a stacked manner; a packaging layer covering each of the DDR chipsets; an IPD wafer arranged on one side of the packaging layer; at least an IPD chip is arranged in the IPD wafer; an IVR chip arranged on the other side of the packaging layer; the IVR chip is electrically connected to the IPD wafer; some of the DDR chips are electrically connected to the IPD chip; and some of the DDR chips are electrically connected to the IVR chip.

[0006] Optionally, the DDR module packaging structure also includes a redistribution layer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the redistribution layer is located between the IVR chip and the packaging layer; the DDR chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; the IPD chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; the DDR chip electrically connected to the IPD chip is connected to the IPD chip through the redistribution layer.

[0007] Optionally, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected via a connecting wire; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting wire.

[0008] Optionally, in each of the DDR chipsets, the DDR chips are the same; each of the DDR chips is directly or indirectly connected to the IVR chip, and is directly or indirectly connected to the IPD chip.

[0009] Optionally, the DDR module packaging structure further includes: a solder ball, which is arranged on a side of the redistribution layer facing away from the packaging layer, connected to the metal wiring layer, and arranged in the same layer as the IVR chip.

[0010] Optionally, there are two groups of DDR chips, each group includes four DDR chips; and the IVR chip is located between the two corresponding groups of DDR chips.

[0011] The present invention also provides a method for preparing a DDR module packaging structure, comprising the following steps: providing an IPD wafer, wherein the IPD wafer is provided with at least an IPD chip; forming multiple groups of DDR chipsets on the IPD wafer; arranging the DDR chipsets on the same layer; arranging connecting wires of the DDR chips and the connecting wires of the IPD chips; forming a packaging layer, wherein the packaging layer covers the DDR chipsets and the connecting wires; mounting an IVR chip, which is located on the opposite side of the packaging layer relative to the IPD wafer and is connected to the connecting wires.

[0012] Optionally, after forming the packaging layer and before mounting the IVR chip, it also includes: forming a redistribution layer, which is located on the opposite side of the packaging layer relative to the IPD wafer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the connecting lines; the IVR chip is mounted on the side of the redistribution layer facing away from the IPD wafer, and is connected to the metal wiring layer in the redistribution layer.

[0013] Optionally, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected through a connecting wire; the IPD chip is connected to the metal wiring layer in the redistribution layer through a connecting wire; in each of the DDR chipsets, at least one of the DDR chips is connected to the IVR chip, and at least one of the DDR chips is connected to the IPD chip.

[0014] Optionally, before forming the redistribution layer, it also includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the DDR chip on the outermost layer and the ends of each connecting line; before mounting the IVR chip, it also includes: forming solder balls, wherein the solder balls are formed on the surface of the redistribution layer facing away from the IPD wafer and connected to the metal wiring layer; and the solder balls reserve a preset installation area for the IVR chip; and the IVR chip is mounted in the preset installation area.

[0015] The technical solution of the present invention has the following advantages:

[0016] The DDR module packaging structure provided by the present invention integrates the DDR chipset, IPD chip and IVR chip into one module, thereby improving the overall integration of the module, reducing the transmission distance between the components in the module, improving crosstalk and return loss, and reducing PDN impedance to improve the integrity of the signal and power supply. The IVR chip can provide a stable and clean power supply for the DDR chip and the IPD chip, and the IPD chip provides a pull-up voltage for the address line and control line of the DDR chip. After reducing the interconnection distance between the DDR chip, the IPD chip and the IVR chip, the transmission distance can be reduced, the crosstalk and return loss can be improved, and the PDN impedance can be reduced to improve the integrity of the signal and power supply.

[0017] The preparation method of the DDR module packaging structure provided by the present invention can prepare the DDR module packaging structure provided by the present invention. The DDR chipset, IPD chip and IVR chip are integrated into one module, which improves the overall integration of the module, reduces the transmission distance between the components in the module, improves crosstalk and return loss, and reduces PDN impedance to improve the integrity of the signal and power supply. Among them, the IVR chip can provide a stable and clean power supply for the DDR chip and the IPD chip, and the IPD chip provides a pull-up voltage for the address line and control line of the DDR chip. After reducing the interconnection distance between the DDR chip, the IPD chip and the IVR chip, the transmission distance can be reduced, the crosstalk and return loss can be improved, and the PDN impedance can be reduced to improve the integrity of the signal and power supply.

[0018] In addition, the DDR module packaging structure and manufacturing method provided by the present invention are based on the wafer-level fan-out packaging process, and the packaging is directly implemented on the IPD (Integrated Passive Device) wafer. Compared with the traditional DDR storage module, no substrate is required, which shortens the production cycle and reduces costs. Compared with the conventional fan-out packaging technology, the temporary carrier bonding process is omitted, further simplifying the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a DDR module packaging structure according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a system framework of a DDR module packaging structure according to an embodiment of the present invention;

[0022] Figure 3-Figure 11 It is a schematic diagram of various states in a specific process of a method for preparing a DDR module packaging structure according to an embodiment of the present invention.

[0023] Description of reference numerals:

[0024] 100-IPD wafer; 210, 220-DDR chipset; 211, 212, 213, 214, 221, 222, 223, 224-DDR chips; 300-packaging layer; 400-IVR chip; 500-rewiring layer; 600-solder balls. DETAILED DESCRIPTION

[0025] In order to solve the problems of low integration of DDR chips, passive devices and IVR in existing memory chip integration solutions, low signal and power integrity due to long transmission distance, and to improve the defects of inflexible substrate design, long process cycle and high cost of existing integration technology, the present invention provides a DDR module packaging structure and a preparation method thereof.

[0026] The technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In the description of the present invention, it should be noted that the terms "first", "second" and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0027] Example 1

[0028] refer to Figure 1 and Figure 2 , this embodiment provides a DDR module packaging structure, including:

[0029] Multiple DDR chipsets are arranged in the same layer; for example, in this embodiment, they include DDR chipsets 210 and 220.

[0030] The DDR chipset includes a plurality of DDR chips stacked in layers. For example, in this embodiment, the DDR chipset 210 includes a plurality of DDR chips 211 , 212 , 213 , and 214 ; the DDR chipset 220 includes a plurality of DDR chips 221 , 222 , 223 , and 224 .

[0031] The encapsulation layer encapsulates the DDR chipsets. In this embodiment, the encapsulation layer 300 encapsulates the DDR chipsets 210 and 220 .

[0032] The IPD wafer is disposed on one side of the packaging layer; the IPD wafer is provided with at least an IPD chip; in this embodiment, the IPD wafer 100 is disposed on one side of the packaging layer 300, and the IPD wafer 100 is provided with at least an IPD chip (not shown in the figure). In some embodiments, passive devices such as capacitors and resistors may also be provided (passive devices are not shown in the figure).

[0033] The IVR chip is disposed on the other side of the packaging layer; the IVR chip is electrically connected to the IPD wafer. In this embodiment, the IVR chip 400 is disposed on the other side of the packaging layer 300 and is electrically connected to the IPD wafer 100.

[0034] Some of the DDR chips are electrically connected to the IPD chip; some of the DDR chips are electrically connected to the IVR chip. Figure 1 As shown, some of the DDR chips 211, 212, 213, 214 and 221, 222, 223, 224 are electrically connected to the IVR chip 400, and some are electrically connected to the IPD wafer 100 and the IPD chips therein.

[0035] The schematic diagram of the system framework of a DDR chipset of the DDR module packaging structure of this embodiment is shown in FIG. Figure 2 The clocks of each chip are interconnected internally, using a Fly-by topology; the IVR chip provides power for the DDR chip and the IPD chip; the IPD chip provides pull-up for the address line and control line of the DDR chip, using the DDR protocol. Figure 2 The figure also shows the internal signal grouping of each DDR chip in a DDR chipset according to the definition of the Fly-by topology structure.

[0036] The DDR module packaging structure provided in this embodiment integrates the DDR chipset, IPD chip and IVR chip into one module, thereby improving the overall integration of the module, reducing the transmission distance between the components in the module, improving crosstalk and return loss, and reducing PDN impedance to improve the integrity of the signal and power supply. The IVR chip can provide a stable and clean power supply for the DDR chip and the IPD chip, and the IPD chip provides a pull-up voltage for the address line and control line of the DDR chip. After reducing the interconnection distance between the DDR chip, the IPD chip and the IVR chip, the transmission distance can be reduced, the crosstalk and return loss can be improved, and the PDN impedance can be reduced to improve the integrity of the signal and power supply.

[0037] In addition, the DDR module packaging structure provided in this embodiment can be directly packaged on an IPD (Integrated Passive Device) wafer based on a wafer-level fan-out packaging process. Compared with the traditional DDR storage module, no substrate is required, which shortens the production cycle and reduces costs. Compared with conventional fan-out packaging technology, the temporary carrier bonding process is omitted, further simplifying the production process.

[0038] Furthermore, the DDR module packaging structure of this embodiment also includes:

[0039] Rewiring layer 500; the rewiring layer 500 includes a metal wiring layer (the black line portion in the area 500 in the figure) and an insulating isolation layer covering the metal wiring layer (the portion covering the black line in the area 500 in the figure); the rewiring layer 500 is located between the IVR chip 400 and the packaging layer 300; the DDR chip electrically connected to the IVR chip 400 is connected to the IVR chip 400 through the rewiring layer 500; the IPD chip electrically connected to the IVR chip 400 is connected to the IVR chip 400 through the rewiring layer 500; the DDR chip electrically connected to the IPD chip is connected to the IPD chip through the rewiring layer 500. That is, the rewiring layer 500 serves as a transfer for connecting the various chips to realize the connection between the various chips.

[0040] Furthermore, in this embodiment, the DDR chips in the DDR chipset are stacked in a staggered manner, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected via a connecting wire; the IPD chip is connected to the metal wiring layer in the redistribution layer via a connecting wire. Figure 1 As shown, some DDR chips (such as 214 and 224) are directly connected to the metal wiring layer in the redistribution layer 500; another part of the DDR chips (such as 211, 212, 213, 221, 222, and 223) are connected to the metal wiring layer in the redistribution layer 500 through connecting wires. The IPD chip is connected to the metal wiring layer in the redistribution layer 500 through connecting wires. In some embodiments, these connecting wires are metal pillars or hard wires made of other conductive materials.

[0041] Furthermore, in this embodiment, in each of the DDR chipsets, each of the DDR chips is the same; each of the DDR chips is directly or indirectly connected to the IVR chip, and is directly or indirectly connected to the IPD chip. In this way, it is ensured that the IVR chip can provide a stable and clean power supply for the DDR chip and the IPD chip, and the IPD chip provides a pull-up voltage for the address line and control line of the DDR chip.

[0042] Furthermore, in this embodiment, the DDR module packaging structure further includes: a solder ball 600, which is arranged on the side of the redistribution layer 500 facing away from the packaging layer 300, connected to the metal wiring layer, and arranged in the same layer as the IVR chip. The IVR chip 400 is arranged in the gap between the solder balls 600, which is separated from the IPD wafer and the DDR chipset on the one hand, and does not need to be arranged separately outside the packaging module, thereby shortening the distance between the IPD chip and the DDR chip.

[0043] Specifically, in this embodiment, there are two groups of DDR chipsets, each group contains four DDR chips; and the IVR chip is located between the two corresponding groups of DDR chipsets.

[0044] Example 2

[0045] This embodiment provides a method for preparing a DDR module packaging structure to prepare the DDR module packaging structure provided in the above embodiment 1. Figure 3-Figure 11 , including the following steps:

[0046] refer to Figure 3 , providing an IPD wafer, wherein the IPD wafer is provided with at least an IPD chip;

[0047] refer to Figure 4 , forming a plurality of DDR chipsets on the IPD wafer; each of the DDR chipsets is arranged on the same layer;

[0048] refer to Figure 5 , setting connection lines of each of the DDR chips and connection lines of the IPD chip;

[0049] refer to Figure 6 , forming a packaging layer, wherein the packaging layer covers each of the DDR chipsets and each of the connecting wires;

[0050] refer to Fig.10 , mounting an IVR chip, which is located on the opposite side of the packaging layer relative to the IPD wafer, and is connected to each of the connecting wires.

[0051] refer to Fig.11 , and finally the wafer is cut to form a single packaging structure.

[0052] The preparation method of the DDR module packaging structure provided in this embodiment can prepare the DDR module packaging structure provided by the present invention. The DDR chipset, IPD chip and IVR chip are integrated into one module, which improves the overall integration of the module, reduces the transmission distance between the components in the module, improves crosstalk and return loss, and reduces PDN impedance to improve the integrity of the signal and power supply. Among them, the IVR chip can provide a stable and clean power supply for the DDR chip and the IPD chip, and the IPD chip provides a pull-up voltage for the address line and control line of the DDR chip. After reducing the interconnection distance between the DDR chip, the IPD chip and the IVR chip, the transmission distance can be reduced, the crosstalk and return loss can be improved, and the PDN impedance can be reduced to improve the integrity of the signal and power supply.

[0053] In addition, the preparation method of the DDR module packaging structure provided in this embodiment can be directly packaged on an IPD (Integrated Passive Device) wafer based on a wafer-level fan-out packaging process. Compared with the traditional DDR storage module, no substrate is required, which shortens the production cycle and reduces costs. Compared with conventional fan-out packaging technology, the temporary carrier bonding process is omitted, further simplifying the production process.

[0054] For further reference, Fig. 9 After forming the packaging layer and before mounting the IVR chip, it also includes: forming a redistribution layer, which is located on the opposite side of the packaging layer relative to the IPD wafer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the connecting wires; the IVR chip is mounted on the side of the redistribution layer facing away from the IPD wafer, and is connected to the metal wiring layer in the redistribution layer.

[0055] Furthermore, the DDR chips in the DDR chipset are staggered and stacked, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected through a connecting wire; the IPD chip is connected to the metal wiring layer in the redistribution layer through a connecting wire; in each of the DDR chipsets, at least one of the DDR chips is connected to the IVR chip, and at least one of the DDR chips is connected to the IPD chip.

[0056] For further reference, Figure 7 , Figure 8 , before forming the redistribution layer, it also includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the DDR chip on the outermost layer and the ends of each of the connecting wires;

[0057] refer to Fig. 9Before mounting the IVR chip, it also includes: forming solder balls, wherein the solder balls are formed on the surface of the redistribution layer facing away from the IPD wafer to connect the metal wiring layer; and the solder balls reserve a preset installation area for the IVR chip; and the IVR chip is mounted in the preset installation area.

[0058] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the invention.

Claims

1. A DDR module packaging structure, It is characterized in that include: Multiple groups of DDR chipsets arranged in the same layer; the DDR chipsets include multiple DDR chips arranged in a stacked manner; A packaging layer, covering each of the DDR chipsets; An IPD wafer is arranged on one side of the packaging layer; the IPD wafer is provided with at least an IPD chip; An IVR chip is disposed on the other side of the packaging layer; The IVR chip is electrically connected to the IPD wafer; Some of the DDR chips are electrically connected to the IPD chip; some of the DDR chips are electrically connected to the IVR chip.

2. The DDR module packaging structure according to claim 1, It is characterized in that Also includes a redistribution layer; the redistribution layer includes a metal wiring layer and an insulating isolation layer covering the metal wiring layer; The redistribution layer is located between the IVR chip and the packaging layer; The DDR chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; The IPD chip electrically connected to the IVR chip is connected to the IVR chip through the redistribution layer; The DDR chip electrically connected to the IPD chip is connected to the IPD chip through the redistribution layer.

3. The DDR module packaging structure according to claim 2, It is characterized in that The DDR chips in the DDR chipset are arranged in a staggered stack, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected through a connecting line; The IPD chip is connected to the metal wiring layer in the redistribution layer through a connecting wire.

4. The DDR module packaging structure according to claim 3, It is characterized in that In each of the DDR chipsets, the DDR chips are identical; each of the DDR chips is directly or indirectly connected to the IVR chip, and is directly or indirectly connected to the IPD chip.

5. The DDR module packaging structure according to claim 3, It is characterized in that Also includes: The solder ball is arranged on the side of the redistribution layer facing away from the packaging layer, connected to the metal wiring layer, and arranged in the same layer as the IVR chip.

6. The DDR module packaging structure according to claim 3, It is characterized in that There are two DDR chipsets, and each group contains four DDR chips; The IVR chip is located between two corresponding groups of DDR chipsets.

7. A method for preparing a DDR module packaging structure, It is characterized in that The following steps are involved: Providing an IPD wafer, wherein the IPD wafer is provided with at least an IPD chip; forming a plurality of DDR chipsets on the IPD wafer; Each of the DDR chipsets is arranged in the same layer; Setting connection lines of the DDR chips and the IPD chips; Forming a packaging layer, wherein the packaging layer covers each of the DDR chipsets and each of the connecting wires; The IVR chip is mounted on the opposite side of the packaging layer to the IPD wafer and is connected to each of the connection lines.

8. The method for preparing the DDR module packaging structure according to claim 7, It is characterized in that After forming the encapsulation layer and before mounting the IVR chip, it also includes: forming a redistribution layer located on the opposite side of the packaging layer to the IPD wafer; the redistribution layer comprises a metal wiring layer and an insulating isolation layer covering the metal wiring layer; the metal wiring layer is connected to each of the connecting wires; The IVR chip is mounted on the side of the redistribution layer facing away from the IPD wafer and is connected to the metal wiring layer in the redistribution layer.

9. The method for preparing the DDR module packaging structure according to claim 8, It is characterized in that The DDR chips in the DDR chipset are arranged in a staggered stack, and each DDR chip is directly connected to the metal wiring layer in the redistribution layer or connected through a connecting line; The IPD chip is connected to the metal wiring layer in the redistribution layer through a connecting wire; In each of the DDR chipsets, at least one of the DDR chips is connected to the IVR chip, and at least one of the DDR chips is connected to the IPD chip.

10. The method for preparing the DDR module packaging structure according to claim 8, It is characterized in that Before forming the redistribution layer, the method further includes: thinning the IPD wafer; thinning the packaging layer to expose the pins of the DDR chip on the outermost layer and the ends of each of the connecting wires; Before mounting the IVR chip, the method further includes: forming solder balls, the solder balls being formed on the surface of the redistribution layer facing away from the IPD wafer to connect the metal wiring layer; and the solder balls reserving a preset mounting area for the IVR chip; and mounting the IVR chip on the preset mounting area.

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