Deep groove capacitor structure and manufacturing method thereof

Abstract

A deep trench capacitor structure is provided, including a doped region of a substrate having a two-dimensional trench array defined therein, the two-dimensional trench array having a structure shaped like a Chinese character'tian 'formed by a plurality of segments defined therein, each segment having a plurality of grooves; at least one layer of polycrystalline silicon conductive layer structure is arranged in the groove; the metal electrode structure is formed on the polycrystalline silicon conducting layer structure and comprises a barrier layer and a filling metal layer formed on the barrier layer; the residual groove is filled with the electrode dielectric layer, and an air gap is formed in the electrode dielectric layer; the interlayer dielectric layer covers the electrode dielectric layer, the polycrystalline silicon conducting layer structure and the metal electrode structure; and a plurality of contact windows respectively connected to an exposed top surface of the required polycrystalline silicon conductive layer structure, an exposed top surface of the metal electrode structure and the doped region of the substrate. The resistivity is reduced, the resistance of the metal electrode and the contact resistance of the contact window are reduced, and the parasitic resistance is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a deep trench capacitor structure and a manufacturing method thereof. Background Art

[0002] It is disclosed in the case with the application number (CN109427753):

[0003] Please refer to Figure 1 , the trench array 808 is centrosymmetric in a cross shape, composed of four trench sections (blocks) 808s. The arrangement directions of adjacent trench sections are perpendicular to each other, and their stresses cancel each other out. The introduction of the air gap 804 further reduces the strain and significantly reduces the wafer warpage;

[0004] Please refer to Figure 2 , in the prior art, the electrode is filled with polysilicon, and its resistivity is relatively high, and the influence of the air gap load is serious.

[0005] To solve the above problems, a new deep trench capacitor structure and a manufacturing method thereof need to be proposed. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a deep trench capacitor structure and a manufacturing method thereof, which are used to solve the problem that it is difficult to solve stress release in the setting of the trench array and the contact window in the prior art.

[0007] To achieve the above object and other related objects, the present invention provides a deep trench capacitor structure, including:

[0008] A doped region of a substrate, in which a two-dimensional trench array is defined. The two-dimensional trench array has a cross-shaped structure composed of a plurality of sections defined therein, and a plurality of grooves are provided in each of the sections;

[0009] At least one layer of polysilicon conductive layer structure disposed in the grooves;

[0010] A metal electrode structure formed on the polysilicon conductive layer structure. The metal electrode structure includes a barrier layer and a filling metal layer formed on the barrier layer;

[0011] An electrode dielectric layer filling the remaining grooves, and an air gap is formed in the electrode dielectric layer;

[0012] An interlayer dielectric layer covering the electrode dielectric layer, the polysilicon conductive layer structure, and the metal electrode structure;

[0013] A plurality of contact windows, respectively connected to an exposed top surface of the required polysilicon conductive layer structure, an exposed top surface of the metal electrode structure, and the doped region of the substrate.

[0014] Preferably, the polysilicon conductive layer structure includes a polysilicon layer.

[0015] Preferably, the polysilicon conductive layer structure further comprises a dielectric layer between the polysilicon layer and the substrate or a dielectric layer between the polysilicon layers according to capacitance density.

[0016] Preferably, the dielectric layer comprises oxide / nitride / oxide.

[0017] Preferably, edge portions of the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure are stepped structures.

[0018] Preferably, a side wall is formed on the side wall of the stepped structure.

[0019] Preferably, the material of the barrier layer includes titanium and titanium nitride.

[0020] Preferably, the material of the filling metal layer is tungsten.

[0021] The present invention also provides a method for manufacturing the above-mentioned deep trench capacitor structure, comprising:

[0022] Step 1, forming a two-dimensional groove array in a doping region of a substrate, wherein the two-dimensional groove array has a field-shaped structure consisting of a plurality of sections defined therein, and a plurality of grooves are disposed in each of the sections;

[0023] Step 2, forming at least one layer of polysilicon conductive layer structure in the groove;

[0024] forming a metal electrode structure on the polysilicon conductive layer structure, wherein the metal electrode structure comprises a barrier layer and a filling metal layer formed on the barrier layer;

[0025] forming an electrode dielectric layer filling the remaining groove, wherein an air gap is formed in the electrode dielectric layer;

[0026] forming an interlayer dielectric layer covering the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure;

[0027] Step three, forming a plurality of contact windows on the interlayer dielectric layer, which are respectively connected to an exposed top surface of the desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure, and the doped region of the substrate.

[0028] Preferably, the polysilicon conductive layer structure in step 2 comprises a polysilicon layer.

[0029] Preferably, the polysilicon conductive layer structure in step 2 further includes a dielectric layer between the polysilicon layer and the substrate or a dielectric layer between the polysilicon layer and the polysilicon layer according to capacitance density.

[0030] Preferably, the dielectric layer in step 2 comprises oxide / nitride / oxide.

[0031] Preferably, in step 2, edge portions of the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure are stepped structures.

[0032] Preferably, a side wall is formed on the side wall of the stepped structure in step 2.

[0033] Preferably, the material of the barrier layer in step 2 includes titanium and titanium nitride.

[0034] Preferably, the material of the filling metal layer in step 2 is tungsten.

[0035] As described above, the deep trench capacitor structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0036] Compared with the traditional polysilicon process, the present invention reduces the resistivity, reduces the resistance of the metal electrode itself and the contact resistance of the contact window, thereby reducing the parasitic resistance, has no air gap load effect, and can also omit the step of forming metal silicide, avoiding the leakage problem caused by the formation of metal silicide between the layers of the multilayer mechanism. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 Shown is a layout of a trench array and a contact window in the prior art and a schematic diagram of a cross-sectional structure of a device;

[0038] Figure 2 The schematic diagram of the prior art electrode filled with polysilicon is shown;

[0039] Figure 3 Shown is a schematic diagram of a groove array of the present invention;

[0040] Figure 4 A schematic diagram showing a cross-sectional structure of a groove array of the present invention;

[0041] Figure 5 Shown is a schematic diagram of the deep trench capacitor structure of the present invention;

[0042] Figure 6 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present disclosure. The specific elements and their arrangements are described below to illustrate the embodiments of the present disclosure. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present disclosure should not be limited thereto. For example, it is mentioned in the specification that the first feature is formed on the second feature, which includes an embodiment in which the first feature and the second feature are in direct contact, and also includes an embodiment in which there are other features between the first feature and the second feature, that is, the first feature and the second feature are not in direct contact. In addition, the embodiments of the present disclosure may repeat the figure marks and / or letters in various examples. The above repetition is for the purpose of simplicity and clarity, and is not used to limit the relationship between the various embodiments and / or configurations discussed.

[0046] In addition, spatially relative terms may be used, such as "below", "below", "lower", "above", "higher" and similar terms. These spatially relative terms are used to facilitate the description of the relationship between one (some) element or feature and another (some) element or feature in the figure. These spatially relative terms include different orientations of the device in use or operation, as well as the orientations described in the drawings. When the device is turned to a different orientation (rotated 90 degrees or other orientations), the spatially relative adjectives used therein will also be interpreted according to the turned orientation.

[0047] It should also be noted that the embodiments of the present disclosure are described in terms of trench capacitor structures that may be included in an integrated circuit (e.g., a microprocessor, a memory device, and / or some other integrated circuit). Such integrated circuits may also include various passive and active microelectronic devices, such as resistors, other types of capacitors (e.g., metal-insulator-metal capacitors (MIMCAPs)), inductors, diodes, metal-oxide-semiconductor field effect transistors (MOSFETs), complementary metal-oxide-semiconductor field effect transistors (CMOS transistors), bipolar junction transistors (BJTs), laterally diffused MOS transistors (LDMOS), high power MOS transistors, or other types of transistors. One of ordinary skill in the art will recognize other embodiments of semiconductor devices that may benefit from various aspects of the present disclosure.

[0048] See also Figure 5 The present invention provides a deep trench capacitor structure, comprising:

[0049] A doping region 102 of a substrate 101 has a two-dimensional groove array defined therein, wherein the two-dimensional groove array has a zigzag structure consisting of a plurality of sections defined therein, and a plurality of grooves are disposed in each section;

[0050] The substrate 101 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a III-V substrate, or some other semiconductor substrates.

[0051] The number of grooves in each section can be the same or different, and the arrangement direction in each section can also be adjusted according to actual needs. For example, see Figure 3 , the two-dimensional groove array is formed into a windmill shape.

[0052] A cross section of the groove Figure 4 As shown, a low-resistance doping region 102 is formed by diffusion doping;

[0053] Each section basically has the same groove cross-sectional structure, but there are differences in whether the contact holes are connected to the electrode steps of each layer around it.

[0054] At least one polysilicon conductive layer structure is disposed in the groove; and

[0055] In some embodiments, the polysilicon conductive layer structure includes a polysilicon layer.

[0056] In some embodiments, the polysilicon conductive layer structure further includes a dielectric layer between the polysilicon layer and the substrate 101 or a dielectric layer between the polysilicon layer and the polysilicon layer according to the capacitance density. Figure 5 In the case where the polysilicon conductive layer structure is a first polysilicon conductive layer 103 and a second polysilicon conductive layer 104 stacked in sequence, one dielectric layer or two dielectric layers may be formed according to the requirements of capacitance density.

[0057] In some embodiments, the dielectric layer includes oxide / nitride / oxide.

[0058] A metal electrode structure 105 formed on the polysilicon conductive layer structure, wherein the metal electrode structure 105 includes a barrier layer and a filling metal layer formed on the barrier layer;

[0059] The electrode dielectric layer 106 fills the remaining grooves. The material of the electrode dielectric layer 106 may be an oxide layer. An air gap 107 is formed in the electrode dielectric layer 106. The stress of the substrate 101 (such as a wafer) can be released after subsequent steps. The metal layer does not need to fill the grooves. Then, a layer of electrode dielectric layer 106 is deposited to form an air gap 107 at the center. The highest height of the air gap 107 cannot exceed the height of the metal electrode structure 105.

[0060] In some embodiments, edge portions of the electrode dielectric layer 106 , the polysilicon conductive layer structure, and the metal electrode structure 105 are stepped structures.

[0061] In some embodiments, a spacer 108 is formed on the sidewall of the stepped structure.

[0062] An interlayer dielectric layer 109 covering the electrode dielectric layer 106, the polysilicon conductive layer structure and the metal electrode structure 105;

[0063] In some embodiments, the material of the barrier layer includes titanium and titanium nitride.

[0064] In some embodiments, the material of the filling metal layer is tungsten.

[0065] A plurality of contact windows 110 are respectively connected to an exposed top surface of a desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure 105 , and the doped region 102 of the substrate 101 .

[0066] For example, some methods of forming trench capacitors include forming a two-dimensional array of trenches in a substrate 101 (e.g., a wafer). A plurality of stacked polysilicon conductive layer structures and metal electrode structures 105 are formed to cover the substrate 101 and completely fill the array of trenches. In addition, the polysilicon conductive layer structures and metal electrode structures 105 are vertically stacked and each conductive layer is lined with the trenches. The electrodes are patterned sequentially from the top of the metal electrode structure 105 stack to the bottom of the polysilicon conductive layer structure stack. An inter-layer dielectric layer 109 is formed to cover the substrate 101 and the electrode stack, and chemical-mechanical polish (CMP) is performed to the top of the inter-layer dielectric layer. Contact vias are formed that pass through the inter-layer dielectric layer and extend to the electrodes.

[0067] Contact windows 110 are formed by etching and filling contact holes to connect the electrodes respectively. Since the contact resistance between the contact string and the metal electrode structure 105 is low, the step of forming metal silicide can be omitted, and the subsequent process continues to form the necessary metal / via / passivation layer layers.

[0068] In other embodiments of the present invention, the number of gate polysilicon layers may not be limited to two layers, and the pattern arrangement of each contact window 110 / polysilicon layer / metal electrode structure 105 may be changed accordingly.

[0069] See also Figure 6 The present invention also provides a method for manufacturing the above-mentioned deep trench capacitor structure, comprising:

[0070] Step 1: forming a two-dimensional groove array in a doping region 102 of a substrate 101, wherein the two-dimensional groove array has a zigzag structure consisting of a plurality of sections defined therein, and a plurality of grooves are disposed in each section;

[0071] The substrate 101 may be a bulk silicon substrate 101 , a silicon-on-insulator (SOI) substrate 101 , a III-V substrate 101 , or some other semiconductor substrate 101 .

[0072] The number of grooves in each section can be the same or different, and the arrangement direction in each section can also be adjusted according to actual needs. For example, see Figure 3 , the two-dimensional groove array is formed into a windmill shape.

[0073] A cross section of the groove Figure 4 As shown, a low-resistance doping region 102 is formed by diffusion doping;

[0074] Each section basically has the same groove cross-sectional structure, but there are differences in whether the contact holes are connected to the electrode steps of each layer around it.

[0075] Step 2: forming at least one layer of polysilicon conductive layer structure in the groove;

[0076] forming a metal electrode structure 105 on the polysilicon conductive layer structure, wherein the metal electrode structure 105 comprises a barrier layer and a filling metal layer formed on the barrier layer;

[0077] An electrode dielectric layer 106 is formed to fill the remaining groove. The material of the electrode dielectric layer 106 may be an oxide layer. An air gap 107 is formed in the electrode dielectric layer 106.

[0078] forming an interlayer dielectric layer 109 covering the electrode dielectric layer 106, the polysilicon conductive layer structure and the metal electrode structure 105;

[0079] In some embodiments, the polysilicon conductive layer structure in step 2 includes a polysilicon layer.

[0080] In some embodiments, the polysilicon conductive layer structure in step 2 further includes a dielectric layer between the polysilicon layer and the substrate 101 or a dielectric layer between the polysilicon layer and the polysilicon layer according to the capacitance density. Figure 5 In the case where the polysilicon conductive layer structure is a first polysilicon conductive layer 103 and a second polysilicon conductive layer 104 stacked in sequence, one dielectric layer or two dielectric layers may be formed according to the requirements of capacitance density.

[0081] In some embodiments, the dielectric layer in step 2 includes oxide / nitride / oxide.

[0082] In some embodiments, the edge portions of the electrode dielectric layer 106 , the polysilicon conductive layer structure, and the metal electrode structure 105 in step 2 are stepped structures.

[0083] In some embodiments, a sidewall spacer 108 is formed on the sidewall of the stepped structure in step 2.

[0084] In some embodiments, the material of the barrier layer in step 2 includes titanium and titanium nitride.

[0085] In some embodiments, the material of the filling metal layer in step 2 is tungsten.

[0086] Step 3: forming a plurality of contact windows 110 on the interlayer dielectric layer 109 , which are respectively connected to an exposed top surface of the desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure 105 , and the doped region 102 of the substrate 101 .

[0087] For example, some methods of forming trench capacitors include forming a two-dimensional array of trenches in a substrate 101 (e.g., a wafer). A plurality of stacked polysilicon conductive layer structures and metal electrode structures 105 are formed to cover the substrate 101 and completely fill the array of trenches. In addition, the polysilicon conductive layer structures and metal electrode structures 105 are vertically stacked and each conductive layer is lined with the trenches. The electrodes are patterned sequentially from the top of the metal electrode structure 105 stack to the bottom of the polysilicon conductive layer structure stack. An inter-layer dielectric layer 109 is formed to cover the substrate 101 and the electrode stack, and chemical-mechanical polish (CMP) is performed to the top of the inter-layer dielectric layer. Contact vias are formed that pass through the inter-layer dielectric layer and extend to the electrodes.

[0088] Contact windows 110 are formed by etching and filling contact holes to connect the electrodes respectively. Since the contact resistance between the contact string and the metal electrode structure 105 is low, the step of forming metal silicide can be omitted, and the subsequent process continues to form the necessary metal / via / passivation layer layers.

[0089] In other embodiments of the present invention, the number of gate polysilicon layers may not be limited to two layers, and the pattern arrangement of each contact window 110 / polysilicon layer / metal electrode structure 105 may be changed accordingly.

[0090] In summary, compared with the traditional polysilicon process, the present invention has a lower resistivity, reduces the resistance of the metal electrode itself and the contact window contact resistance, thereby reducing the parasitic resistance, has no air gap load effect, and can also omit the step of forming metal silicide, avoiding the leakage problem caused by the formation of metal silicide between the layers of the multilayer mechanism. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0091] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A deep trench capacitor structure, It is characterized in that include: A doping region of a substrate has a two-dimensional groove array defined therein, wherein the two-dimensional groove array has a field-shaped structure consisting of a plurality of sections defined therein, and a plurality of grooves are disposed in each of the sections; At least one polysilicon conductive layer structure is disposed in the groove; A metal electrode structure formed on the polysilicon conductive layer structure, the metal electrode structure comprising a barrier layer and a filling metal layer formed on the barrier layer; An electrode dielectric layer filling the remaining groove, wherein an air gap is formed in the electrode dielectric layer; An interlayer dielectric layer covering the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure; A plurality of contact windows are respectively connected to an exposed top surface of the required polysilicon conductive layer structure, an exposed top surface of the metal electrode structure, and the doped region of the substrate.

2. The deep trench capacitor structure according to claim 1, Features: The polysilicon conductive layer structure includes a polysilicon layer.

3. The deep trench capacitor structure according to claim 1, Features: The polysilicon conductive layer structure further includes a dielectric layer between the polysilicon layer and the substrate or a dielectric layer between the polysilicon layer and the polysilicon layer according to capacitance density.

4. The deep trench capacitor structure according to claim 3, Features: The dielectric layer includes oxide / nitride / oxide.

5. The deep trench capacitor structure according to claim 1, Features: The edge portions of the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure are step-shaped structures.

6. The deep trench capacitor structure according to claim 1, Features: A side wall is formed on the side wall of the stepped structure.

7. The deep trench capacitor structure according to claim 3, Features: The material of the barrier layer includes titanium and titanium nitride.

8. The deep trench capacitor structure according to claim 3, Features: The material of the filling metal layer is tungsten.

9. The method for manufacturing a deep trench capacitor structure according to any one of claims 1 to 8, It is characterized in that include: Step 1, forming a two-dimensional groove array in a doping region of a substrate, wherein the two-dimensional groove array has a field-shaped structure consisting of a plurality of sections defined therein, and a plurality of grooves are disposed in each of the sections; Step 2, forming at least one layer of polysilicon conductive layer structure in the groove; forming a metal electrode structure on the polysilicon conductive layer structure, wherein the metal electrode structure comprises a barrier layer and a filling metal layer formed on the barrier layer; forming an electrode dielectric layer filling the remaining groove, wherein an air gap is formed in the electrode dielectric layer; forming an interlayer dielectric layer covering the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure; Step three, forming a plurality of contact windows on the interlayer dielectric layer, which are respectively connected to an exposed top surface of the desired polysilicon conductive layer structure, an exposed top surface of the metal electrode structure, and the doped region of the substrate.

10. The method for manufacturing a deep trench capacitor structure according to claim 9, Features: The polysilicon conductive layer structure in step 2 includes a polysilicon layer.

11. The method for manufacturing a deep trench capacitor structure according to claim 9, Features: The polysilicon conductive layer structure in step 2 further includes a dielectric layer between the polysilicon layer and the substrate or a dielectric layer between the polysilicon layer and the polysilicon layer according to the capacitance density.

12. The method for manufacturing a deep trench capacitor structure according to claim 11, Features: The dielectric layer in step 2 includes oxide / nitride / oxide.

13. The method for manufacturing a deep trench capacitor structure according to claim 9, Features: In step 2, the edge portions of the electrode dielectric layer, the polysilicon conductive layer structure and the metal electrode structure are stepped structures.

14. The method for manufacturing a deep trench capacitor structure according to claim 13, Features: In step 2, a side wall is formed on the side wall of the stepped structure.

15. The method for manufacturing a deep trench capacitor structure according to claim 9, Features: The material of the barrier layer in step 2 includes titanium and titanium nitride.

16. The method for manufacturing a deep trench capacitor structure according to claim 9, Features: The material of the filling metal layer in step 2 is tungsten.

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