Method for measuring SiC MOSFET channel near interface trap density

Abstract

The invention relates to a method for measuring the near-interface trap density of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) channel, which belongs to the field of semiconductor device testing and comprises the following steps of: selecting a SiC MOSFET sample; performing standard alternating current capacitance measurement by using a parameter analyzer to test capacitance between the anode and the cathode and the anode; selecting a high reference frequency and a low reference frequency from the frequencies of the plurality of sine waves; the difference between the response charge density at the low reference frequency and the response charge density at the high reference frequency is calculated to determine a near-interface trap density at which the region is active above a threshold. According to the method, the density of the near-interface trap influencing the SiC MOSFET channel performance can be represented in a lossless mode, the test method is simple, data support can be provided for SiC MOSFET performance optimization, the device performance and reliability are improved, a user can be helped to compare and select devices from different manufacturers more conveniently, and the method is suitable for SiC MOSFETs of all structures.

Description

Technical Field

[0001] The invention relates to a method for measuring the near-interface trap density of a SiC MOSFET channel, which is mainly used for non-destructive characterization of the near-interface trap density of SiC MOSFET and belongs to the technical field of semiconductor device testing. Background Art

[0002] Silicon carbide power metal oxide semiconductor field effect transistor (SiC MOSFET) has shown significant advantages in high power and high frequency applications due to its low on-resistance, fast switching speed and low power loss. However, the performance of SiC MOSFET is limited by many factors, among which the channel carrier mobility is a key issue. The interface between SiC and SiO2 is prone to defects during the manufacturing process, such as carbon-containing byproducts, dangling bonds, lattice mismatch, etc. generated during thermal oxidation. These defects induce the formation of near-interface traps, which are difficult to avoid in the process. These traps are located near the SiO2 / SiC interface, capturing and releasing carriers, thereby affecting the overall performance of the MOSFET. Although a large number of studies have focused on these near-interface traps, most of them focus on the trap energy levels below the conduction band. For the trap energy levels aligned with the conduction band energy level and around the Fermi level, the relevant characterization methods and effects of their trap density are not fully understood.

[0003] There are two main types of SiC MOSFET structures: trench structure and planar structure. Compared with the traditional planar structure, the trench structure has a smaller device spacing and higher channel mobility, and its application is becoming more and more extensive. Unlike the planar MOSFET, the evaluation of the trench sidewall of the trench structure and its influence on the channel carriers is complicated. Most of the existing characterization methods are only suitable for planar MOSFETs, not for trench MOSFETs.

[0004] Therefore, developing a method that is applicable to all structures of SiC MOSFET and can accurately measure the channel near-interface trap density is crucial to evaluating and optimizing SiC MOSFET performance. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention provides a method for measuring the near-interface trap density of a SiC MOSFET channel. Based on the capacitance measurement results at different frequencies, the density of near-interface traps that affect the channel performance of the SiC MOSFET can be non-destructively characterized. The test method is simple and applicable to SiC MOSFETs of all structures.

[0006] The present invention adopts the following technical solution: A method for measuring the near-interface trap density of a SiC MOSFET channel comprises the following steps: S1: Select SiC MOSFET samples, which have undergone standard electrical tests to ensure that they can work properly and have good experimental repeatability; S2: Standard AC capacitance measurement using a parameter analyzer: Set the SiC MOSFET sample to be tested to the gate controlled diode (GCD) operating mode to measure the capacitance C between the anode and cathode G ; When testing the capacitor C G During the process, a gate DC voltage bias from -15V to 15V is applied to the gate. , at a specific gate DC voltage bias Under the condition of superimposing a sine wave with an amplitude of 30mV (which can be realized by parameter analyzers with voltage and capacitance test function); the frequency f of the sine wave is multiple, and the capacitance C between the anode and the cathode obtained under multiple different frequencies f is recorded. G ; S3: Selecting a high reference frequency and a low reference frequency from the frequencies f of the multiple sine waves; S4: Calculation of near-interface trap density , the formula is as follows: ; in, Take the gate DC voltage bias Positive value of The capacitance C is obtained by testing at low reference frequency. G ; The capacitance C obtained by testing at high reference frequency G ; represents the integral of the gate DC voltage bias; is the unit charge; is the gate area.

[0007] Preferably, in step S1, the SiC MOSFET sample is a planar MOSFET or a trench MOSFET.

[0008] Preferably, in step S2, the gate-controlled diode working mode is: the drain and source of the SiC MOSFET sample to be tested are short-circuited and grounded together as a cathode, and the gate electrode is tested as an anode.

[0009] Preferably, in step S2, the parameter analyzer is a Keithley parameter analyzer, which is a commonly used parameter analyzer on the market and has voltage and capacitance testing functions.

[0010] Preferably, in step S2, the frequency f of the sine wave is selected to be 1 KHz, 10 KHz, 100 KHz and 1 MHz.

[0011] Preferably, in step S3, 1 MHz is selected as the high reference frequency, and 1 kHz is selected as the low reference frequency.

[0012] For any details not provided in the present invention, please refer to the prior art.

[0013] The beneficial effects of the present invention are: The method of measuring the near-interface trap density of the SiC MOSFET channel of the present invention has simple test conditions and is easy to operate. It is based on the existing standard AC capacitance test and does not require the construction of new test equipment. The method of the present invention does not need to consider the sample shape, electrode position, etc. It only needs to configure the MOSFET to the gate-controlled diode (GCD) working mode, and then test the change of the capacitance at different frequencies at the anode and cathode ends with the bias voltage to complete the test. It can be applied to SiC MOSFETs of all structures, including planar structure, double trench structure, and asymmetric trench structure.

[0014] The method of the present invention is a method for testing traps aligned with the conduction band and around the Fermi level, which can non-destructively characterize the near-interface trap density that affects the channel performance of SiC MOSFET devices. This method provides accurate data support for the performance optimization of SiC MOSFET to improve the performance and reliability of the device. At the same time, the method can also help users more conveniently compare and select SiC MOSFET devices from different manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings in the specification, which constitute a part of the present application, are used to provide further understanding of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0016] Figure 1 It is a schematic diagram of the testing device of the present invention; Figure 2 is the capacitance C at different frequencies in Example 1 G With gate DC voltage bias Schematic diagram of the change curve; Figure 3 is the relationship between the near-interface trap density and the gate DC voltage bias in Example 1 Schematic diagram of the change curve; Figure 4 is the capacitance C at different frequencies in Example 2 G With gate DC voltage bias Schematic diagram of the change curve; Figure 5 is the relationship between the near-interface trap density and the gate DC voltage bias in Example 2 Schematic diagram of the change curve. DETAILED DESCRIPTION

[0017] In order to enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of the present invention are clearly and completely described below in conjunction with the drawings in the implementation of this specification, but are not limited to this. Anything not fully described in the present invention shall be based on the conventional technology in the art.

[0018] Example 1 A method for measuring the near-interface trap density of a SiC MOSFET channel comprises the following steps: S1: Select commercial dual-trench SiC MOSFET samples, which have undergone standard electrical tests to ensure that they can work properly and have good experimental repeatability; S2: Standard AC capacitance measurement using Keithley parameter analyzer: Set the SiC MOSFET sample to be tested to the gate controlled diode (GCD) operating mode to measure the capacitance C between the anode and cathode G ; The working mode of the gate-controlled diode is: the drain and source of the SiC MOSFET sample to be tested are short-circuited and grounded together as the cathode, and the gate electrode is tested as the anode; When testing the capacitor C G During the process, a gate DC voltage bias from -15V to 15V is applied to the gate. , at a specific gate DC voltage bias Under this condition, a sine wave with an amplitude of 30mV is superimposed (this can be achieved by any parameter analyzer with voltage and capacitance test function); the frequency f of the sine wave is selected to be 1KHz, 10KHz, 100KHz and 1MHz. The test device is as follows: Figure 1 As shown, the capacitance C between the anode and the cathode is recorded at different frequencies f. G , the capacitance C is obtained by testing G Follow The change curve of Figure 2 shown.

[0019] S3: The measuring principle of the present invention is: The gate DC voltage bias In the region above the threshold voltage (the threshold voltage can be found in the manual, usually around 3V, the gate DC voltage bias in this embodiment It can reach 15V, which is enough to turn on the device, so the size of the threshold voltage has no effect on the result). Due to the quantum confinement effect, the Fermi level passes through the bottom of the conduction band edge; the trap energy level above the bottom of the conduction band can capture and release electrons from the channel through the electron tunneling mechanism; the reduction in the average density of free inversion layer electrons leads to a reduction in the channel current.

[0020] Since the capacitor CG is the applied gate DC voltage bias function, so the specific Near-interface trapped charges Corresponding to the active gate capacitance: (1); represents the unit charge. According to formula (1), we can get Next ; The response time of near-interface trapped charges depends on the rate at which the traps capture and release carriers. Due to differences in the nature and distribution of the traps, their response times are different. When voltage is applied or operating conditions are changed, the trapped charges respond quickly and affect device performance. Capacitance values ​​measured at high frequencies are smaller because charges with response times longer than 1 / f have little effect on the charge and discharge currents. By comparing the capacitance C measured at different frequencies, G , the effect of near-interface traps on the capacitance can be quantified, thereby deriving the density of traps.

[0021] Due to the small density of traps with response time less than 1 μs, 1 MHz is chosen as the high reference frequency.

[0022] For measurements at frequencies below 1 MHz, traps with response times greater than 1 μs affect the charge and discharge currents, so the capacitance value recorded is greater than the capacitance value at 1 MHz.

[0023] Since the density of traps with response time greater than 1ms is small, 1KHz is selected as the low reference frequency; Only electrons trapped in near-interface traps affect the channel current and degrade the performance of the MOSFET. The near-interface trapped charges at low reference frequencies (use represents) minus the near-interface trap charge at high reference frequency (use Represented) is obtained, as shown in formula (2): (2).

[0024] S4: Calculate the difference in near-interface trap charge at different frequencies and calculate the near-interface trap density , the formula is as follows: (3); in, Take the gate DC voltage bias Positive value of The capacitance C is obtained by testing at low reference frequency. G ; The capacitance C obtained by testing at high reference frequency G ; represents the integral of the gate DC voltage bias; is the unit charge; is the gate area. It can be quantified by calculating the difference between the response charge density at a low reference frequency and the response charge density at a high reference frequency.

[0025] The capacitance C measured at the low reference frequency G ( ) and the capacitance C obtained by testing at high reference frequency G ( ) is substituted into formula (3), and the integrated charge density of the two is obtained by integration. and , take the difference between the two and divide by the unit charge and gate area , It can be obtained by the chip size and cell size of the device. Finally, the active near-interface trap density in the above-threshold region of the channel can be obtained. , the test results are as follows Figure 3 shown.

[0026] Example 2 A method for measuring the near-interface trap density of a SiC MOSFET channel comprises the following steps: S1: Select commercial non-dual trench SiC MOSFET samples. The samples have undergone standard electrical tests to ensure that they can work properly and have good experimental repeatability. S2: Standard AC capacitance measurement using Keithley parameter analyzer: Set the non-dual trench SiC MOSFET sample to be tested in gate controlled diode (GCD) operation mode to test the capacitance C between the anode and cathode G ; The working mode of the gate-controlled diode is: the drain and source of the SiC MOSFET sample to be tested are short-circuited and grounded together as the cathode, and the gate electrode is tested as the anode; When testing the capacitor C G During the process, a gate DC voltage bias from -15V to 15V is applied to the gate. , at a specific gate DC voltage bias Under this condition, a sine wave with an amplitude of 30mV is superimposed (this can be achieved by any parameter analyzer with voltage and capacitance test function); the frequency f of the sine wave is selected to be 1KHz, 10KHz, 100KHz and 1MHz. The test device is as follows: Figure 1 As shown, the capacitance C between the anode and the cathode is recorded at different frequencies f.G , the capacitance C is obtained by testing G Follow The change curve of Figure 4 shown.

[0027] S3: Select 1MHz as the high reference frequency and 1KHz as the low reference frequency; S4: Calculate the near-interface trap density using formula (3) , the active near-interface trap density in the above-threshold region of the channel is obtained , the test results are as follows Figure 5 shown.

[0028] (3); in, Take the gate DC voltage bias Positive value of The capacitance C is obtained by testing at low reference frequency. G ; The capacitance C obtained by testing at high reference frequency G ; represents the integral of the gate DC voltage bias; is the unit charge; is the gate area.

[0029] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for measuring the near-interface trap density of a SiC MOSFET channel, characterized in that: The steps include: S1: Select SiC MOSFET samples, which have undergone standard electrical tests to ensure they can work properly. S2: Standard AC capacitance measurement using a parameter analyzer: Set the SiC MOSFET sample to be tested in gate-controlled diode operation mode to measure the capacitance C between the anode and cathode. G ; When testing the capacitor C G During the process, a gate DC voltage bias from -15V to 15V is applied to the gate. , at a specific gate DC voltage bias Under the condition of superimposing a sine wave with an amplitude of 30mV; the frequency f of the sine wave is multiple, and the capacitance C between the anode and the cathode obtained under multiple different frequencies f is recorded. G ; S3: Selecting a high reference frequency and a low reference frequency from the frequencies f of the multiple sine waves; S4: Calculation of near-interface trap density , the formula is as follows: ； in, Take the gate DC voltage bias Positive value of The capacitance C is obtained by testing at low reference frequency. G ; The capacitance C obtained by testing at high reference frequency G ; represents the integral of the gate DC voltage bias; is the unit charge; is the gate area.

2. The method for measuring the near-interface trap density of SiC MOSFET channel according to claim 1, characterized in that: In step S1 , the SiC MOSFET sample is a planar MOSFET or a trench MOSFET.

3. The method for measuring the near-interface trap density of SiC MOSFET channel according to claim 1, characterized in that: In step S2, the gate-controlled diode working mode is: the drain and source of the SiC MOSFET sample to be tested are short-circuited and grounded together as a cathode, and the gate electrode is tested as an anode.

4. The method for measuring the near-interface trap density of SiC MOSFET channel according to claim 3, characterized in that: In step S2, the parameter analyzer selects a Keithley parameter analyzer.

5. The method for measuring the near-interface trap density of SiC MOSFET channel according to claim 3, characterized in that: In step S2, the frequency f of the sine wave is selected to be 1 KHz, 10 KHz, 100 KHz and 1 MHz.

6. The method for measuring the near-interface trap density of SiC MOSFET channel according to claim 5, characterized in that: In step S3, 1 MHz is selected as the high reference frequency, and 1 KHz is selected as the low reference frequency.

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