Groove etching method and semiconductor device

Abstract

The invention provides a groove etching method and a semiconductor device, and the method comprises the following steps: providing a substrate, and forming a mask layer on one surface of the substrate; coating a photoresist layer on the mask layer; forming an initial groove corresponding to the target groove on the photoresist layer by adopting a photoetching process; processing the photoresist layer by adopting an ultraviolet curing process; etching the mask layer by adopting a first etching process to obtain a patterned mask layer; and removing the photoresist layer. According to the trench etching method, the ultraviolet curing process of the photoresist layer is added before the mask layer is etched, the photoresist layer is cured while side wall stripes of a pattern of the photoresist layer are weakened, the photoresist layer tends to be flattened, further, the plasma transverse etching capacity is enhanced when the mask layer is etched, and the etching efficiency of the trench is improved. Therefore, the stripes on the side wall of the photoresist, which are transferred to the side wall of the mask layer, are further weakened, and the roughness of the side wall of the target groove is finally improved.

Description

Technical Field

[0001] The present invention relates to the technical field related to semiconductor devices, and in particular to a trench etching method and a semiconductor device. Background Art

[0002] Trench etching technology has always been a key technology in semiconductor process manufacturing, especially the critical dimension (CD) of trench isolation, which will directly affect the trench depth and the overall morphology of the trench. For example, the process flow of silicon carbide (SIC) trench etching is generally to deposit a dielectric layer on a silicon carbide substrate, apply photoresist on the surface of the dielectric layer, perform photolithography to form a pattern on the photoresist, use the photoresist as a mask, dry-etch the dielectric layer, then remove the remaining photoresist, use the dielectric layer as a trench etching mask layer to etch the silicon carbide trench, and finally remove the dielectric layer by wet method to form the required trench structure.

[0003] At present, after etching of silicon carbide trenches, the sidewalls of the trenches are relatively rough and have vertical stripes. Such stripes will have a great impact on device leakage and reliability. Therefore, the flattening of the sidewalls of silicon carbide trenches has been a technical problem to be solved for a long time. After slicing, it was found that the reason for the stripes on the sidewalls of silicon carbide trenches is that the sidewalls of the photoresist after the photolithography process have vertical stripes. When the dielectric layer is etched with the photoresist as a mask layer, the stripes are transferred from the photoresist to the sidewalls of the dielectric layer. Finally, when the silicon carbide trench is etched with the dielectric layer as a mask layer, the stripes on the dielectric layer are transferred to the sidewalls of the silicon carbide, causing the sidewalls of the silicon carbide trenches to be rough.

[0004] At present, the main process methods for improving the vertical stripes on the sidewalls of silicon carbide trenches are: first, flattening the sidewalls of the photoresist from the source, eliminating the vertical stripes by adjusting the photolithography exposure method or hard baking the photoresist after photolithography, but adjusting the exposure method or hard baking will change the morphology of the photoresist, causing the photoresist to become tilted or collapsed; second, repairing the sidewall stripes after silicon carbide trench etching, mainly by dry etching, but the process window for dry etching of the trench sidewalls is difficult to control, and too long dry etching time will cause critical dimension loss (Critical Dimension Loss), and too short processing time will not significantly repair the stripes.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present invention, and therefore may include information that does not constitute the prior art known to those skilled in the art. Summary of the invention

[0006] In view of the problems in the prior art, the purpose of the present invention is to provide a groove etching method and a semiconductor device. The groove etching method adds an ultraviolet curing process for the photoresist layer before etching the mask layer, and solidifies the photoresist layer while weakening the side wall stripes of the pattern of the photoresist layer, so that the photoresist layer tends to be flattened. Furthermore, when etching the mask layer, the plasma lateral etching ability is enhanced, so that the stripes on the side wall of the photoresist transferred to the side wall of the mask layer are further weakened, and finally the roughness of the side wall of the target groove is improved.

[0007] Specifically, a first aspect of the present invention provides a trench etching method, the trench etching method comprising the following steps:

[0008] Providing a substrate, and forming a mask layer on a surface of the substrate;

[0009] coating a photoresist layer on the mask layer;

[0010] Using a photolithography process to form an initial groove corresponding to the target groove on the photoresist layer;

[0011] Treating the photoresist layer by ultraviolet curing process;

[0012] Etching the mask layer using a first etching process to obtain a patterned mask layer;

[0013] The photoresist layer is removed.

[0014] According to a first aspect of the present invention, the first etching process is a dry etching process.

[0015] According to the first aspect of the present invention, the pressure of the reaction chamber in the dry etching process is greater than 200 mTorr. According to the first aspect of the present invention, the curing temperature of the ultraviolet curing process is 80°C to 120°C.

[0016] According to the first aspect of the present invention, the curing time of the UV curing process is 100 seconds to 1000 seconds.

[0017] According to the first aspect of the present invention, the trench etching method further comprises the following steps:

[0018] Using the patterned mask layer as a mask, a second etching process is used to etch a portion of the thickness of the substrate to form a target groove;

[0019] The patterned mask layer is removed.

[0020] According to the first aspect of the present invention, the second etching process is a dry etching process.

[0021] According to the first aspect of the present invention, the roughness of the sidewall of the trench is less than or equal to 0.60 nm.

[0022] According to the first aspect of the present invention, the patterned mask layer is removed by a wet process.

[0023] A second aspect of the present invention provides a semiconductor device, comprising a substrate and a trench arranged at the bottom, wherein the trench is prepared by the trench etching method.

[0024] Compared with the prior art, in the groove etching method of the present invention, after obtaining the patterned photoresist layer, the photoresist layer is cured again to flatten the side walls of the pattern of the photoresist layer, improve the roughness of the side walls of the pattern of the mask layer obtained by etching the patterned photoresist layer, and finally reduce the roughness of the side walls of the groove obtained using the mask layer as a mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. By reading the detailed description of the non-limiting embodiments with reference to the following drawings, other features, purposes and advantages of the present invention will become more apparent. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings without creative work. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same figure numbers in the figures represent the same or similar parts, and their repeated descriptions will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities.

[0026] Figure 1 A flow chart of a groove preparation method according to an embodiment of the present invention;

[0027] Figures 2 to 8 It is a schematic structural diagram corresponding to each step of a groove preparation method according to an embodiment of the present invention;

[0028] Fig. 9 a scanning electron microscope image of a target trench prepared by a conventional trench preparation method; and

[0029] Fig.10 A scanning electron microscope image of a target groove prepared by a groove preparation method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0030] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in the present invention. The present invention can also be implemented or applied through other different specific embodiments, and the details in the present invention can also be modified or changed according to different viewpoints and application systems without departing from the spirit of the present invention. It should be noted that the embodiments and features in the embodiments of the present invention can be combined with each other without conflict.

[0031] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0032] In the representation of the present invention, the reference terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics represented in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. Moreover, the specific features, structures, materials or characteristics represented may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples represented in the present invention and the features of different embodiments or examples, unless they are contradictory.

[0033] In order to clearly describe the present invention, components not related to the description are omitted, and the same reference numerals are given to the same or similar components throughout the specification.

[0034] Throughout the specification, when a device is said to be "connected" to another device, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a device is said to "include" a certain component, unless otherwise stated, it does not exclude other components, but means that other components may be included.

[0035] When a device is said to be "on" another device, it may be directly on the other device, but there may also be other devices between it. In contrast, when a device is said to be "directly" on another device, there are no other devices between it.

[0036] Although the terms first, second, etc. are used to represent various elements in some examples, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first interface and the second interface, etc. are represented. Moreover, as used in this article, the singular forms "one", "one" and "the" are intended to also include plural forms, unless there is an opposite indication in the context. It should be further understood that the terms "comprising" and "including" indicate the existence of features, steps, operations, elements, components, projects, kinds, and / or groups, but do not exclude the existence, occurrence or addition of one or more other features, steps, operations, elements, components, projects, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Only when the combination of elements, functions, steps or operations is inherently mutually exclusive in some way, will there be an exception to this definition.

[0037] The technical terms used herein are only used to refer to specific embodiments and are not intended to limit the present invention. The singular form used herein also includes the plural form as long as the sentence does not clearly indicate the opposite meaning. The meaning of "including" used in the specification is to specify specific characteristics, regions, integers, steps, operations, elements and / or components, and does not exclude the existence or addition of other characteristics, regions, integers, steps, operations, elements and / or components.

[0038] Although not defined differently, all terms, including technical and scientific terms used herein, have the same meaning as those generally understood by those skilled in the art to which the present invention belongs. Terms defined in commonly used dictionaries are additionally interpreted as having meanings consistent with the content of relevant technical literature and current disclosures, and unless defined, shall not be overly interpreted as ideal or very formal meanings.

[0039] In order to overcome the above technical problems, the present invention provides a groove etching method and a semiconductor device, the groove etching method comprising the following steps: providing a substrate, forming a mask layer on a surface of the substrate; coating a photoresist layer on the mask layer; forming an initial groove corresponding to the target groove on the photoresist layer by a photolithography process; treating the photoresist layer by an ultraviolet curing process; etching the mask layer by a first etching process to obtain a patterned mask layer; and removing the photoresist layer. The groove etching method of the present invention adds an ultraviolet curing process to the photoresist layer before etching the mask layer, and solidifies the photoresist layer while weakening the sidewall stripes of the pattern of the photoresist layer, so that the photoresist layer tends to be flattened. Furthermore, when etching the mask layer, the plasma lateral etching ability is enhanced, so that the stripes on the sidewall of the photoresist transferred to the sidewall of the mask layer are further weakened, and finally the roughness of the sidewall of the target groove is improved.

[0040] The process of the trench etching method and the semiconductor device of the present invention are further described below in conjunction with the accompanying drawings and specific embodiments. It can be understood that the various specific embodiments are not intended to limit the protection scope of the present invention.

[0041] Figure 1 is a flow chart of a groove preparation method according to an embodiment of the present invention. Figures 2 to 8 The present invention is a schematic structural diagram of each step of a trench preparation method according to an embodiment of the present invention. The trench etching method includes the following steps:

[0042] Step S100: Provide a substrate, and form a mask layer 20 on a surface of the substrate; the substrate of the present invention may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, or a silicon carbide (SiC) substrate. Alternatively, the substrate may be a laminated substrate including, for example, Si and SiGe, or a laminated substrate including Si and SiC. Figure 2 In the embodiment of the present invention, the substrate includes a silicon carbide substrate 10 and a silicon carbide epitaxial layer 11 thereon which can optimize the lattice structure, material properties and device structure of the device. The mask layer 20 can be a single layer or a multilayer, such as the mask layer 20 can include a silicon dioxide layer and a silicon nitride layer, or include a silicon dioxide layer and a titanium nitride layer, etc.

[0043] Step S200: coating a photoresist layer 30 on the mask layer 20. The thickness of the photoresist layer 30 can be determined according to the size of the desired pattern. The photoresist layer of desired thickness can be obtained by controlling the type of photoresist, the rotation speed and time during spin coating, etc.

[0044] Step S300: using a photolithography process to form an initial groove 31 corresponding to the target groove on the photoresist layer 30, Figure 3Further, step S300 includes exposing and developing the photoresist layer 30 of step S200 by a photolithography process to obtain a patterned photoresist layer 30. The width of the initial groove 31 may be consistent with the width of the target groove.

[0045] Step S400: Treat the photoresist layer 30 with a UV curing process. Figure 4 . Different from the existing groove etching process in which the patterned photoresist layer 30 is directly used as a mask to etch the mask layer 20 thereunder, the present invention adds a UV curing process for the photoresist layer 30. In one embodiment, the curing temperature of the UV curing process can be 80°C to 120°C, and the curing time of the UV curing process can be 100 seconds to 1000 seconds. Through step S400, the sidewalls of the initial grooves 31 on the photoresist layer 30 are further smoothed at the curing temperature, that is, the stripes formed on the sidewalls of the initial grooves 31 during the development of the photoresist layer 30 in step S300 are improved. That is, the roughness of the sidewalls of the initial grooves 31' of the photoresist layer 30' treated by the UV curing process is reduced, and the roughness (surface roughness) here refers to the unevenness of the small spacing and tiny peaks and valleys on the surface.

[0046] Step S500: Etching the mask layer 20 using a first etching process to obtain a patterned mask layer. Figure 5 . In this step, the first etching process can be a dry etching process, such as reactive ion etching (RIE), plasma etching (Plasma Enhance Chemical Vapor Deposition, PECVD), etc. Reactive ion etching RIE is a method of etching samples by chemical reaction between ions and surfaces. The basic principle is to use high-energy ions to impact the surface of the sample under high pressure. The high-energy electrons and ions generated will cause surface reactions to form a layer of reaction products, thereby achieving the purpose of etching. Plasma etching PECVD is a method of etching samples by chemical and physical reactions caused by plasma on the surface. Plasma is generated by a gas discharge process, which can generate high-energy ions and electrons. These particles cause surface reactions and produce etching by impacting the surface of the sample.

[0047] For example, when reactive ion etching (RIE) is used to etch the mask layer 20, chemical etching accounts for a larger component. Chemical etching is an ion chemical reaction between plasma and atoms or molecules of the etched material in all directions, so that the film is etched in two directions perpendicular to and parallel to the surface of the etched film at the same time, or in other words, etching that is close to isotropic occurs. When plasma etching (PECVD) is used to etch the mask layer 20, the physical etching component is greater than the chemical etching component. The so-called physical etching is that the plasma has a larger energy and a lower gas density, and the etching of the film is promoted by the physical bombardment of the surface of the etched insulating film by charged ions, that is, the etching mainly occurs in the direction perpendicular to the surface of the etched film, which is also called anisotropic etching. The sidewalls of the grooves etched in this way are close to vertical or have a slope of less than 90°.

[0048] In step S500, the sidewalls of the initial grooves 31' of the photoresist layer 30' treated by the UV curing process are smooth. In order to further weaken the vertical stripes on the sidewalls of the grooves 21 etched on the mask layer 20, when etching the mask layer 20, the strengths of chemical etching and physical etching capabilities can be adjusted, such as using dry etching process parameters in which chemical etching is dominant. When chemical etching is stronger than physical etching, the ability to laterally etch the mask layer 20 can be enhanced, the vertical stripes on the sidewalls of the grooves 21 of the mask layer 20 can be weakened, and the roughness of the sidewalls can be improved.

[0049] In one embodiment, the first etching process is a plasma etching process, wherein, in order to ensure the etching of the mask layer 20 at the edge of the wafer, the first etching process includes two stages, namely, a main etching stage and an over-etching stage. Table 1 shows the parameters of the first etching process of step S500 of one embodiment. The reaction gas includes a mixed gas of CHF3, CF4, O2, N2 and Ar. The pressure of the reaction chamber of the first etching process in the present invention is greater than 200mTorr, which is much greater than the ~30mTorr in the existing process of etching the mask layer. By increasing the pressure of the reaction chamber, the molecular free path is reduced, thereby reducing the physical bombardment in the etching process, that is, suppressing the physical etching part in the etching process. At the same time, the increase in the pressure of the reaction chamber can increase the concentration of free radicals, and the chemical etching ability is enhanced.

[0050] Table 1 shows the parameters of the first etching process of an embodiment.

[0051] First etching process Main Etch Overetch Etching time (seconds) 350 50 Pressure(mTorr) 240 240 High frequency voltage(W) 400 400 Low frequency voltage(W) 200 200 <![CDATA[CHF3(sccm)]]> 22 22 <![CDATA[CF4(sccm)]]> 60 60 <![CDATA[O2(sccm)]]> 20 20 <![CDATA[N2(sccm)]]> 10 10 Ar(sccm) 200 200

[0052] Step S600: removing the photoresist layer 30' to obtain Figure 6 structure;

[0053] Furthermore, the trench etching method further comprises the following steps:

[0054] Step S700: Using the patterned mask layer 20 as a mask, a second etching process is used to etch a portion of the thickness of the substrate to form a target trench T. Figure 7 ;

[0055] Step S800: removing the patterned mask layer 20 by a wet process. Figure 8 .

[0056] The structure (including width, aspect ratio, etc.) of the target trench T in step S700 can be set according to the structure of the silicon carbide device to be obtained and the performance to be achieved. Similarly, the second etching process here can be a dry etching process, but its parameters may be different from the parameters of the first etching process in step S500. Taking the acquisition of the target trench T in the silicon carbide epitaxial layer 11 as an example, the second etching process adopts a plasma etching process, and the specific process parameters are shown in Table 2.

[0057] Table 2 shows the parameters of the second etching process of an embodiment.

[0058]

[0059]

[0060] The roughness of the sidewall of the target groove on the wafer obtained by using the groove preparation method of the present invention was measured, and the experimental results showed that the roughness of the sidewall of the target groove was less than or equal to 0.60 nm. Fig. 9 a scanning electron microscope image (SEM) of a target trench prepared by an existing trench preparation method; and Fig.10 The scanning electron microscope image of the target groove prepared by the groove preparation method of one embodiment of the present invention. Table 3 shows the roughness of the sidewalls of the target grooves at different positions of the wafer prepared by the existing groove etching method and the existing groove etching method of one embodiment of the present invention. It can be seen that the roughness of the sidewalls of the target grooves at the center of the wafer obtained by the groove etching method of the present invention is reduced from 2.72nm of the prior art to 0.52nm. It can be seen that by adding the ultraviolet curing process of the photoresist layer before etching the mask layer, so as to make the sidewalls of the pattern of the photoresist layer smooth, it is beneficial to improve the roughness of the sidewalls of the target grooves obtained by etching.

[0061] Table 3 shows the roughness of the sidewalls of the target trenches at different positions of the wafer prepared by the existing trench etching method and the existing trench etching method according to one embodiment of the present invention.

[0062] Location Roughness at the wafer center Roughness at the wafer edge Existing trench etching methods 2.72nm 2.57nm One embodiment of the present invention 0.52nm 0.52nm

[0063] The present invention also provides a semiconductor device, which may be a MOSFET or an IGBT, etc. The semiconductor device includes a substrate and a groove arranged at the bottom, and the groove is prepared by the groove etching method. Since the groove etching method of the present invention is applicable to grooves of various aspect ratios, it is particularly applicable to manufacturing a groove isolation structure on a wafer, which is used to isolate regions between different electronic components, thereby realizing electrical isolation between highly integrated electronic components on the wafer. Since the roughness of the sidewall of the groove is reduced, the roughness of the dielectric layer in the groove can be improved, thereby improving the reliability and stability of the circuit. When applied to semiconductor power devices (e.g., super junction MOSFET), the working performance of the device will be greatly improved.

[0064] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

[0065] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A trench etching method, characterized in that: The trench etching method comprises the following steps: Providing a substrate, and forming a mask layer on a surface of the substrate; coating a photoresist layer on the mask layer; Using a photolithography process to form an initial groove corresponding to the target groove on the photoresist layer; Treating the photoresist layer by ultraviolet curing process; Etching the mask layer using a first etching process to obtain a patterned mask layer; The photoresist layer is removed.

2. The trench etching method according to claim 1, characterized in that: The first etching process is a dry etching process.

3. The trench etching method according to claim 2, characterized in that: The pressure of the reaction chamber in the dry etching process is greater than 200 mTorr.

4. The trench etching method according to claim 1, characterized in that: The curing temperature of the UV curing process is 80°C to 120°C.

5. The trench etching method according to claim 1, characterized in that: The curing time of the UV curing process is 100 seconds to 1000 seconds.

6. The trench etching method according to claim 1, characterized in that: The trench etching method further comprises the following steps: Using the patterned mask layer as a mask, a second etching process is used to etch a portion of the thickness of the substrate to form a target groove; The patterned mask layer is removed.

7. The trench etching method according to claim 6, characterized in that: The second etching process is a dry etching process.

8. The trench etching method according to claim 6, characterized in that: The roughness of the sidewall of the groove is less than or equal to 0.60 nm.

9. The trench etching method according to claim 6, characterized in that: The patterned mask layer is removed by a wet process.

10. A semiconductor device, characterized in that: The semiconductor device comprises a substrate and a trench arranged at the bottom, and the trench is prepared by using the trench etching method described in any one of claims 1 to 9.

Images