GaN semiconductor power transistor with tilted gate field plate and method of manufacture

Abstract

The invention discloses a GaN semiconductor power transistor structure with an inclined gate field plate and a manufacturing method. The gate field plate includes a gate metal field plate formed using contact metal and / or interconnect metal and a tilted gate field plate structure. The sloped structure of the gate field plate is defined by etching a dielectric layer having a graded composition to form a sloped opening filled with a conductive metal. The dielectric thickness and the tilt angle below the gate field plate are configured to appropriately shape the electric field in a region between the gate and the drain.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is related to U.S. patent application No. 18 / 129,457, filed on March 31, 2023, entitled “GaN Semiconductor Power Transistors With Stepped Metal Field Plates and Methods of Fabrication,” which is incorporated herein by reference in its entirety. Technical Field

[0002] The present invention relates to gallium nitride (GaN) semiconductor power transistors for high voltage and high current applications, such as GaN high electron mobility transistors (HEMTs). Background Art

[0003] In field effect transistors, field plates can be used to design or shape the electric field between electrodes of a power transistor (eg, in the region around the gate and between the gate and drain) to reduce dynamic on-resistance and increase device breakdown voltage.

[0004] The following references disclose examples of methods for stepped, tapered or tilted field plates for semiconductor power transistors: 10,068,974B2 to Li et al., granted on Sept. 4, 2018, and entitled “Field Plate Power Device and Method of Manufacturing the same.” US2008 / 0308813A1 by Suh et al., issued December 18, 2008, entitled “High Breakdown Enhancement Mode Gallium Nitride based High Electron Mobility Transistors with Integrated Slant Field Plate”; US2021 / 0280678A1 to Patel, granted on September 9, 2020, and titled “Greyscale Lithography for Double Slanted Gate Connected Field Plate”; Chu et al., US Pat. No. 8,530,978B1, issued on Sept. 10, 2013, entitled “High Current High Voltage GaN Field Effect Transistors and Method of Fabricating the Same”; US10,068,974B2, granted on September 4, 2018, entitled "Field Plate Power Device and Method of Manufacturing the same"; US9,929,243B1 to Corrion et al., issued on March 27, 2018, entitled “Stepped Field Palate Wide Bandgap Field-Effect Transistor and Method”; US8,980,759B1 by Corrion et al., issued on March 17, 2015, entitled “Method of Fabricating Slanted Field-Plate GaN Heterojunction Field-Effect Transistor”; US Patent No. 8,999,780B1 to Khalil et al., issued on April 7, 2015, entitled “Non-uniform two-dimensional electron gas profile in III-Nitride HEMT devices”; US10,103,219B2 by Pei et al., authorized on October 16, 2018, is titled "Power Semiconductor Device and Method for Manufacturing the same".

[0005] Some of these device structures add significant process complexity and / or may be incompatible with existing manufacturing processes offered by some semiconductor foundries.

[0006] In some device structures, the gate metal is used to form a gate metal field plate (GFMP). For example, a stepped gate metal field plate can be fabricated by gate metal deposition and etching or by using a lift-off metallization process.

[0007] Lift-off refers to the process of patterning a mask material (e.g., photoresist) and depositing a thin film (e.g., gate metal) over the entire area, then removing the mask material to leave the thin film only in the unmasked areas. The disadvantage of the lift-off metallization process is that unwanted metal layers and halos may remain on the surface of the wafer after lift-off. For high voltage applications, such as using GaN semiconductor high electron mobility transistors, the presence of unwanted metal extrusions can cause electric field crowding and potentially lead to dielectric failure.

[0008] There is a need for improved or alternative device structures and fabrication processes for power semiconductor transistors, such as GaN high electron mobility transistors, that include a gate metal field plate for high voltage applications. Summary of the invention

[0009] The present invention seeks to provide an improved or alternative device structure and manufacturing process for a GaN semiconductor power transistor (eg, a GaN high electron mobility transistor) including a gate metal field plate that overcomes one or more of the above-mentioned problems.

[0010] Aspects of the present invention provide a device structure and a manufacturing method including a GaN semiconductor power transistor (eg, an enhancement mode GaN high electron mobility transistor) including a tilted gate field plate.

[0011] One aspect provides a semiconductor device structure including an enhancement mode GaN semiconductor power transistor, including: An epitaxial layer structure, wherein the epitaxial layer structure includes a semiconductor substrate, a buffer layer, and a GaN semiconductor heterostructure, wherein the GaN semiconductor heterostructure includes a GaN channel layer and an AlGaN barrier layer, and provides a two-dimensional electron gas (2DEG) active region; a p-GaN layer, the p-GaN layer being patterned to define a p-GaN gate region; a first passivation layer; contact openings, the contact openings passing through the first passivation layer for source contacts and drain contacts; an ohmic contact metal disposed within the contact opening and patterned to form a source contact and a drain contact; a second passivation layer; A gate contact opening, the gate contact opening passing through the first passivation layer and the second passivation layer to reach the p-GaN gate region; a gate metal, the gate metal being positioned within the gate contact opening and being patterned to form a gate contact, the gate metal also forming a gate metal field plate in a region between the gate contact and a drain contact; a third dielectric layer formed thereon, the third dielectric layer having a graded composition; an opening etched through a third dielectric layer for source, drain and gate contacts, and another opening etched through the third dielectric layer having sloped sidewalls for forming a sloped gate field plate; At least one layer of conductive metal fills each opening to form a source contact, a drain contact, a gate contact, and a tilted gate field plate.

[0012] The third dielectric layer comprises a graded composition, wherein a bottom portion of the third dielectric layer has a denser composition than a top portion of the third dielectric layer, the graded composition providing an etch rate difference defining a tilt angle of a tilted gate metal field plate. The thickness of the third passivation layer and the tilt angle of the tilted gate field plate are configured to shape an electric field between a gate contact and a drain contact below the tilted gate field plate.

[0013] Another aspect of the present invention provides a method for manufacturing a semiconductor device structure including an enhancement mode GaN semiconductor power transistor, comprising: Providing an epitaxial layer structure, the epitaxial layer structure includes a semiconductor substrate, a buffer layer, a GaN semiconductor heterostructure and a covering p-GaN layer, the GaN semiconductor heterostructure includes a GaN channel layer and an AlGaN barrier layer, and provides a two-dimensional electron gas active region; etching the capping p-GaN layer to define a p-GaN gate region; providing a first passivation layer covering the p-GaN gate region; etching contact openings through the first passivation layer for source and drain contacts; depositing and patterning ohmic contact metal to form source and drain contacts; providing a second passivation layer; etching a gate contact opening through the first passivation layer and the second passivation layer to the p-GaN gate region; depositing and patterning a gate metal to form a gate contact and a gate metal field plate; depositing a third dielectric layer overall, the third dielectric layer having a graded composition, a bottom portion of the third dielectric layer having a denser composition and a slower etch rate than a top portion of the third dielectric layer; performing a first etching process on the third dielectric layer to form contact openings for a source contact, a gate contact, and a drain contact; A second etching process including wet etching is performed on the third dielectric layer to form an inclined opening of the gate field plate. At least one layer of conductive metal is deposited to fill contact openings for source contacts, gate contacts, and drain contacts and to form a tilted gate field plate.

[0014] The thickness of the third passivation layer and the tilt angle of the tilted gate field plate are configured to shape an electric field between the gate contact and the drain contact below the tilted gate field plate.

[0015] The step of depositing at least one layer of conductive metal may include depositing a single metal layer or multiple metal layers.

[0016] Depositing and patterning the gate metal to form the gate contact and the gate metal field plate may include a lift-off metal process.Depositing and patterning the gate metal to form the gate contact and the gate metal field plate may include depositing and etching the gate metal.

[0017] An enhanced GaN semiconductor power transistor structure with a tilted gate field plate and a method for manufacturing the same are disclosed. In an exemplary embodiment, the resulting tilted field plate structure provides an electric field distribution that provides a lower and smoother Coss curve, thereby improving the device's figure of merit (FOM). BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A schematic cross-sectional view showing a semiconductor device structure including an e-type GaN high electron mobility transistor including a gate metal contact and a gate metal field plate (GMFP) according to a first exemplary embodiment; and

[0019] FIG. 2A to FIG. 2J Schematic cross-sectional views are shown to illustrate steps in a method for manufacturing a semiconductor device structure including an e-type GaN high electron mobility transistor including a gate metal contact and a gate metal field plate (GMFP) for a first exemplary embodiment;

[0020] Figure 3 Schematic cross-sectional views are shown to illustrate steps in a method of manufacturing a semiconductor device structure including an e-type GaN high electron mobility transistor including a gate metal contact and a gate metal field plate (GMFP) according to a second exemplary embodiment;

[0021] The foregoing and other features, aspects and advantages will become more apparent from the following detailed description of exemplary embodiments, which is given by way of example only, taken in conjunction with the accompanying drawings. DETAILED DESCRIPTION

[0022] Figure 11 shows a schematic cross-sectional view of a device structure 10 including an enhancement mode (E-mode) GaN high electron mobility transistor having a gate metal field plate according to a first exemplary embodiment. The GaN transistor is fabricated on a semiconductor substrate (e.g., a silicon substrate 102). The semiconductor layer includes an epitaxial layer stack 112, which includes one or more buffer layers or intermediate layers 104, a GaN channel layer 106, and an overlying AlGaN barrier layer 108, which are epitaxially formed on the semiconductor substrate 102. For example, for a GaN on silicon device structure, the substrate 102 may be a p-doped silicon substrate. <111> . The latter may be referred to as a growth substrate. The GaN / AlGaN heterostructure layer 106 / 108 produces a two-dimensional electron gas (2DEG) active region 110 in the device region of the GaN-on-silicon substrate. The stack of GaN epitaxial layers formed on the silicon substrate, i.e., the intermediate layer 104, the GaN layer 106, and the AlGaN layer 108, and any intermediate layers not actually shown, will be referred to as an "epitaxial layer stack" or "epitaxial stack" 112 hereinafter. After the epitaxial layer stack 112 is formed, source, drain, and gate electrodes are formed. For example, a conductive metal layer, such as an aluminum / titanium (Al / Ti) layer that forms an ohmic contact (OC) with the underlying GaN heterostructure layer, is deposited and patterned to define a source electrode 122 and a drain electrode 124. A gate electrode 126 is defined on the channel region between the source electrode and the drain electrode, for example a gate electrode comprising a Schottky metal such as palladium (Pd) or gold (Au). The gate metal may include multiple layers, such as a thin layer of titanium (Ti), a thin layer of platinum, and a thicker layer of gold (Au). The device structure may be fabricated as a normally-on depletion-mode (D-mode) device, or as a normally-off enhancement-mode (E-mode) device. For an E-mode high electron mobility transistor, the gate structure includes a p-type semiconductor layer 116 disposed in a region below the gate electrode, such as a p-type GaN layer or a p-type AlGaN layer below the gate metal 126, such as Figure 1 For a D-type high electron mobility transistor, the p-GaN layer is omitted and the gate electrode is formed directly on the AlGaN barrier layer.

[0023] like Figure 1 As schematically shown in FIG. 1 , the lateral GaN high electron mobility transistor device structure further includes a gate metal field plate (GMFP) 128. The gate metal field plate includes one or more metal layers that are the same as the gate metal. For example, a multilayer metal including Ti / Pt / Au. The gate metal 126 and the gate metal field plate 128 can be formed by metal deposition and etching or by a lift-off metallization process.

[0024] There is an overlying interconnect structure including one or more conductive metal layers and a dielectric layer. The interconnect structure may include multiple conductive metal layers and intermediate (intermetallic) dielectric layers to provide source contacts, drain contacts, and gate contacts. For example, a first metal layer (which may be referred to as a contact metal) provides a source contact 222 with a source ohmic contact 122 and a drain contact 224 with a drain ohmic contact 124, as well as a gate contact 226 with a gate metal 126. Another metal layer labeled M1 provides a larger area of ​​source contact 322, drain contact 324, and gate contact 326. The contact metal and metal M1 may each include multiple conductive metal layers or be formed by a single conductive metal layer. The contact metal also defines an inclined gate field plate 228 that contacts the gate metal field plate 128. Metal M1 defines a field plate contact region 328. Figure 1 The interconnect structure schematically shown in also includes a second metal layer, labeled M2, defining a source contact region 522, a drain contact region 524, and a gate field plate contact region 528.

[0025] The gate metal field plate 128 may be connected to the source contact region 522 through a metal M2 interconnect trace 530 to the contact region 528 and through an intermediate metal layer including the tilted field plate 228, as shown in FIG. Figure 1 Schematically shown in FIG.

[0026] For simplicity, in Figure 1 In the GaN transistor structure shown, only a single source electrode, drain electrode and gate electrode are shown. Figure 1 Only one transistor element for the device structure 10 is shown in the simplified schematic cross-sectional view in FIG, but it should be understood that a large area, multi-island lateral GaN high electron mobility transistor can be provided. In a multi-island lateral GaN high electron mobility transistor, multiple transistor islands or cells are connected in parallel to form a large gate width transistor with high current carrying capacity. An inactive region or isolation region can surround the two-dimensional electron gas active device region. For example, the isolation region can be formed by ion implantation.

[0027] The device structure can be manufactured as a normally-on depletion-mode (D-type) device, or as a normally-off enhancement-mode (E-type) device. For example, for a D-type high electron mobility transistor, the GaN heterostructure can include an undoped GaN layer and an undoped AlGaN layer, with the gate electrode formed directly on the AlGaN layer. For an enhancement-mode (E-type) high electron mobility transistor, the GaN heterostructure includes a p-type semiconductor layer 116 disposed in a region below the gate electrode, such as a p-type GaN layer or a p-type AlGaN layer below the gate metal, such as Figure 1 Schematically shown in FIG.

[0028] The gate metal field plate 128 is formed of a gate metal, which may include multiple metal layers, such as Ti / Pt / Au. In order to form the inclined gate field plate structure 228, the composition of the dielectric 3 has a gradient composition so that wet etching can form a tapered opening with a defined tilt angle. For example, the third dielectric layer (dielectric 3) has a gradient composition, wherein the bottom of the third dielectric layer has a denser composition and a slower etching rate than the top of the third dielectric layer, and the top of the third dielectric layer is less dense and has a higher etching rate.

[0029] For example, the dielectric passivation layer may include silicon dioxide, silicon nitride, silicon oxynitride, and combinations thereof to provide appropriate thickness and composition.The structures shown in the figures are simplified schematic representations, and thicknesses and lateral dimensions are not drawn to scale.

[0030] For GaN high electron mobility transistors with high two-dimensional electron gas density, insufficient thickness of the dielectric under the gate metal field plate can lead to degradation of the dielectric, which may form a leakage path. For example, if the thickness of the dielectric 1 (e.g., SiN) under the gate metal field plate is too thin, such as ≤100nm, it may not be thick enough for devices with high two-dimensional electron gas density at the AlGaN / GaN interface. By selecting an appropriate tilt angle, the dielectric thickness under the tilted gate field plate can be controlled, so that the electric field distribution can be optimized by suppressing the magnitude of the vertical electric field, which helps reduce leakage and improves the robustness and lifetime of the device.

[0031] FIG. 2A to FIG. 2J A schematic cross-sectional view is shown to illustrate the Figure 1 The exemplary embodiment shown is a step in an embodiment of a method of manufacturing a semiconductor device structure including an e-type GaN high electron mobility transistor including a gate metal contact and a gate metal field plate.

[0032] like Figure 2A As schematically shown in , in the fabrication of a GaN high electron mobility transistor for high voltage applications, the starting wafer may be an epitaxial wafer comprising a silicon substrate 102 and a GaN semiconductor epitaxial layer stack, the GaN semiconductor epitaxial layer stack comprising one or more buffer / intermediate layers 104, a silicon nitride channel layer 106, and an overlying AlGaN barrier layer 108. The GaN / AlGaN heterostructure layer creates a two-dimensional electron gas active region for the device region of the GaN substrate on silicon. The epitaxial layer stack for an enhancement mode GaN high electron mobility transistor comprising a p-GaN gate structure may include a p-GaN capping layer. The first step in the process is a p-GaN gate etch, which defines a p-GaN gate region 116 for each transistor element, as shown in FIG. Figure 2BDevice processing needs to be carefully controlled to maintain the microstructural quality of the semiconductor layers of the starting wafer. For example, exposure of the AlGaN and p-GaN semiconductor layers during device processing can create defects or trap states, which can lead to degradation of key static and dynamic electrical parameters. Figure 2C As schematically shown in FIG. 1 , it is therefore desirable to provide a first dielectric or passivation layer 300-1 over the p-GaN gate structure and over the AlGaN barrier layer before forming ohmic contacts for the source and drain, and before providing gate metal for the gate structure and gate metal field plate. After providing the passivation layer 300-1, an isolation region 114 may be provided around the active region, for example, ion implantation may be performed to form an implanted isolation region 114 surrounding the active region.

[0033] After forming the passivation layer 300-1, as Figure 2D As schematically shown in FIG. 1 , an opening is formed in the passivation layer 300-1 by depositing and etching the source and drain ohmic contact metals, and a source ohmic contact 122 and a drain ohmic contact 124 are formed. After providing the second dielectric or passivation layer 300-2, a gate contact opening is made, and a gate metal is provided by deposition and etching back or using a lift-off process, such as Figure 2E The gate is patterned to form a gate contact 126 and a gate metal field plate 128 .

[0034] Then, if Figure 2F As shown, a third dielectric layer 300-3 is deposited to provide a desired thickness of dielectric for forming an opening that will be used to define the structure of the tilted gate field plate 228. The third dielectric layer 300-3 is deposited with a graded composition, for example, it is denser at the bottom and less dense at the top. Then, as shown in FIG. Figure 2G As shown, the process performs dielectric etching to form a tapered opening. The graded composition of the third dielectric layer 300-3 allows the third dielectric layer 300-3 to be wet etched to form a tapered opening with a predetermined sidewall tilt angle. The lower density composition at the top is etched faster than the higher density composition at the bottom. The composition of the third dielectric layer changes from bottom to top to control the etching rate and form a tapered sidewall 227.

[0035] Contact openings 221 for the source, drain and gate are defined, for example by dry etching, such as Figure 2H shown.

[0036] These etching steps provide openings for source contacts, drain contacts, gate contacts and angled metal field plates.

[0037] The contact metal deposition step may be used to form source contact 222, drain contact 224, gate contact 226, and tilted gate field 228. A first metallization layer M1 is then deposited and patterned to provide contact regions for each, such as Fig.2I As shown, it includes a source contact region 322 , a gate contact region 226 , a gate metal field plate contact region 328 and a drain contact region 324 .

[0038] If necessary, a second level of interconnection may be provided by depositing a fourth dielectric layer (intermetal dielectric) 300-4, etching contact openings, and forming a second metallization layer M2 to fill the contact openings and form M2 contact regions. Figure 2J As shown, it includes source contact 422 / 522, drain contact 424 / 524, and gate metal field plate contact 428 / 528. The gate metal field plate contact can be connected to the source through region 530 of M2.

[0039] A schematic cross-sectional view of a device structure 20 including an enhancement mode (E-mode) GaN high electron mobility transistor according to a second exemplary embodiment is shown in FIG. Figure 3 As shown, the enhancement mode GaN high electron mobility transistor has a gate metal field plate. The corresponding parts are marked with Figure 1 The same reference numerals are used herein. Figure 3 The device structure 20 schematically shown in FIG. Figure 1 The device structure 10 schematically shown in FIG. 1 is different in that the opening in the dielectric 3 for the gate metal field plate 228-2 has a different lateral profile to form a Figure 3 The inclined field plate shown in FIG. 1 tapers towards the drain region.

[0040] exist Figure 1 and Figure 3 In the exemplary embodiment schematically shown in , the tilt angle provides a smooth taper of the dielectric thickness below the field plate in the drain direction. In alternative embodiments, the gate metal field plate can have a more complex shape, which is controlled by a gradual variation of the composition of the dielectric 3 with thickness, so that the etching rate of the dielectric 3 depends on the thickness to control the tilt angle of the opening in which the gate metal field plate is formed.

[0041] By choosing the appropriate tilt angle and the dielectric thickness below the tilted field plate, the electric field distribution can be optimized by suppressing the magnitude of the vertical electric field, which helps reduce leakage and improves the device robustness and lifetime.

[0042] The above-referenced related U.S. Patent Application No. 18 / 129,457, entitled “GaN Semiconductor Power Transistors With Stepped Metal Field Plates and Methods of Fabrication” filed on March 31, 2023, discloses a power semiconductor structure including an exemplary embodiment of a stepped metal field plate. GaN semiconductor power transistors including exemplary embodiments of a tilted gate metal field plate fabricated as disclosed herein can provide an improved E field distribution, such as a lower and smoother Coss curve, to provide an improved quality factor.

[0043] While exemplary embodiments have been described and shown in detail, it should be clearly understood that these embodiments are by way of illustration and example only and are not restrictive, with the scope of the present invention being limited only by the appended claims.

Claims

1. A semiconductor device structure including an enhancement mode GaN semiconductor power transistor, comprising: An epitaxial layer structure, the epitaxial layer structure comprising a semiconductor substrate, a buffer layer, and a GaN semiconductor heterostructure, wherein the GaN semiconductor heterostructure comprises a GaN channel layer and an AlGaN barrier layer, providing a two-dimensional electron gas (2DEG) active region; a p-GaN layer patterned to define a p-GaN gate region; a first passivation layer; contact openings, the contact openings passing through the first passivation layer for source contacts and drain contacts; an ohmic contact metal located within the contact opening and patterned to form a source contact and a drain contact; a second passivation layer; a gate contact opening, the gate contact opening passing through the first passivation layer and the second passivation layer to reach the p-GaN gate region; a gate metal located within the gate contact opening and patterned to form a gate contact, the gate metal also forming a gate metal field plate in a region between the gate contact and the drain contact; a third dielectric layer formed thereon, the third dielectric layer having a graded composition; an opening etched through the third dielectric layer for source, drain and gate contacts, and another opening etched through the third dielectric layer having sloped sidewalls for forming a sloped gate field plate; At least one layer of conductive metal fills each of the openings to form the source contact, the drain contact, the gate contact, and the tilted gate field plate. 2 . The semiconductor device structure of claim 1 , wherein the thickness of the third dielectric layer and the graded composition are configured to shape an electric field between the gate contact and the drain contact below the tilted gate field plate.

3. The semiconductor device structure of claim 1 , wherein a thickness of the third dielectric passivation layer and a tilt angle of the tilted gate field plate are configured to shape an electric field between the gate contact and the drain contact below the tilted gate field plate. 4 . The semiconductor device structure of claim 1 , wherein the at least one layer of conductive metal comprises depositing a single metal layer. 5 . The semiconductor device structure of claim 1 , wherein the at least one conductive metal layer comprises depositing a plurality of metal layers. 6 . The semiconductor device structure of claim 1 , comprising an interconnect trace connecting the source contact and the tilted gate field plate. 7 . The semiconductor device structure according to claim 1 , wherein the gate metal contact and the gate metal field plate are formed by a lift-off metal process. 8 . The semiconductor device structure according to claim 1 , wherein the gate metal contact and the gate metal field plate are formed by deposition and etching of the gate metal.

9. The semiconductor device structure of claim 1, wherein the third dielectric layer comprises a graded composition, wherein a bottom portion of the third dielectric layer has a denser composition than a top portion of the third dielectric layer, the graded composition providing an etch rate difference that defines the tilt angle.

10. The semiconductor device structure of claim 1, wherein the third dielectric layer comprises a plurality of dielectric layers deposited sequentially to provide the graded composition.

11. A method for manufacturing an enhancement mode GaN semiconductor power transistor, comprising: Providing an epitaxial layer structure, the epitaxial layer structure comprising a semiconductor substrate, a buffer layer, a GaN semiconductor heterostructure and a covering p-GaN layer, the GaN semiconductor heterostructure comprising a GaN channel layer and an AlGaN barrier layer, providing a two-dimensional electron gas active region; etching the capping p-GaN layer to define a p-GaN gate region; providing a first passivation layer covering the p-GaN gate region; etching contact openings through the first passivation layer for source and drain contacts; depositing and patterning ohmic contact metal to form source and drain contacts; providing a second passivation layer; etching a gate contact opening through the first passivation layer and the second passivation layer to the p-GaN gate region; depositing and patterning a gate metal to form a gate contact and a gate metal field plate; depositing a third dielectric layer overall, the third dielectric layer having a graded composition, a bottom portion of the third dielectric layer having a denser composition and a slower etch rate than a top portion of the third dielectric layer; performing a first etching process on the third dielectric layer to form contact openings for a source contact, a gate contact, and a drain contact; performing a second etching process including wet etching on the third dielectric layer to form an inclined opening for an inclined gate field plate; At least one layer of conductive metal is deposited to fill contact openings for the source contact, the gate contact, and the drain contact and to form a tilted gate field plate. 12 . The method of claim 11 , wherein a thickness of the third dielectric passivation layer and a tilt angle of the tilted gate field plate are configured to shape an electric field between the gate contact and the drain contact below the tilted gate field plate.

13. The method of claim 11, wherein the step of depositing at least one layer of conductive metal comprises depositing a single metal layer.

14. The method of claim 11, wherein the step of depositing at least one layer of conductive metal comprises depositing a plurality of metal layers. 15 . The method of claim 11 , wherein depositing and patterning a gate metal to form the gate contact and the gate metal field plate comprises a lift-off metal process. 16 . The method of claim 11 , wherein depositing and patterning a gate metal to form the gate contact and the gate metal field plate comprises depositing and etching the gate metal.

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