Switch type delay line circuit

Abstract

The invention discloses a switch type delay line circuit, which comprises a first part of circuit serving as a single-pole double-throw switch, a second part of circuit serving as a single-pole double-throw switch, a third part of circuit serving as a third part of circuit, a fourth part of circuit serving as a fourth part of circuit and a fifth part of circuit serving as a fifth part of circuit, n delay modules and N-1 double-pole-double-throw switches are arranged at intervals and connected in series, one end of the first delay module is connected with two ports of the other end of the first part of circuit, the other end of the first delay module is connected with one end of the first double-pole-double-throw switch, and the rest can be done in the same manner until the time delay module is connected with the other end of the first part of circuit. The other end of the (N-1) th double-pole-double-throw switch is connected with one end of the Nth time delay module, and the other end of the Nth time delay module is connected with the second part circuit; n-bit adjustable time delay is realized; and the second part circuit is used as a single-pole double-throw switch, two ports of one end of the second part circuit are connected with the other end of the Nth delay module, and one port of the other end of the second part circuit is used as a radio frequency input / output port RF2 of the delay line circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuit design, and in particular to a switch type delay line circuit. Background Art

[0002] With the rapid development of satellite Internet around the world, real-time monitoring of transit satellites, identification and analysis of links and signals have become key issues affecting national security, and the development of low-cost large-aperture phased array antennas has become a bottleneck device for the above monitoring system. Traditional phase-shift controlled phased array antennas have the phenomenon of beam deflection, which makes large-aperture arrays face the problem of narrow instantaneous bandwidth. The application of delay line circuits can greatly alleviate this problem. At present, signal delay functions are mostly implemented in an analog-to-digital hybrid manner, but the increase in the number of digital channels will inevitably increase the cost of the entire machine sharply, and analog delay components have design bottlenecks such as poor consistency, low accuracy, and small range. Summary of the invention

[0003] Technical purpose: In view of the defects in the prior art, the present invention discloses a switch-type delay line circuit to achieve high precision, large range and high consistency.

[0004] Technical solution: In order to achieve the above technical objectives, the present invention adopts the following technical solution.

[0005] A switch type delay line circuit, comprising: The first circuit is a single-pole double-throw switch, one end of which is connected to the RF input / output port RF1 of the delay line circuit, and the other end of which is connected to the first delay module; N delay modules and N-1 double-pole double-throw switches are arranged in series at intervals, one end of the first delay module is connected to the two ports at the other end of the first part of the circuit, the other end of the first delay module is connected to one end of the first double-pole double-throw switch, and so on, until the other end of the N-1th double-pole double-throw switch is connected to one end of the Nth delay module, and the other end of the Nth delay module is connected to the second part of the circuit; to achieve N-bit adjustable delay; The second circuit part, as a single-pole double-throw switch, has two ports at one end connected to the other end of the Nth delay module, and one port at the other end serves as the radio frequency input / output port RF2 of the delay line circuit.

[0006] Beneficial effects: (1) The present invention achieves high-precision, wide-range, and high-consistency delay performance through cascade extension of the structure, that is, the interval connection of the delay module and the double-pole double-throw switch; (2) The present invention introduces an attenuation network into a small-range delay circuit, and its attenuation increases with increasing frequency, thereby achieving a path loss with consistent frequency characteristics under different delay states. Without deteriorating the delay performance, the gain consistency of different delay states is greatly improved, and the complexity of circuit gain calibration is reduced; BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of an equivalent structure of a switch-type delay line circuit provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a single-pole double-throw switch provided in an embodiment of the present application; Figure 3 A schematic diagram of the double-pole double-throw switch structure provided in an embodiment of the present application; Figure 4 A schematic diagram of the delay unit structure provided in an embodiment of the present application; Figure 5 A schematic diagram of the delay line circuit structure provided for this application; Figure 6 The simulation results of the switch delay line circuit example provided in the embodiment of the present application are as follows: Figure 1 ; Figure 7 The simulation results of the switch delay line circuit example provided in the embodiment of the present application are as follows: Figure 2 ; Figure 8 The simulation results of the switch delay line circuit example provided in the embodiment of the present application are as follows: Figure 3 ; Fig. 9 The simulation results of the switch delay line circuit example provided in the embodiment of the present application are as follows: Figure 4 ; In the figure: 100-first circuit; 200-second circuit; 300-third circuit; 400-fourth circuit; 500-fifth circuit; 600-sixth circuit; 700-seventh circuit; 101-first transistor, 102-second transistor, 103-third transistor, 104-fourth transistor, 105-first inductor, 106-second inductor, 107-third inductor, 301-fifth transistor, 302-sixth transistor, 303-seventh Transistor, 304-eighth transistor, 305-ninth transistor, 306-tenth transistor, 307-eleventh transistor, 308-twelfth transistor, 309-fourth inductor, 310-fifth inductor, 311-sixth inductor, 312-seventh inductor, 501-eighth inductor, 502-ninth inductor, 503-first capacitor, 504-second capacitor, 505-third capacitor, 506-first transmission line, 507-second transmission line, 508-fourth capacitor, 509-first resistor. DETAILED DESCRIPTION

[0008] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0009] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0010] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0011] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0012] In the description of this application, it is also necessary to explain that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0013] In conjunction with the accompanying drawings, some embodiments of the present application are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0014] After a lot of practice and experience summary, it is found that traditional analog delay components have design bottlenecks such as poor consistency, low precision, and small range. This application proposes a switching delay line circuit that can achieve high-precision, large-range, and highly consistent delay performance.

[0015] Please refer to Figure 5 , a switch type delay line circuit of the present application comprises: The first circuit 100 is used as a single-pole double-throw switch, one port at one end is used as the radio frequency input / output port RF1 of the delay line circuit, and the two ports at the other end are connected to the first delay module; N delay modules and N-1 double-pole double-throw switches are arranged in series at intervals, one end of the first delay module is connected to the two ports at the other end of the first circuit 100, and the other end of the first delay module is connected to one end of the first double-pole double-throw switch, and so on, until the other end of the N-1 double-pole double-throw switch is connected to one end of the N delay module, and the other end of the N delay module is connected to the second circuit 200; to achieve an adjustable delay of N bits; The second circuit 200 is a single-pole double-throw switch, with two ports at one end connected to the other end of the Nth delay module, and one port at the other end serving as the RF input / output port RF2 of the delay line circuit; the present application uses a single-pole double-throw switch at the input and output ports to switch the delay path, and a double-pole double-throw switch between the delay modules to switch the delay path, thereby realizing the adjustable delay function. Figure 5 The structure shown can achieve high-precision and large-range delay functions.

[0016] In the direction from the RF input / output port RF1 to the RF input / output port RF2, the delay module includes a number of delay units with the same structure, and the number of delay units increases in geometric progression, with a ratio of 2. The first delay module is provided with 1 delay unit, and the Nth delay module is provided with 2 delay units. N-1 A delay unit is provided to realize an adjustable delay of N bits. A large-range delay circuit and a small-range delay circuit are provided in the delay unit. In the present application, the large-range and small-range delay circuits are distinguished according to the electrical length of the delay circuit, that is, of the two delay circuits, the one with the larger electrical length is used as the large-range delay circuit, and the one with the smaller electrical length is used as the small-range delay circuit; that is to say, in the present application, the electrical length of the large-range delay circuit is greater than the electrical length of the small-range delay circuit. In the delay module, the large-range delay circuits are connected in sequence, and the small-range delay circuits are connected in sequence.

[0017] Please refer to Figure 1 , Figure 1 A schematic diagram of a switch delay line circuit structure provided in an embodiment of the present application, wherein N is set to 3, i.e., a 3-bit delay is achieved. A switch delay line circuit provided in this embodiment includes: The first circuit 100 is a single-pole double-throw switch, one end of which is connected to the RF input / output port RF1 of the delay line circuit, and the other end of which is connected to the third circuit 300 via the fifth circuit 500; The third circuit 300 is a double-pole double-throw switch, wherein two ports at one end are connected to the first circuit 100 through the fifth circuit 500, and two ports at the other end are connected to the fourth circuit 400 through the sixth circuit 600; The fourth circuit 400 is a double-pole double-throw switch, wherein two ports at one end are connected to the third circuit 300 through the sixth circuit 600, and two ports at the other end are connected to the second circuit 200 through the seventh circuit 700; The second circuit 200 is a single-pole double-throw switch, two ports at one end of which are connected to the fourth circuit 400 through the seventh circuit 700, and one port at the other end is connected to the radio frequency input / output port RF2 of the delay line circuit; The fifth circuit 500, the sixth circuit 600 and the seventh circuit 700 serve as delay modules to implement adjustable delay in the signal transmission process between the RF input / output port RF1 of the delay line circuit and the RF input / output port RF2 of the delay line circuit.

[0018] Please refer to Figure 2 , Figure 2 Schematic diagram of the structure of the first circuit 100 provided in an embodiment of the present application. The first circuit 100 serves as a single-pole double-throw switch, including a first transistor 101, a second transistor 102, a third transistor 103, a fourth transistor 104, a first inductor 105, a second inductor 106 and a third inductor 107.

[0019] One end of the first inductor 105 is connected to the drain of the third transistor 103 and the drain of the fourth transistor 104, and the other end of the first inductor 105 serves as port 1 of the single-pole double-throw switch, which is also a port at one end of the single-pole double-throw switch. Port 1 is connected to the RF input / output port RF1 of the delay line circuit; one end of the second inductor 106 is connected to the drain of the first transistor 101 and the source of the third transistor 103, and the other end of the second inductor 106 serves as port 2 of the single-pole double-throw switch; one end of the third inductor 107 is connected to the drain of the second transistor 102 and the source of the fourth transistor 104, and the other end of the third inductor 107 serves as port 3 of the single-pole double-throw switch. Ports 2 and 3 serve as two ports at the other end of the single-pole double-throw switch and are connected to the first delay module; the source of the first transistor 101 is grounded, and the source of the second transistor 102 is grounded. The gate of the first transistor 101 is connected to the gate of the fourth transistor 104. voltage, the gate of the second transistor 102 and the gate of the third transistor 103 are connected Voltage.

[0020] The inductance of the second inductor 106 is the same as that of the third inductor 107; the size of the first transistor 101 is the same as that of the fourth transistor 104, and the gate control voltage is the same; the size of the second transistor 102 is the same as that of the third transistor 103, and the gate control voltage is the same; the gate control voltages of the first transistor 101 and the third transistor 103 are opposite, and the gate control voltages of the second transistor 102 and the fourth transistor 104 are opposite.

[0021] When the first transistor 101 and the fourth transistor 104 are turned off, the second transistor 102 and the third transistor 103 are turned on. At this time, a signal path is formed between port 1 and port 2 of the single-pole double-throw switch, and the signal between other ports is cut off. The first inductor 105, the second inductor 106, the turn-off parasitic capacitance of the first transistor 101, and the turn-off parasitic capacitance of the fourth transistor 104 form a T-type matching network between port 1 and port 2; when the first transistor 101 and the fourth transistor 104 are turned on, the second transistor 102 and the third transistor 103 are turned off. At this time, a signal path is formed between port 1 and port 3 of the single-pole double-throw switch, and the signal between other ports is cut off. The first inductor 105, the third inductor 107, the turn-off parasitic capacitance of the second transistor 102, and the turn-off parasitic capacitance of the third transistor 103 form a T-type matching network between port 1 and port 3.

[0022] In this embodiment, the second circuit 200 is the same as the first circuit 100. Port 1 of the single-pole double-throw switch in the second circuit 200 is connected to the radio frequency input / output port RF2 of the delay line circuit.

[0023] Please refer to Figure 3 , Figure 3 This is a structural schematic diagram of the third circuit 300 provided in an embodiment of the present application. The third circuit 300 serves as a double-pole double-throw switch, including a fifth transistor 301, a sixth transistor 302, a seventh transistor 303, an eighth transistor 304, a ninth transistor 305, a tenth transistor 306, an eleventh transistor 307, a twelfth transistor 308, a fourth inductor 309, a fifth inductor 310, a sixth inductor 311, and a seventh inductor 312.

[0024] One end of the fourth inductor 309 is connected to the drain of the fifth transistor 301, the source of the ninth transistor 305, and the source of the eleventh transistor 307, and the other end of the fourth inductor 309 serves as port 1 of the double-pole double-throw switch; one end of the fifth inductor 310 is connected to the drain of the sixth transistor 302, the drain of the ninth transistor 305, and the drain of the twelfth transistor 308, and the other end of the fifth inductor 310 serves as port 2 of the double-pole double-throw switch, and port 1 and port 2 of the double-pole double-throw switch serve as two ports at one end of the double-pole double-throw switch; one end of the sixth inductor 311 is connected to the drain of the seventh transistor 303. The source of the fifth transistor 301, the sixth transistor 302, the seventh transistor 303, and the eighth transistor 304 are connected to the drain of the eighth transistor 304, the drain of the tenth transistor 306, and the drain of the eleventh transistor 307, and the other end of the seventh inductor 312 serves as port 4 of the double-pole double-throw switch, and port 3 and port 4 of the double-pole double-throw switch serve as two ports at the other end of the double-pole double-throw switch; the sources of the fifth transistor 301, the sixth transistor 302, the seventh transistor 303, and the eighth transistor 304 are grounded. The gates of the fifth transistor 301, the sixth transistor 302, the seventh transistor 303, the eighth transistor 304, the ninth transistor 305, the tenth transistor 306, the eleventh transistor 307 and the twelfth transistor 308 are respectively connected to the gate control signal to realize the four conduction channels of the double-pole double-throw switch; the port No. 1 and the port No. 2 of the double-pole double-throw switch as the two ports at one end are connected to the first part of the circuit 100 through the fifth part of the circuit 500, and the port No. 3 and the port No. 4 of the double-pole double-throw switch as the two ports at the other end are connected to the fourth part of the circuit 400 through the sixth part of the circuit 600.

[0025] The fourth inductor 309, the fifth inductor 310, the sixth inductor 311, and the seventh inductor 312 have the same inductance; the fifth transistor 301, the sixth transistor 302, the seventh transistor 303, and the eighth transistor 304 have the same size; the ninth transistor 305, the tenth transistor 306, the eleventh transistor 307, and the twelfth transistor 308 have the same size.

[0026] When the seventh transistor 303, the eighth transistor 304, the ninth transistor 305, and the tenth transistor 306 are turned on, the remaining transistors are turned off. At this time, a signal path is formed between port 1 and port 2 of the double-pole double-throw switch, and the signal between other ports is cut off. The fourth inductor 309, the fifth inductor 310, the turn-off parasitic capacitance of the eleventh transistor 307, and the turn-off parasitic capacitance of the twelfth transistor 308 form a T-type matching network between port 1 and port 2; when the sixth transistor 302, the seventh transistor 303, the eleventh transistor 307, and the twelfth transistor 308 are turned on, the remaining transistors are turned off. At this time, a signal path is formed between port 1 and port 4 of the double-pole double-throw switch, and the signal between other ports is cut off. The fourth inductor 309, the seventh inductor 312, the turn-off parasitic capacitance of the ninth transistor 305, and the turn-off parasitic capacitance of the tenth transistor 306 form a T-type matching network between port 1 and port 4; When the fifth transistor 301, the sixth transistor 302, the ninth transistor 305, and the tenth transistor 306 are turned on, the remaining transistors are turned off. At this time, a signal path is formed between port No. 3 and port No. 4 of the double-pole double-throw switch, and the signal between other ports is cut off. The sixth inductor 311, the seventh inductor 312, the turn-off parasitic capacitance of the eleventh transistor 307, and the turn-off parasitic capacitance of the twelfth transistor 308 form a T-type matching network between port No. 3 and port No. 4; when the fifth transistor 301, the eighth transistor 304, the eleventh transistor 307, and the twelfth transistor 308 are turned on, the remaining transistors are turned off. At this time, a signal path is formed between port No. 3 and port No. 2 of the double-pole double-throw switch, and the signal between other ports is cut off. The fifth inductor 310, the sixth inductor 311, the turn-off parasitic capacitance of the ninth transistor 305, and the turn-off parasitic capacitance of the tenth transistor 306 form a T-type matching network between port No. 3 and port No. 2.

[0027] In this embodiment, the fourth circuit section 400 is the same as the third circuit section 300 .

[0028] In this embodiment, when the fifth circuit 500, the sixth circuit 600, and the seventh circuit 700 are used as delay modules, each delay module includes a plurality of cascaded delay units, and the delay unit includes a large-range delay circuit and a small-range delay circuit; the fifth circuit 500 includes one delay unit, the sixth circuit 600 includes two cascaded delay units, and the seventh circuit 700 includes four cascaded delay units; the large-range delay circuits of the delay units in each delay module are connected in sequence, and the small-range delay circuits are connected in sequence; In this embodiment, the fifth circuit 500 includes a minimum delay unit. Figure 4 , Figure 4A schematic diagram of the structure of the fifth circuit 500 provided in an embodiment of the present application, wherein the fifth circuit 500 includes an eighth inductor 501, a ninth inductor 502, a first capacitor 503, a second capacitor 504, a third capacitor 505, a first transmission line 506, a second transmission line 507, a fourth capacitor 508, and a first resistor 509.

[0029] One end of the eighth inductor 501 serves as port a and is grounded through the first capacitor 503. The other end of the eighth inductor 501 is connected to one end of the ninth inductor 502. One end of the ninth inductor 502 is grounded through the second capacitor 504. The other end of the ninth inductor 502 is grounded through the third capacitor 505. The other end of the ninth inductor 502 serves as port b. One end of the first transmission line 506 serves as port c. The other end of the first transmission line 506 is grounded through the fourth capacitor 508 and the first resistor 509. The other end of the first transmission line 506 is connected to one end of the second transmission line 507. The other end of the second transmission line 507 serves as port d. The fourth capacitor 508 and the first resistor 509 constitute an attenuation network, and the attenuation thereof increases with increasing frequency, so as to achieve consistent gain-frequency characteristics of small-range delay and large-range delay.

[0030] In each minimum delay unit, port a and port b serve as two ports at one end, and port c and port d serve as two ports at the other end.

[0031] The eighth inductor 501, the ninth inductor 502, the first capacitor 503, the second capacitor 504, and the third capacitor 505 form an artificial transmission line, the characteristic impedance of the artificial transmission line is the port impedance, and a large range of delay from port a to port b is achieved, and the delay is determined by the electrical length of the artificial transmission line; the first transmission line 506, the second transmission line 507, the fourth capacitor 508, and the first resistor 509 form a T-type transmission network, the characteristic impedance of the first transmission line 506 and the second transmission line 507 is the port impedance, and a small range of delay from port c to port d is achieved, and the delay is determined by the total electrical length of the first transmission line 506 and the second transmission line 507; the electrical length of the artificial transmission line is greater than the total electrical length of the first transmission line 506 and the second transmission line 507; the delay difference between port a to port b and port c to port d is the adjustable delay accuracy of the delay line circuit.

[0032] For the large-range delay from port a to port b, due to the limitation of the inductance quality factor, the artificial transmission line will introduce a certain insertion loss, and the insertion loss increases with the increase of frequency; for the small-range delay from port c to port d, since the total electrical length of the first transmission line 506 and the second transmission line 507 is less than the electrical length of the artificial transmission line, the insertion loss of the transmission line does not increase significantly with the increase of frequency; therefore, the gain difference between the large-range delay path and the small-range delay path in the low-frequency band is small, and the gain difference between the large-range delay path and the small-range delay path in the high-frequency band is large, resulting in poor consistency of the circuit under different delay states. The present invention adds a fourth capacitor 508 and a first resistor 509 to the small-range delay path. By adjusting the characteristic impedance of the transmission line and the capacitance of the fourth capacitor, the small-range delay path can still achieve good impedance matching. The series capacitors and resistors will introduce frequency-related losses, with smaller losses in the low-frequency band and larger losses in the high-frequency band. Ultimately, the gain-frequency characteristics of the small-range delay path and the large-range delay path are consistent, which greatly reduces the calibration complexity of the circuit in system applications and can expand the instantaneous bandwidth of the system.

[0033] In this embodiment, the sixth circuit 600 is composed of two fifth circuits 500 in cascade, that is, it includes two minimum delay units, the large-scale delay path is composed of two artificial transmission lines in series, and the small-scale delay path is composed of two T-type transmission networks in series.

[0034] In this embodiment, the seventh circuit 700 is composed of four fifth circuits 500 in cascade, that is, it includes four minimum delay units; the large-scale delay path is composed of four artificial transmission lines in series, and the small-scale delay path is composed of four T-type transmission networks in series.

[0035] Please refer to Figure 6 , Figure 7 , Figure 8 , Fig. 9 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 This is the simulation result diagram of the switch type delay line circuit example. Figure 6 The delay simulation results under eight conditions show that in the 5-35GHz frequency band, the delay range reaches 56ps and the delay accuracy reaches 8ps; Figure 7 The simulation results of delay-added amplitude modulation show that the maximum gain difference between different delay states is less than 2dB in the 5-35GHz frequency band; Figure 8 , Fig. 9 They are the input reflection coefficient and the output reflection coefficient under eight delay states respectively. In the 5-35GHz frequency band, both the input and output reflection coefficients are below -10dB.

[0036] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0037] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A switch type delay line circuit, characterized in that: include: The first circuit (100) is used as a single-pole double-throw switch, one port at one end is used as the radio frequency input / output port RF1 of the delay line circuit, and the other two ports are connected to the first delay module; N delay modules and N-1 double-pole double-throw switches are arranged in series at intervals, one end of the first delay module is connected to the two ports at the other end of the first circuit 100, and the other end of the first delay module is connected to one end of the first double-pole double-throw switch, and so on, until the other end of the N-1 double-pole double-throw switch is connected to one end of the N delay module, and the other end of the N delay module is connected to the second circuit 200; to achieve an adjustable delay of N bits; The second circuit (200) serves as a single-pole double-throw switch, with two ports at one end connected to the other end of the Nth delay module, and one port at the other end serving as a radio frequency input / output port RF2 of the delay line circuit.

2. A switch type delay line circuit according to claim 1, characterized in that: In the direction from the RF input / output port RF1 to the RF input / output port RF2, the delay module includes a number of delay units with the same structure, and the number of delay units increases in geometric progression, with a ratio of 2. The first delay module is provided with 1 delay unit, and the Nth delay module is provided with 2 delay units. N-1 A delay unit is provided to realize an adjustable delay of N bits.

3. A switch type delay line circuit according to claim 2, characterized in that: The delay unit is provided with a large-range delay circuit and a small-range delay circuit. The electrical length of the large-range delay circuit is greater than the electrical length of the small-range delay circuit. In the delay line circuit, the large-range delay circuits are connected in sequence, and the small-range delay circuits are connected in sequence.

4. A switch type delay line circuit according to claim 2, characterized in that: The delay unit structure comprises an eighth inductor (501), a ninth inductor (502), a first capacitor (503), a second capacitor (504), a third capacitor (505), a first transmission line (506), a second transmission line (507), a fourth capacitor (508), and a first resistor (509); One end of the eighth inductor (501) serves as port a and is grounded via the first capacitor (503); the other end of the eighth inductor (501) is connected to one end of the ninth inductor (502); one end of the ninth inductor 502 is grounded via the second capacitor (504); the other end of the ninth inductor (502) is grounded via the third capacitor (505); the other end of the ninth inductor (502) serves as port b; one end of the first transmission line (506) serves as port c; the other end of the first transmission line (506) is grounded via the fourth capacitor (508) and the first resistor (509); the other end of the first transmission line 506 is connected to one end of the second transmission line (507); the other end of the second transmission line (507) serves as port d; The eighth inductor (501), the ninth inductor (502), the first capacitor (503), the second capacitor (504), and the third capacitor (505) form an artificial transmission line to achieve a large-range delay from port a to port b; the first transmission line (506), the second transmission line (507), the fourth capacitor (508), and the first resistor (509) form a T-type transmission network to achieve a small-range delay from port c to port d; the fourth capacitor (508) and the first resistor (509) form an attenuation network; wherein the electrical length of the artificial transmission line is greater than the total electrical length of the first transmission line (506) and the second transmission line (507).

5. A switch type delay line circuit according to claim 1, characterized in that: The first circuit (100) serves as a single-pole double-throw switch, comprising a first transistor (101), a second transistor (102), a third transistor (103), a fourth transistor (104), a first inductor (105), a second inductor (106) and a third inductor (107); One end of the first inductor (105) is connected to the drain of the third transistor (103) and the drain of the fourth transistor (104), and the other end of the first inductor (105) serves as port No. 1 of the single-pole double-throw switch, and port No. 1 serves as the radio frequency input / output port RF1 of the delay line circuit; one end of the second inductor (106) is connected to the drain of the first transistor (101) and the source of the third transistor (103), and the other end of the second inductor (106) serves as port No. 2 of the single-pole double-throw switch; One end of the third inductor (107) is connected to the drain of the second transistor (102) and the source of the fourth transistor (104); the other end of the third inductor (107) serves as port No. 3 of the single-pole double-throw switch; ports No. 2 and No. 3 of the single-pole double-throw switch serve as two ports at the other end and are connected to the first delay module; the source of the first transistor (101) is grounded, and the source of the second transistor (102) is grounded; the gate of the first transistor (101) is connected to the gate of the fourth transistor (104). voltage, the gate of the second transistor (102) and the gate of the third transistor (103) are connected Voltage.

6. A switch type delay line circuit according to claim 5, characterized in that: When the first transistor (101) and the fourth transistor (104) are turned off, the second transistor (102) and the third transistor (103) are turned on, and at this time, a signal path is formed between port 1 and port 2 of the single-pole double-throw switch, and the signal between other ports is cut off, and the first inductor (105), the second inductor (101), the turn-off parasitic capacitance of the first transistor (101), and the turn-off parasitic capacitance of the fourth transistor (104) form a T-type matching network between port 1 and port 2; when the first transistor (101) and the fourth transistor (104) are turned on, the second transistor (102) and the third transistor (103) are turned off, and at this time, a signal path is formed between port 1 and port 3 of the single-pole double-throw switch, and the signal between other ports is cut off, and the first inductor (105), the third inductor (107), the turn-off parasitic capacitance of the second transistor (102), and the turn-off parasitic capacitance of the third transistor (103) form a T-type matching network between port 1 and port 3.

7. A switch type delay line circuit according to claim 5, characterized in that: The second inductor (106) and the third inductor (107) have the same inductance value; the first transistor (101) and the fourth transistor (104) have the same size and the same gate control voltage; the second transistor (102) and the third transistor (103) have the same size and the same gate control voltage; the gate control voltages of the first transistor (101) and the third transistor (103) are opposite, and the gate control voltages of the second transistor (102) and the fourth transistor (104) are opposite.

8. A switch type delay line circuit according to claim 1, characterized in that: The double-pole double-throw switch structure comprises a fifth transistor (301), a sixth transistor (302), a seventh transistor (303), an eighth transistor (304), a ninth transistor (305), a tenth transistor (306), an eleventh transistor (307), a twelfth transistor (308), a fourth inductor (309), a fifth inductor (310), a sixth inductor (311), and a seventh inductor (312); One end of the fourth inductor (309) is connected to the drain of the fifth transistor (301), the source of the ninth transistor (305), and the source of the eleventh transistor (307), and the other end of the fourth inductor (309) serves as port No. 1 of the double-pole double-throw switch; One end of the fifth inductor (310) is connected to the drain of the sixth transistor (302), the drain of the ninth transistor (305), and the drain of the twelfth transistor (308); the other end of the fifth inductor 310 serves as port 2 of the double-pole double-throw switch; port 1 and port 2 of the double-pole double-throw switch serve as two ports at one end of the double-pole double-throw switch; one end of the sixth inductor (311) is connected to the drain of the seventh transistor (303), the source of the tenth transistor (306), and the source of the twelfth transistor (308); the other end of the sixth inductor (311) serves as port 3 of the double-pole double-throw switch; one end of the seventh inductor (312) is connected to the drain of the eighth transistor (304), the drain of the tenth transistor (306), and the source of the twelfth transistor (308); The drain of the first transistor (307) is connected, the other end of the seventh inductor (312) serves as the No. 4 port of the double-pole double-throw switch, and the No. 3 port and the No. 4 port of the double-pole double-throw switch serve as the two ports of the other end of the double-pole double-throw switch; the sources of the fifth transistor (301), the sixth transistor (302), the seventh transistor (303), and the eighth transistor (304) are grounded; and the gates of the fifth transistor (301), the sixth transistor (302), the seventh transistor (303), the eighth transistor (304), the ninth transistor (305), the tenth transistor (306), the eleventh transistor (307), and the twelfth transistor (308) are respectively connected to the gate control signal to realize the four conduction channels of the double-pole double-throw switch.

9. A switch type delay line circuit according to claim 8, characterized in that: When the seventh transistor (303), the eighth transistor (304), the ninth transistor (305), and the tenth transistor (306) are turned on, the remaining transistors are turned off, and a signal path is formed between port No. 1 and port No. 2 of the double-pole double-throw switch, and the signals between the other ports are cut off. The fourth inductor (309), the fifth inductor (310), the turn-off parasitic capacitance of the eleventh transistor (307), and the turn-off parasitic capacitance of the twelfth transistor (308) form a T-type matching network between port No. 1 and port No. 2; when the sixth transistor (302), the seventh transistor (303), the eleventh transistor (307), and the twelfth transistor (308) are turned on, the remaining transistors are turned off, and a signal path is formed between port No. 1 and port No. 4 of the double-pole double-throw switch, and the signals between the other ports are cut off. The fourth inductor (309), the seventh inductor (312), the turn-off parasitic capacitance of the ninth transistor (305), and the turn-off parasitic capacitance of the tenth transistor (306) form a T-type matching network between port No. 1 and port No.

4. When the fifth transistor (301), the sixth transistor (302), the ninth transistor (305) and the tenth transistor (306) are turned on, the remaining transistors are turned off, and a signal path is formed between the No. 3 port and the No. 4 port of the double-pole double-throw switch, and the signal between the other ports is cut off. The sixth inductor (311), the seventh inductor (312), the turn-off parasitic capacitance of the eleventh transistor (307) and the turn-off parasitic capacitance of the twelfth transistor (308) form a T-type matching network between the No. 3 port and the No. 4 port; When the fifth transistor (301), the eighth transistor (304), the eleventh transistor (307) and the twelfth transistor (308) are turned on, the remaining transistors are turned off, and a signal path is formed between the No. 3 port and the No. 2 port of the double-pole double-throw switch, and the signal between the other ports is cut off. The fifth inductor (310), the sixth inductor (311), the turn-off parasitic capacitance of the ninth transistor (305) and the turn-off parasitic capacitance of the tenth transistor (306) form a T-type matching network between the No. 3 port and the No. 2 port.

10. A switch type delay line circuit according to claim 8, characterized in that: The fourth inductor (309), the fifth inductor (310), the sixth inductor (311), and the seventh inductor (312) have the same inductance value; the fifth transistor (301), the sixth transistor (302), the seventh transistor (303), and the eighth transistor (304) have the same size; and the ninth transistor (305), the tenth transistor (306), the eleventh transistor (307), and the twelfth transistor (308) have the same size.

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