Data receiving method based on DMA (Direct Memory Access) circular linked list

Abstract

The invention relates to a scene that a processor uses serial port communication in the field of electronic payment, in particular to a data receiving method based on a DMA (Direct Memory Access) circular linked list, which adopts a DMA function and a hardware linked list function of a security processor to receive serial port data; meanwhile, making a chain table of DMA into a circular chain table by software; in order to receive the data with the uncertain length, monitoring the data change in the DMA at fixed time intervals by using a timer, and judging that the receiving is completed when the data received by the DMA in the fixed time is not changed any more; on the premise that hardware is not changed, the load capacity of the CPU is enhanced. And the DMA is used for automatically receiving data, so that the interruption triggering frequency is reduced. According to the method, the cyclic linked list is matched with the timer function, so that the CPU load can be effectively reduced, the receiving of data with variable lengths can be supported, and the memory consumption is also reduced. On the premise of avoiding replacing a processor with higher performance and avoiding increasing the cost, the beneficial effects of ensuring the efficiency and not sacrificing the stability are realized.

Description

Technical Field

[0001] The present invention relates to a scenario in which a processor in the field of electronic payment uses serial port communication, and in particular to a data receiving method based on a DMA circular linked list. Background Art

[0002] In payment terminal devices, a dual-chip architecture is usually used to improve system performance and security. The dual-chip architecture generally consists of an application processor and a security processor, where the security processor is responsible for performing security-related operations such as encryption and decryption, user authentication, key management, etc. In the payment industry, due to the importance of security and data privacy, the security processor plays a key role in the entire system.

[0003] As payment terminal functions become increasingly complex, the workload of security processors is also gradually increasing. This is especially true for the communication part with the application processor. Usually, the communication between the two processors is transmitted via serial ports, and the security processor is responsible for receiving and processing serial port data. However, as the complexity of payment terminal equipment requirements increases, the security processor needs to process a large amount of serial port communication data and other security transactions at the same time. This high-load task poses a great challenge to the performance of the security processor, especially how to ensure efficient reception and processing of data during serial port communication, which has become an important factor affecting the overall performance of the terminal.

[0004] At present, the industry usually adopts the method of sacrificing some performance in exchange for stable serial port data, or replacing the processor with a more powerful one, but this undoubtedly increases the cost.

[0005] Therefore, how to efficiently receive and process serial port data without replacing high-performance processing and ensure the normal operation of the security processor has become a technical problem that needs to be solved in payment terminal equipment. Summary of the invention

[0006] The object of the present invention is to provide a data receiving method based on a DMA circular linked list, thereby solving the above-mentioned problems existing in the prior art.

[0007] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] The DMA function and hardware linked list function of the security processor are used to receive serial port data. At the same time, the DMA linked list is made into a circular linked list in software. In order to receive data of indefinite length, a timer is used to monitor the data changes in DMA at fixed intervals. When the received data of DMA no longer changes within a fixed time, the reception is judged to be completed.

[0009] Specifically, a data receiving method based on a DMA circular linked list uses the DMA function and hardware linked list function of a security processor to receive serial port data; at the same time, the DMA linked list is made into a circular linked list in software; in order to receive data of uncertain length, a timer is used to monitor the data changes in the DMA at fixed intervals, and the reception is judged to be completed when the DMA received data within the fixed time no longer changes; specifically, it includes: a parsing process initialization process, a DMA initialization process, a DMA interrupt processing process, and a timer interrupt processing process.

[0010] Preferably, the analysis process initialization process specifically includes:

[0011] A1, the master serial port performs initialization actions, configures the serial port IO, baud rate, and interrupt mode;

[0012] A2, the master initializes the global variable, where dwLastData = -1; this global variable is used to record the length of the data received last time, the valid range is between 1 and DMA_RXBUF_SIZE, and the value assigned is -1, which is an invalid value;

[0013] Create a circular buffer queue named ringbuf to store data exported from DMA;

[0014] A3, the master controller assigns initial values ​​to the structure st_DmaUart;

[0015] A4, the master configures the DMA function register and performs initialization operations;

[0016] A5, the master enables the serial port interrupt and turns on the DMA function of the serial port, that is, configures the receiving channel of the serial port into DMA;

[0017] A6, the master configures the timer and adjusts the interrupt trigger interval of the timer to the preset value;

[0018] A7, exit the current process;

[0019] The characters in the above process have the following meanings:

[0020] DMA_RXBUF_SIZE: macro definition, indicating the maximum length of serial port DMA reception.

[0021] Preferably, in step A3, the master controller assigns an initial value to the structure st_DmaUart, which specifically includes:

[0022] isRecvOverFlow is set to 0. When DMA receives full data, that is, after receiving the DMA_RXBUF_SIZE length, the value will increase by 1, indicating the number of times.

[0023] The initial value of dwRxNum is 0, which indicates the length of the received data in the current DMA buffer.

[0024] The pbRxBuf pointer points to the global array uartbuf1, which represents the receive buffer area and is used to record the destination address of DMA reception;

[0025] The value of dwRxLastNum is 0, which indicates the length of the data received by the last DMA, that is, the length of the data received in the previous node in the linked list;

[0026] The pbRxLastBuf pointer points to address 0, which indicates the address of the buffer in the previous node in the DMA linked list. Because the linked list has not been established yet after the initialization, the current address is 0.

[0027] Preferably,

[0028] The preset value in step A6 is 2 ms.

[0029] Preferably, the DMA initialization process specifically includes:

[0030] B1, master DMA channel disabled;

[0031] B2, the master configures DMA interrupts, turns on TC interrupts and EC interrupts; TC indicates that a receive completion interrupt has occurred, and EC indicates that an error interrupt has occurred;

[0032] B3, the master initializes the linked list structure. Currently, the structure array gst_DMALLI is defined. The array has two elements. The value of gst_DMALLI[0] is as follows:

[0033] gst_DMALLI[0].SrcAddr = (uint32_t)RXDATA; that is, the source address points to the serial port receive data register;

[0034] gst_DMALLI[0].DestAddr = (uint32_t)uartbuf1; that is, the destination buffer address points to the initial position of the global data uartbuf1;

[0035] gst_DMALLI[0].NextLLIAddr=(uint32_t)&gst_DMALLI[1];that is, point the next address of the linked list to the address of structure 1;

[0036] gst_DMALLI[0].CTRL = DMA_GetConfigRegVal(UART_DMA_CH)|DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable;

[0037] B4, the master controller assigns the value of structure gst_DMALLI[1] as follows:

[0038] gst_DMALLI[1].SrcAddr = (uint32_t)RXDATA; that is, the source address points to the serial port receive data register;

[0039] gst_DMALLI[1].DestAddr = (uint32_t)uartbuf2; that is, the destination buffer address points to the initial position of the global data uartbuf2;

[0040] gst_DMALLI[1].NextLLIAddr=(uint32_t)&gst_DMALLI[0];that is, point the next address of the linked list to the address of structure 0;

[0041] gst_DMALLI[1].CTRL = DMA_GetConfigRegVal(UART_DMA_CH)|DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable;

[0042] B5, the master writes the variable in gst_DMALLI[0] into its own register:

[0043] UART_DMA_CH->SRCADDR=gst_DMALLI[0].SrcAddr; that is, set the source address of DMA;

[0044] UART_DMA_CH->DESTADDR=gst_DMALLI[0].DestAddr; Set the destination address of DMA;

[0045] UART_DMA_CH->CONTROL = gst_DMALLI[0].CTRL; Set the DMA control register, which contains the maximum length of reception;

[0046] UART_DMA_CH->LLI=gst_DMALLI[0].NextLLIAddr;Set the address of the next configuration structure in the DMA linked list;

[0047] B6, master enables DMA interface;

[0048] The characters in the above process have the following meanings:

[0049] RXDATA: The address of the master hardware serial port receiving data;

[0050] uartbuf1, uartbuf2: the names of the global arrays opened, which are used as the destination addresses of DMA.

[0051] Preferably, the processing process of the DMA interrupt specifically includes:

[0052] C1, the master determines whether TC in the interrupt register is set to 1. If so, C2 in this process is executed, otherwise C7 in this process is executed;

[0053] C2, the master determines whether st_DmaUart.isRecvOverFlow>=1 is established, that is, whether the number of reception completions exceeds 2 times. If yes, C3 in this process is executed, otherwise C5 in this process is executed;

[0054] C3, the master controller disables the DMA interface, that is, turns off the DMA function;

[0055] C4, the master sets st_DmaUart.isErrOccur to 1, indicating that an error has occurred in the current DMA reception;

[0056] C5, the master exports the status of the current register to the global structure; because after the TC interrupt is triggered, the chip will automatically load the content of the next node in the linked list; export the content of the current register to the st_DmaUart structure for use in the timer interrupt;

[0057] C6, the master clears the interrupted reception completion flag;

[0058] C7, the master determines whether the DMA error interrupt EC is set, if so, execute C8 in this process, otherwise execute C9 in this process;

[0059] C8, the master sets st_DmaUart.isErrOccur to 1, indicating that an error occurred in DMA reception;

[0060] C9, the master clears the error flag of the interrupt;

[0061] C10, exit the current process.

[0062] Preferably, the specific assignment process of exporting the content of the current register to the st_DmaUart structure is as follows:

[0063] st_DmaUart.pbRxBuf=(uint8_t*)(UART_DMA_CH->DESTADDR) assigns the address of the current cached data to the global structure for subsequent data export;

[0064] st_DmaUart.dwRxNum=0;Clear the current record data length;

[0065] st_DmaUart.pbRxLastBuf=

[0066] (uint8_t*)(((DMA_LLI_TypeDef*)(UART_DMA_CH->LLI))->DestAddr); Assign the used cache address to the global structure for subsequent data export;

[0067] st_DmaUart.dwRxLastNum = DMA_RXBUF_SIZE; because the current switch is made after the reception is completed, the current value is the maximum value received;

[0068] st_DmaUart.isRecvOverFlow++; the number of completed receptions is incremented by one.

[0069] Preferably, the interrupt processing flow of the timer specifically includes:

[0070] D0, the master defines the local variable dwCurrData;

[0071] D1, the master determines whether st_DmaUart.isRecvOverFlow==1 is true, if so, execute D2 in this process, otherwise execute D6 in this process;

[0072] D2, the master determines st_DmaUart.isRecvOverFlow = 0, that is, the number of receptions is cleared to 0;

[0073] D3, the master fills the data received by DMA into RINGBUF, that is, copies the data starting from the st_DmaUart.pbRxLastBuf address DMA_RXBUF_SIZE long data to RINGBUF;

[0074] D4, the master rewrites dwLastData to -1, that is, assigns the variable to an invalid value;

[0075] D5, the master obtains the remaining address of the buffer BUF in the DMA, that is, dwCurrData = DMA_GetCurrDataCounter (UART_DMA_CH); because the master counts in reverse order, the count value decreases from the maximum count value as the received data increases; jump to D12 in this process to execute;

[0076] D6, the master determines whether st_DmaUart.isRecvOverFlow==2 is true, if so, execute D7 in this process, otherwise execute D5 in this process;

[0077] D7, the master sets st_DmaUart.isRecvOverFlow to 0;

[0078] D8, the master fills the data received by DMA into RINGBUF, that is, the data starting from the st_DmaUart.pbRxBuf address is copied to RINGBUF by DMA_RXBUF_SIZE length of data;

[0079] D9, the master fills the data received by DMA into RINGBUF, that is, the data starting from the st_DmaUart.pbRxLastBuf address is copied to the data of DMA_RXBUF_SIZE length to RINGBUF;

[0080] D10, the master rewrites dwLastData to -1, that is, assigns the variable to an invalid value;

[0081] D11, the master controller turns on the DMA channel function and jumps to D5 in this process;

[0082] D12, the master determines whether dwCurrData == DMA_RXBUF_SIZE is true, that is, whether the length of the currently received data is equal to the maximum length. If so, it means that no data has been received, and jumps to D20 in this process;

[0083] D13, the main control determines whether dwCurrData==dwLastData is true. If true, it means that the data has not changed within the fixed interval period, and it is determined that the data reception is completed;

[0084] D14 master disables DMA, that is, turns off the DMA function;

[0085] D15, the master obtains the count length in DMA, converts DMA_RXBUF_SIZE-dwCurrData to get the received data length, and assigns it to st_DmaUart.dwRxNum;

[0086] D16, the master fills the data received in DMA into RINGBUF, that is, fills the data of st_DmaUart.dwRxNum length into RINGBUF starting from st_DmaUart.pbRxBuf address;

[0087] D17, the master reconfigures the DMA source address RXDATA, the destination address st_DmaUart.pbRxBuf and the maximum length DMA_RXBUF_SIZE received by DMA; it is used to reset the DMA receive buffer pointer to zero;

[0088] D18, the master enables the DMA interface, that is, turns on the DMA function and jumps to D20 in this process;

[0089] D19, the master sets dwLastData = dwCurrData, that is, updates the current received data length to the historical record variable;

[0090] D20, end the current process;

[0091] The characters in the above process have the following meanings:

[0092] dwCurrData: used to record the length of the cached data in the current DMA.

[0093] The beneficial effects of the present invention are:

[0094] The data receiving method based on DMA circular linked list of the present invention can enhance the load capacity of CPU under the premise of ensuring that the hardware remains unchanged. DMA is used to automatically receive data to reduce the frequency of interrupt triggering. The use of circular linked list in conjunction with the timer function can effectively reduce the CPU load while supporting the reception of data of indefinite length, while also reducing memory consumption. The technical solution of the present invention achieves the beneficial effect of ensuring efficiency without sacrificing stability under the premise of avoiding the replacement of a more powerful processor to avoid increasing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0095] Figure 1 It is a schematic diagram of the process of the master control initialization configuration in the present invention;

[0096] Figure 2 It is a schematic diagram of the process of the master initializing DMA in the present invention;

[0097] Figure 3 It is a schematic diagram of the processing flow in the DMA interruption of the present invention;

[0098] Figure 4 This is the processing flow in the timer interruption of the present invention. DETAILED DESCRIPTION

[0099] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following Figure 1-4 It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0100] The following examples are explained in more detail:

[0101] (I) Analysis process initialization process:

[0102] The characters represent the following meanings:

[0103] DMA_RXBUF_SIZE: The macro definition indicates the maximum length of the serial port DMA reception, and the current program configuration is 1024 bytes.

[0104] A1, the master serial port is initialized to configure the serial port IO, baud rate, interrupt mode, etc.

[0105] A2, the master initializes the global variable. dwLastData = -1; this global variable is used to record the length of the last received data, the valid range is between 1 and DMA_RXBUF_SIZE, and the value assigned is -1, which is an invalid value

[0106] Create a circular buffer queue named ringbuf to store data exported from DMA.

[0107] A3, the master controller assigns initial values ​​to the structure st_DmaUart.

[0108] The value of isRecvOverFlow is 0. When the DMA reception is full, that is, after the DMA_RXBUF_SIZE length is received, the value will be increased by 1, indicating the number of times.

[0109] The initial value of dwRxNum is 0, which indicates the length of the received data in the current DMA buffer.

[0110] The pbRxBuf pointer points to the global array uartbuf1, which represents the receive buffer area and is used to record the destination address of DMA reception.

[0111] The value of dwRxLastNum is 0, which indicates the length of the data received by the last DMA, that is, the length of the data received in the previous node in the linked list.

[0112] The pbRxLastBuf pointer points to address 0, which indicates the address of the buffer in the previous node in the DMA linked list. Because the linked list has not been established yet due to the initialization, the current address is 0.

[0113] A4, the master configures the DMA function register and performs initialization operations. For more detailed steps, please refer to the description of process 2.

[0114] A5, the master enables the serial port interrupt and turns on the DMA function of the serial port, that is, configures the serial port's receiving channel into DMA.

[0115] A6, the master configures the timer and adjusts the interrupt trigger interval of the timer to 2ms.

[0116] A7, exit the current process

[0117] (II) DMA initialization process:

[0118] The characters represent the following meanings:

[0119] RXDATA: The address of the master hardware serial port receiving data.

[0120] uartbuf1, uartbuf2: the names of the global arrays opened, which are used as the destination addresses of DMA.

[0121] B1, master DMA channel disabled (subsequent configuration can only be performed after the DMA function is turned off, otherwise the configuration data cannot be written into the register).

[0122] B2, the master configures DMA interrupts and turns on TC interrupts and EC interrupts. TC indicates that a receive completion interrupt has occurred, and EC indicates that an error interrupt has occurred.

[0123] B3, the master initializes the linked list structure. Currently, the structure array gst_DMALLI is defined, and the array has two elements. The value of gst_DMALLI[0] is as follows:

[0124] gst_DMALLI[0].SrcAddr=(uint32_t)RXDATA; that is, the source address points to the serial port receive data register.

[0125] gst_DMALLI[0].DestAddr = (uint32_t)uartbuf1; that is, the destination buffer address points to the initial position of the global data uartbuf1.

[0126] gst_DMALLI[0].NextLLIAddr=(uint32_t)&gst_DMALLI[1];that is, point the next address of the linked list to the address of structure 1.

[0127] gst_DMALLI[0].CTRL = DMA_GetConfigRegVal(UART_DMA_CH) | DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable.

[0128] B4, the master controller assigns the value of structure gst_DMALLI[1] as follows:

[0129] gst_DMALLI[1].SrcAddr=(uint32_t)RXDATA; that is, the source address points to the serial port receive data register.

[0130] gst_DMALLI[1].DestAddr = (uint32_t)uartbuf2; that is, the destination buffer address points to the initial position of the global data uartbuf2.

[0131] gst_DMALLI[1].NextLLIAddr=(uint32_t)&gst_DMALLI[0];that is, point the next address of the linked list to the address of structure 0.

[0132] gst_DMALLI[1].CTRL=DMA_GetConfigRegVal(UART_DMA_CH)|DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable.

[0133] B5, the master writes the variable in gst_DMALLI[0] into its own register

[0134] UART_DMA_CH->SRCADDR=gst_DMALLI[0].SrcAddr; that is, set the source address of DMA

[0135] UART_DMA_CH->DESTADDR=gst_DMALLI[0].DestAddr;Set DMA destination address

[0136] UART_DMA_CH->CONTROL=gst_DMALLI[0].CTRL; Set the DMA control register, which contains the maximum length of reception.

[0137] UART_DMA_CH->LLI=gst_DMALLI[0].NextLLIAddr; Set the address of the next configuration structure in the DMA linked list.

[0138] B6, master enables DMA interface.

[0139] (III) How to handle DMA interrupts:

[0140] Symbol definition:

[0141] C1, the master determines whether TC in the interrupt register is set to 1. If so, it executes C2, otherwise it executes C7.

[0142] C2, the master determines whether st_DmaUart.isRecvOverFlow>=1 is true, that is, whether the number of reception completions exceeds 2 times. If yes, execute C3, otherwise execute C5

[0143] C3, the master controller disables the DMA interface, that is, turns off the DMA function.

[0144] C4, the master sets st_DmaUart.isErrOccur to 1, indicating that an error has occurred in the current DMA reception.

[0145] C5, the master exports the current register status to the global structure. Because after the TC interrupt is triggered, the chip will automatically load the content of the next node in the linked list. The current register content is exported to the st_DmaUart structure for use in the timer interrupt. The specific assignment process is as follows:

[0146] st_DmaUart.pbRxBuf = (uint8_t*)(UART_DMA_CH->DESTADDR) assigns the address of the current cached data to the global structure for subsequent data export.

[0147] st_DmaUart.dwRxNum=0;Clear the current record data length. st_DmaUart.pbRxLastBuf=(uint8_t*)(((DMA_LLI_TypeDef*)(UART_DMA_CH->LLI))->DestAddr);Assign the used buffer address to the global structure for subsequent data export.

[0148] st_DmaUart.dwRxLastNum = DMA_RXBUF_SIZE; because the current switch is made after the reception is completed, the current value is the maximum value received.

[0149] st_DmaUart.isRecvOverFlow++; the number of completed receptions is incremented by one.

[0150] C6, the master clears the interrupted reception completion flag;

[0151] C7, the master determines whether the DMA error interrupt EC is set, if so, execute C8, otherwise execute C9.

[0152] C8, the master sets st_DmaUart.isErrOccur to 1, indicating that an error occurred in DMA reception.

[0153] C9, the master clears the error flag of the interrupt.

[0154] C10, exit the current process.

[0155] (IV) Timer interrupt processing flow:

[0156] Symbol definition:

[0157] dwCurrData: used to record the length of the cached data in the current DMA.

[0158] D0, the master defines the local variable dwCurrData.

[0159] D1, the master determines whether st_DmaUart.isRecvOverFlow==1 is true, if so, execute D2, otherwise execute D6.

[0160] D2, the master determines that st_DmaUart.isRecvOverFlow=0 and clears the number of times received.

[0161] D3, the master fills the data received by DMA into RINGBUF, that is, copies the data starting from the st_DmaUart.pbRxLastBuf address and the length of DMA_RXBUF_SIZE to RINGBUF.

[0162] D4, the master rewrites dwLastData to -1; that is, the variable is assigned an invalid value

[0163] D5, the master obtains the remaining address of the buffer BUF in the DMA, that is, dwCurrData = DMA_GetCurrDataCounter (UART_DMA_CH); because the master counts in reverse order, the count value will decrease from the maximum count value as the received data increases. Jump to D12 for execution.

[0164] D6, the master determines whether st_DmaUart.isRecvOverFlow==2 is true, if so, execute D7, otherwise execute D5.

[0165] D7, the master sets st_DmaUart.isRecvOverFlow to 0.

[0166] D8, the master fills the data received by DMA into RINGBUF, that is, copies the data starting from the st_DmaUart.pbRxBuf address and the length of DMA_RXBUF_SIZE to RINGBUF.

[0167] D9, the master fills the data received by DMA into RINGBUF, that is, copies the data starting from the st_DmaUart.pbRxLastBuf address and the length of DMA_RXBUF_SIZE to RINGBUF.

[0168] D10, the master rewrites dwLastData to -1; that is, the variable is assigned an invalid value

[0169] D11, the master control turns on the DMA channel function and jumps to D5

[0170] D12, the master determines whether dwCurrData == DMA_RXBUF_SIZE is true, that is, whether the length of the currently received data is equal to the maximum length. If true, it means that no data has been received. Jump to D20.

[0171] D13, the main control determines whether dwCurrData==dwLastData is established. If it is established, it means that the data has not changed within the fixed interval period, and it is determined that the data reception is completed.

[0172] The D14 master controller disables DMA, that is, turns off the DMA function.

[0173] D15, the master obtains the count length in DMA, converts (DMA_RXBUF_SIZE-dwCurrData) to get the received data length, and assigns it to st_DmaUart.dwRxNum.

[0174] D16, the master fills the data received in DMA into RINGBUF, that is, fills the data of st_DmaUart.dwRxNum length into RINGBUF starting from the address of st_DmaUart.pbRxBuf.

[0175] D17, the master reconfigures the DMA source address RXDATA, the destination address st_DmaUart.pbRxBuf and the maximum length of DMA reception DMA_RXBUF_SIZE. It is used to reset the DMA receive buffer pointer to zero.

[0176] D18, the master enables the DMA interface, that is, turns on the DMA function. Jump to D20.

[0177] D19, the master sets dwLastData = dwCurrData, that is, updates the current received data length to the historical record variable.

[0178] D20, end the current process.

[0179] The present invention utilizes the linked list function of the chip. When the data reception in a node is completed, the configuration structure of the next node is automatically loaded, and the configuration parameters in the structure are written into the hardware register. These parameters include the source address, the destination address, the node address of the next linked list and the receiving length of DMA, so as to autonomously switch the received data to the new address. This mechanism is used to change the linked list into a circular linked list. At this time, only data of a preset fixed length can be received.

[0180] By using a timer to query data within a fixed time, the effect of receiving data of variable length can be achieved.

[0181] This reduces CPU load (reduced number of interrupt inputs) and improves data processing efficiency and ease of use.

[0182] By adopting the above technical solution disclosed in the present invention, the following beneficial effects are obtained:

[0183] The data receiving method based on DMA circular linked list of the present invention can enhance the load capacity of CPU under the premise of ensuring that the hardware remains unchanged. DMA is used to automatically receive data to reduce the frequency of interrupt triggering. The use of circular linked list in conjunction with the timer function can effectively reduce the CPU load while supporting the reception of data of indefinite length, while also reducing memory consumption. The technical solution of the present invention achieves the beneficial effect of ensuring efficiency without sacrificing stability under the premise of avoiding the replacement of a more powerful processor to avoid increasing costs.

[0184] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications should also be considered as the scope of protection of the present invention.

Claims

1. A data receiving method based on a DMA circular linked list, characterized in that: The DMA function and hardware linked list function of the security processor are used to receive serial port data; at the same time, the DMA linked list is made into a circular linked list in software; in order to receive data of uncertain length, a timer is used to monitor the data changes in DMA at fixed intervals, and the reception is judged to be completed when the DMA received data no longer changes within a fixed time; specifically, it includes: the analysis process initialization process, the DMA initialization process, the DMA interrupt processing process, and the timer interrupt processing process.

2. The data receiving method based on DMA circular linked list according to claim 1, characterized in that: The initialization process of the analysis process specifically includes: A1, the master serial port performs initialization actions, configures the serial port IO, baud rate, and interrupt mode; A2, the master initializes the global variable, where dwLastData = -1; this global variable is used to record the length of the last received data, the valid range is between 1 and DMA_RXBUF_SIZE, and the value assigned is -1, which is an invalid value; Create a circular buffer queue named ringbuf to store data exported from DMA; A3, the master controller assigns initial values ​​to the structure st_DmaUart; A4, the master configures the DMA function register and performs initialization operations; A5, the master enables the serial port interrupt and turns on the DMA function of the serial port, that is, configures the receiving channel of the serial port into DMA; A6, the master configures the timer and adjusts the interrupt trigger interval of the timer to the preset value; A7, exit the current process; The characters in the above process have the following meanings: DMA_RXBUF_SIZE: macro definition, indicating the maximum length of serial port DMA reception.

3. The data receiving method based on DMA circular linked list according to claim 2, characterized in that: In step A3, the master controller assigns an initial value to the structure st_DmaUart, which specifically includes: isRecvOverFlow is set to 0. When DMA receives full data, that is, after receiving the DMA_RXBUF_SIZE length, the value will increase by 1, indicating the number of times. The initial value of dwRxNum is 0, which indicates the length of the received data in the current DMA buffer. The pbRxBuf pointer points to the global array uartbuf1, which represents the receive buffer area and is used to record the destination address of DMA reception; The value of dwRxLastNum is 0, which indicates the length of the data received by the last DMA, that is, the length of the data received in the previous node in the linked list; The pbRxLastBuf pointer points to address 0, which indicates the address of the buffer in the previous node in the DMA linked list. Because the linked list has not been established yet after the initialization, the current address is 0.

4. The data receiving method based on DMA circular linked list according to claim 2, characterized in that: The preset value in step A6 is 2 ms.

5. The data receiving method based on DMA circular linked list according to claim 1, characterized in that: The DMA initialization process specifically includes: B1, master DMA channel disabled; B2, the master configures DMA interrupts, turns on TC interrupts and EC interrupts; TC indicates that a receive completion interrupt has occurred, and EC indicates that an error interrupt has occurred; B3, the master initializes the linked list structure. Currently, the structure array gst_DMALLI is defined. The array has two elements. The value of gst_DMALLI[0] is as follows: gst_DMALLI[0].SrcAddr = (uint32_t)RXDATA; that is, the source address points to the serial port receive data register; gst_DMALLI[0].DestAddr = (uint32_t)uartbuf1; that is, the destination buffer address points to the initial position of the global data uartbuf1; gst_DMALLI[0].NextLLIAddr=(uint32_t)&gst_DMALLI[1];that is, point the next address of the linked list to the address of structure 1; gst_DMALLI[0].CTRL = DMA_GetConfigRegVal(UART_DMA_CH)|DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable; B4, the master controller assigns the value of structure gst_DMALLI[1] as follows: gst_DMALLI[1].SrcAddr = (uint32_t)RXDATA; that is, the source address points to the serial port receive data register; gst_DMALLI[1].DestAddr = (uint32_t)uartbuf2; that is, the destination buffer address points to the initial position of the global data uartbuf2; gst_DMALLI[1].NextLLIAddr=(uint32_t)&gst_DMALLI[0];that is, point the next address of the linked list to the address of structure 0; gst_DMALLI[1].CTRL = DMA_GetConfigRegVal(UART_DMA_CH)|DMA_RXBUF_SIZE; Write the length and DMA configuration to the control register variable; B5, the master writes the variable in gst_DMALLI[0] into its own register: UART_DMA_CH->SRCADDR=gst_DMALLI[0].SrcAddr; that is, set the source address of DMA; UART_DMA_CH->DESTADDR=gst_DMALLI[0].DestAddr; Set the destination address of DMA; UART_DMA_CH->CONTROL = gst_DMALLI[0].CTRL; Set the DMA control register, which contains the maximum length of reception; UART_DMA_CH->LLI=gst_DMALLI[0].NextLLIAddr;Set the address of the next configuration structure in the DMA linked list; B6, master enables DMA interface; The characters in the above process have the following meanings: RXDATA: The address of the master hardware serial port receiving data; uartbuf1, uartbuf2: the names of the global arrays opened, which are used as the destination addresses of DMA.

6. The data receiving method based on DMA circular linked list according to claim 1, characterized in that: The processing process of the DMA interrupt specifically includes: C1, the master determines whether TC in the interrupt register is set to 1. If so, C2 in this process is executed, otherwise C7 in this process is executed; C2, the master determines whether st_DmaUart.isRecvOverFlow>=1 is established, that is, whether the number of reception completions exceeds 2 times. If yes, C3 in this process is executed, otherwise C5 in this process is executed; C3, the master controller disables the DMA interface, that is, turns off the DMA function; C4, the master sets st_DmaUart.isErrOccur to 1, indicating that an error has occurred in the current DMA reception; C5, the master exports the status of the current register to the global structure; because after the TC interrupt is triggered, the chip will automatically load the content of the next node in the linked list; export the content of the current register to the st_DmaUart structure for use in the timer interrupt; C6, the master clears the interrupted reception completion flag; C7, the master determines whether the DMA error interrupt EC is set, if so, execute C8 in this process, otherwise execute C9 in this process; C8, the master sets st_DmaUart.isErrOccur to 1, indicating that an error occurred in DMA reception; C9, the master clears the error flag of the interrupt; C10, exit the current process.

7. The data receiving method based on DMA circular linked list according to claim 6, characterized in that: The specific assignment process of exporting the contents of the current register to the st_DmaUart structure is as follows: st_DmaUart.pbRxBuf=(uint8_t*)(UART_DMA_CH->DESTADDR) assigns the address of the current cached data to the global structure for subsequent data export; st_DmaUart.dwRxNum=0;Clear the current record data length; st_DmaUart.pbRxLastBuf= (uint8_t*)(((DMA_LLI_TypeDef*)(UART_DMA_CH->LLI))->DestAddr); Assign the used cache address to the global structure for subsequent data export; st_DmaUart.dwRxLastNum = DMA_RXBUF_SIZE; because the current switch is made after the reception is completed, the current value is the maximum value received; st_DmaUart.isRecvOverFlow++; the number of completed receptions is incremented by one.

8. The data receiving method based on DMA circular linked list according to claim 1, characterized in that: The interrupt processing flow of the timer specifically includes: D0, the master defines the local variable dwCurrData; D1, the master determines whether st_DmaUart.isRecvOverFlow==1 is true, if so, execute D2 in this process, otherwise execute D6 in this process; D2, the master determines st_DmaUart.isRecvOverFlow = 0, that is, the number of receptions is cleared to 0; D3, the master fills the data received by DMA into RINGBUF, that is, the data starting from the address of st_DmaUart.pbRxLastBuf is copied to RINGBUF by DMA_RXBUF_SIZE length; D4, the master rewrites dwLastData to -1, that is, assigns the variable to an invalid value; D5, the master obtains the remaining address of the buffer BUF in the DMA, that is, dwCurrData = DMA_GetCurrDataCounter (UART_DMA_CH); because the master counts in reverse order, the count value decreases from the maximum count value as the received data increases; jump to D12 in this process to execute; D6, the master determines whether st_DmaUart.isRecvOverFlow==2 is true, if so, execute D7 in this process, otherwise execute D5 in this process; D7, the master sets st_DmaUart.isRecvOverFlow to 0; D8, the master fills the data received by DMA into RINGBUF, that is, the data starting from the st_DmaUart.pbRxBuf address is copied to RINGBUF by DMA_RXBUF_SIZE length of data; D9, the master fills the data received by DMA into RINGBUF, that is, the data starting from the address of st_DmaUart.pbRxLastBuf is copied to RINGBUF by DMA_RXBUF_SIZE length; D10, the master rewrites dwLastData to -1, that is, assigns the variable to an invalid value; D11, the master controller turns on the DMA channel function and jumps to D5 in this process; D12, the master determines whether dwCurrData == DMA_RXBUF_SIZE is true, that is, whether the length of the currently received data is equal to the maximum length. If so, it means that no data has been received, and jumps to D20 in this process; D13, the main control determines whether dwCurrData == dwLastData is true. If true, it means that the data has not changed within the fixed interval period, and it is determined that the data reception is completed; D14 master disables DMA, that is, turns off the DMA function; D15, the master obtains the count length in DMA, converts DMA_RXBUF_SIZE-dwCurrData to get the received data length, and assigns it to st_DmaUart.dwRxNum; D16, the master fills the data received in DMA into RINGBUF, that is, fills the data of st_DmaUart.dwRxNum length into RINGBUF starting from st_DmaUart.pbRxBuf address; D17, the master reconfigures the DMA source address RXDATA, the destination address st_DmaUart.pbRxBuf and the maximum length DMA_RXBUF_SIZE received by DMA; it is used to reset the DMA receive buffer pointer to zero; D18, the master enables the DMA interface, that is, turns on the DMA function and jumps to D20 in this process; D19, the master sets dwLastData = dwCurrData, that is, updates the current received data length to the historical record variable; D20, end the current process; The characters in the above process have the following meanings: dwCurrData: used to record the length of the cached data in the current DMA.

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