Semiconductor device and preparation method thereof
The semiconductor device preparation method addresses parasitic BJT current issues by preventing metal silicide formation and reusing the body contact hole as a source contact hole, ensuring efficient carrier management and improved radiation resistance.
Patent Information
- Application Number
- CN202411305337.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-19
- Publication Date
- 2024-12-27
AI Technical Summary
Semiconductor devices experience performance degradation due to the formation of large currents in parasitic BJTs when exposed to radiation, such as space radiation, which affects their functionality and service life.
A semiconductor device preparation method involving the formation of a gate trench, gate oxide layer, and polysilicon gate, followed by creating a body lightly doped region, source and heavily doped regions, and a barrier layer to prevent metal silicide formation, with a body contact hole reused as a source contact hole to manage carrier flow during radiation exposure.
This method prevents metal silicide contamination, forms a deep hole contact window for rapid carrier transmission, and avoids large parasitic BJT currents, thereby maintaining device performance and extending service life.
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Figure CN119208140A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] With the rapid development of semiconductor devices represented by MOSFET devices, semiconductor devices are now widely used. MOSFET devices include source, drain and body regions. The source and drain regions are of the same doping type, while the body region is of a different doping type from the source and drain regions. The source, drain and body regions constitute a parasitic BJT, where the body region is the base region of the parasitic BJT. When a semiconductor device is exposed to radiation, such as space radiation, a large current will be formed in the parasitic BJT, affecting the performance of the semiconductor device. Summary of the invention
[0003] The invention provides a semiconductor device and a preparation method thereof, so as to improve the performance of the semiconductor device.
[0004] According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising:
[0005] Providing a semiconductor substrate, and forming a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench on the semiconductor substrate;
[0006] forming a body lightly doped region in the semiconductor substrate;
[0007] forming a source region and a heavily doped region on the upper surface of the body lightly doped region;
[0008] forming a barrier layer on the upper surface of the heavily doped region;
[0009] After forming the barrier layer, depositing a metal layer and annealing, so that metal silicide is formed on the surfaces of the polysilicon gate and the source region;
[0010] After forming the metal silicide, the unreacted metal layer is removed, and the heavily doped region is etched to form a body contact hole; wherein, along the arrangement direction of the gate trench and the lightly doped region, the width of the body contact hole is smaller than the width of the heavily doped region before etching; and the body contact hole is reused as a source contact hole.
[0011] Optionally, along the vertical direction, the maximum depth of the body contact hole is less than the maximum depth of the body lightly doped region.
[0012] Optionally, providing a semiconductor substrate, and forming a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench on the semiconductor substrate, comprising:
[0013] Providing the semiconductor substrate; wherein the semiconductor substrate comprises an N-type substrate or a P-type substrate;
[0014] Performing epitaxial growth on the semiconductor substrate to form an epitaxial layer;
[0015] A gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed in the epitaxial layer.
[0016] Optionally, a source region and a heavily doped region are formed on the upper surface of the body lightly doped region, respectively, including:
[0017] A source region and a heavily doped region are respectively formed on the upper surface of the body lightly doped region, and a drain region is formed on a side of the gate trench away from the body lightly doped region; wherein, along the arrangement direction of the gate trench and the body lightly doped region, the width of the heavily doped region before etching is greater than or equal to the width of the drain region, and the width of the drain region is greater than the width of the source region.
[0018] Optionally, after forming a body lightly doped region in the semiconductor substrate and before forming a source region and a body heavy doped region on the upper surface of the body lightly doped region, the method further includes:
[0019] A transition region is formed in the body lightly doped region; wherein the carrier concentration of the transition region is less than the carrier concentration of the body heavy doped region, and greater than the carrier concentration of the body lightly doped region;
[0020] A source region and a heavily doped region are formed on the upper surface of the lightly doped region, respectively, including:
[0021] A source region and a heavily doped region are respectively formed on the upper surface of the transition region, so that both the source region and the heavily doped region are connected to the lightly doped region through the transition region.
[0022] Optionally, removing the unreacted metal layer and etching the heavily doped region to form a body contact hole comprises:
[0023] removing the unreacted metal layer;
[0024] After removing the unreacted metal layer, forming an insulating dielectric layer on the surface of the semiconductor substrate;
[0025] forming a photoresist on the surface of the insulating dielectric layer, and patterning the photoresist;
[0026] The area not covered by the photoresist is etched to form the body contact hole in the insulating dielectric layer, and then the heavily doped region is further etched using the insulating dielectric layer as a mask to form the body contact hole in the heavily doped region.
[0027] According to another aspect of the present invention, there is provided a semiconductor device, which is manufactured by the above-mentioned method for manufacturing a semiconductor device;
[0028] The semiconductor device comprises:
[0029] Semiconductor substrate;
[0030] A gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench; the gate oxide layer wraps the polysilicon gate;
[0031] A body region is arranged adjacent to the gate trench in a horizontal direction; wherein the body region includes a heavily doped region and a lightly doped region, the heavily doped region and the source region are arranged above the lightly doped region, and the source region is located between the heavily doped region and the gate trench; the body region also includes a body contact hole, the body contact hole is reused as a source contact hole, and the source region is connected to the body contact hole through the heavily doped region.
[0032] Optionally, the semiconductor substrate includes an N-type substrate or a P-type substrate;
[0033] The semiconductor device further comprises an epitaxial layer located above the semiconductor substrate; the gate trench and the body region are both located on the upper surface of the epitaxial layer.
[0034] Optionally, the semiconductor device further comprises: a drift region located in the semiconductor substrate; the gate trench and the body region are both located in the drift region;
[0035] The drift region is also provided with a drain region and a shallow trench isolation; the drain region, the shallow trench isolation, the gate trench and the body region are arranged adjacent to each other in sequence along the horizontal direction; and a field plate grid is also arranged above the shallow trench isolation.
[0036] Optionally, the semiconductor substrate further includes an isolation layer, a buried layer, and a deep well region connected to the buried layer;
[0037] The isolation layer is located below the drift region; the buried layer is located below the isolation layer; the deep well region extends in a vertical direction and is connected to the buried layer; the deep well region is not connected to the drift region.
[0038] The technical solution of the present invention can avoid the formation of metal silicide on the upper surface of the heavily doped region before depositing the metal layer. In this way, when the heavily doped region is subsequently etched, metal silicide contamination can be avoided, which leads to production line contamination and cross contamination. In addition, by etching the heavily doped region to form a body contact hole, a deep hole contact window can be formed in the body region. When a large number of carriers are generated in the body region due to radiation, a large number of carriers can be quickly transmitted to the body contact hole through the deep hole contact window, thereby avoiding the generation of large parasitic BJT current, causing damage to the semiconductor device and affecting the service life. In addition, by reusing the body contact hole as a source contact hole, when a large number of carriers are generated in the body region due to radiation, a large number of carriers can be avoided from flowing out through the source region, causing the parasitic BJT to be turned on, resulting in an amplification effect and resulting in the generation of large parasitic BJT current.
[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0041] Figure 1 is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention;
[0042] Figure 2 It is a structural schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present invention;
[0043] Figure 3 It is a structural schematic diagram of a manufacturing process of another semiconductor device provided by an embodiment of the present invention;
[0044] Figure 4 It is a structural schematic diagram of a manufacturing process of another semiconductor device provided by an embodiment of the present invention;
[0045] Figure 5 It is a structural schematic diagram of a manufacturing process of another semiconductor device provided by an embodiment of the present invention;
[0046] Figure 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;
[0047] Figure 7It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.
[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0050] Figure 1 It is a flow chart of a method for preparing a semiconductor device provided by an embodiment of the present invention. This embodiment can be applied to preparing a planar laterally diffused metal oxide semiconductor (LDMOS) device, and can also be applied to preparing a vertical high-voltage device. Figure 2 is a schematic diagram of a semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 1 and Figure 2 , the method comprising:
[0051] 1001. Provide a semiconductor substrate, and form a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench on the semiconductor substrate.
[0052] For example, a gate trench 02 may be etched in the semiconductor substrate 01 first, and the depth of the gate trench 02 may be greater than or equal to 0.3 μm and less than or equal to 3 μm; then a gate oxide layer 11 may be formed on the inner wall of the gate trench 02, and the thickness of the gate oxide layer 11 may be 20-1000 nm; finally, polysilicon may be filled in the gate trench 02 to form a polysilicon gate 12. The gate oxide layer 11 wraps the polysilicon gate 12 and exposes the upper surface of the polysilicon gate 12; "upper" refers to the side direction of the semiconductor substrate 01 used to prepare the semiconductor device.
[0053] 1002. Form a body lightly doped region in a semiconductor substrate.
[0054] Specifically, ion implantation and diffusion are performed in a preset region on the upper surface of the semiconductor substrate 01 to form a body lightly doped region 21. The preset region is adjacent to the gate trench 02, so that the body lightly doped region 21 can be arranged adjacent to the gate trench 02 in a horizontal direction; the horizontal direction refers to a direction parallel to the plane where the semiconductor substrate 01 is located, which can also be called a lateral direction.
[0055] 1003. Form a source region and a heavily doped region on the upper surface of the body lightly doped region.
[0056] The source region 30 and the heavily doped region 22 are arranged in a horizontal direction and are both located above the body lightly doped region 21. The heavily doped region 22 and the body lightly doped region 21 constitute the body region 20. In an optional embodiment, along the arrangement direction of the source region 30 and the heavily doped region 22, the width of the heavily doped region 22 before etching is greater than the width of the source region 30.
[0057] In another embodiment, the source region 30 is located between the heavily doped region 22 and the gate trench 02 , and along the horizontal direction, the gate trench 02 , the source region 30 and the heavily doped region 22 are arranged adjacent to each other in sequence.
[0058] For example, taking the prepared semiconductor device as an NMOS transistor, the source region 30 may include an N-type heavily doped region N+, the body lightly doped region 21 may include a P-type lightly doped region PB, and the body heavy doped region 22 may include a P-type heavily doped region P+.
[0059] 1004. Form a barrier layer on the upper surface of the heavily doped region.
[0060] Among them, the blocking layer 101 includes but is not limited to film layer structures such as selective absorption buried oxide layer and photoresist. The blocking layer 101 is used to shield and cover the upper surface of the heavily doped area 22 to ensure that the upper surface of the heavily doped area 22 does not participate in the reaction in subsequent processes.
[0061] 1005. After forming the barrier layer, deposit a metal layer and anneal, so that metal silicide is formed on the surfaces of the polysilicon gate and the source region.
[0062] The resistivity of the metal silicide 60 is lower than that of the polysilicon gate 12 and the source region 30 . The metal silicide 60 can form an ohmic contact between the polysilicon gate 12 and the source region 30 and the metal electrode, thereby reducing the contact resistance.
[0063] For example, a whole metal layer may be deposited and then annealed so that the metal layer can react with silicon to form metal silicide 60, while non-silicon regions such as silicon oxide do not react with the metal layer. After metal silicide 60 is formed in a part of the region, other unreacted metal layers may be removed, for example, by using a metal cleaning agent to clean off the unreacted metal layer while retaining the metal silicide 60.
[0064] In an optional embodiment, in order to avoid the metal layer from reacting with the area of the semiconductor substrate 01 that does not need to be conductive to form a metal silicide 60 and cause misconduction, before forming the gate trench 02, a shallow trench isolation STI can be formed on the surface of the semiconductor substrate 01 that does not require etching and ion implantation. Alternatively, before forming the gate trench 02, a local oxidation can be performed on the surface of the semiconductor substrate 01 that does not require etching and ion implantation to form a local oxidation isolation (not shown in the figure).
[0065] It should be noted that Figure 2 The shallow trench isolation STI is only used to isolate semiconductor devices to avoid the formation of metal silicide 60 between different devices, which may cause misconductance. The shallow trench isolation STI is adjacent to the gate trench 02 is only a feasible implementation method. In other feasible implementation methods, the shallow trench isolation STI and the gate trench 02 may not be adjacent.
[0066] 1006. After forming metal silicide, remove the unreacted metal layer, and etch the heavily doped area to form a body contact hole; wherein, along the arrangement direction of the gate trench and the lightly doped area, the width of the body contact hole is smaller than the width of the heavily doped area before etching; the body contact hole is reused as a source contact hole.
[0067] Exemplarily, when the metal cleaning agent is used to clean the unreacted metal layer, the barrier layer 101 on the surface of the heavily doped region 22 can be removed at the same time. By etching the heavily doped region 22, a deep hole contact window can be formed in the body region 20, that is, a body contact hole H-2 in the body region 20. Along the arrangement direction of the gate trench 02 and the body lightly doped region 21, the width of the body contact hole H-2 is smaller than the width of the heavily doped region 22 before etching, so that the heavily doped region 22 is not completely etched away, and part of the heavily doped region 22 close to the source region 30 is retained. In an optional embodiment, along the arrangement direction of the source region 30 and the heavily doped region 22, the width of the heavily doped region 22 after etching is greater than or equal to the width of the source region 30.
[0068] In other embodiments, when the unreacted metal layer is cleaned with a metal cleaning agent, only the unreacted metal layer may be removed without removing the barrier layer 101 . When the heavily doped region 22 is subsequently etched, the barrier layer 101 may be etched first.
[0069] The body contact hole H-2 is reused as the source contact hole H-3, so that the source region 30 can be connected to the source contact hole H-3 through the heavy doped region 22, and there is no need to set the source contact hole H-3 above the source region 30. In an optional embodiment, when forming the barrier layer 101, the barrier layer 101 can cover the heavy doped region 22 and the source region 30, so that the metal silicide 60 will not be formed on the upper surface of the heavy doped region 22 and the source region 30.
[0070] In addition, a gate contact hole H-1 may be formed on the upper surface of the metal silicide 60 on the surface of the polysilicon gate 12. The gate contact hole H-1 may be formed in the same process as the body contact hole H-2, or the gate contact hole H-1 may be formed in a different process from the body contact hole H-2, which is not limited in the embodiment of the present invention.
[0071] According to an embodiment of the present invention, a barrier layer is formed on the upper surface of the heavily doped region before depositing the metal layer, thereby avoiding the formation of metal silicide on the upper surface of the heavily doped region. In this way, when the heavily doped region is subsequently etched, metal silicide contamination can be avoided, which leads to production line contamination and cross contamination. In addition, a body contact hole is formed by etching the heavily doped region, so that a deep hole contact window can be formed in the body region. When a large number of carriers are generated in the body region due to radiation, a large number of carriers can be quickly transmitted to the body contact hole through the deep hole contact window, thereby avoiding the generation of a large parasitic BJT current, causing damage to the semiconductor device and affecting the service life. In addition, by reusing the body contact hole as a source contact hole, when a large number of carriers are generated in the body region due to radiation, a large number of carriers can be avoided from flowing out through the source region, causing the parasitic BJT to be turned on, resulting in an amplification effect and causing a large parasitic BJT current to be generated.
[0072] Optional, continue to refer to Figure 2 , along the vertical direction, the maximum depth DH of the body contact hole H- 2 is less than the maximum depth D- 2 of the body lightly doped region 21 .
[0073] The vertical direction refers to the direction perpendicular to the plane where the semiconductor substrate 01 is located, which can also be called the longitudinal direction. The maximum depth DH of the body contact hole H-2 refers to the depth of the side surface of the body contact hole H-2 close to the semiconductor substrate 01 extending downward compared to the upper surface of the body region 20; the maximum depth D-2 of the body lightly doped region 21 refers to the depth of the side surface of the body lightly doped region 21 close to the semiconductor substrate 01 extending downward compared to the upper surface of the body region 20; wherein, the upper surface of the body region 20 is also the upper surface of the heavy doped region 22, and the maximum depth of the body lightly doped region 21 is also the maximum depth of the body region 10, and "down" refers to the direction opposite to the side of the semiconductor substrate 01 used to prepare semiconductor devices.
[0074] Specifically, the maximum depth DH of the body contact hole H-2 is less than the maximum depth D-2 of the body lightly doped region 21, that is, the body region 20 is disposed below the body contact hole H-2, and at least the body lightly doped region 21 is disposed below the body contact hole H-2. In this way, it can be avoided that when the body contact hole H-2 receives an electrical signal, the channel current in the semiconductor device is affected, resulting in unstable electrical characteristics of the semiconductor device.
[0075] Exemplarily, the maximum depth DH of the body contact hole H- 2 may be greater than or equal to 0.3 μm and less than or equal to 3 μm; the maximum depth D- 2 of the body lightly doped region 21 is greater than DH.
[0076] In an optional embodiment, a semiconductor substrate is provided, and a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed on the semiconductor substrate, including: providing a semiconductor substrate; wherein the semiconductor substrate includes an N-type substrate or a P-type substrate; performing epitaxial growth on the semiconductor substrate to form an epitaxial layer; forming a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench in the epitaxial layer.
[0077] For example, taking the prepared semiconductor device as an NMOS transistor as an example, Figure 3 is a structural schematic diagram of another semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 3 , an N-type substrate N-sub can be provided as a semiconductor substrate 01, wherein the N-type substrate N-sub is a low-resistance substrate; epitaxy is performed on the semiconductor substrate 01 to form an N-type epitaxial layer N-epi as the epitaxial layer 201, for example, the epitaxial layer 201 can be formed first, and then the epitaxial layer 201 is formed into an N-type epitaxial layer N-epi by ion implantation and diffusion, wherein the resistivity of the N-type epitaxial layer N-epi is higher than that of the N-type substrate N-sub; then, a gate trench 02, and a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02 are formed on the upper surface of the epitaxial layer 201; finally, ion implantation and diffusion are performed on the upper surface of the epitaxial layer 201 to form a body region 20 and a source region 30, and finally a vertical semiconductor device can be obtained.
[0078] The gate (not shown in the figure) of the vertical semiconductor device can be connected to the polysilicon gate 12 through the gate contact hole H-1, and the source (not shown in the figure) can be connected to the source region 30 through the source contact hole H-3. The drain 104 is arranged below the N-type substrate N-sub, and the drain 104 is in contact with the N-type substrate N-sub. When a positive voltage is applied between the drain 104 and the source, and the voltage between the gate and the source is greater than the threshold voltage, a vertical N-type channel can be formed in the N-type epitaxial layer N-epi and turned on, and the current flows from the N-type substrate N-sub to the source region 30.
[0079] In yet another optional embodiment, Figure 4 is a structural schematic diagram of another semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 4 , a source region 30 and a heavily doped region 22 are respectively formed on the upper surface of the body lightly doped region 21, including: forming the source region 30 and the heavily doped region 22 on the upper surface of the body lightly doped region 21, and forming a drain region 40 on the side of the gate trench 02 away from the body lightly doped region 21; wherein, along the arrangement direction of the gate trench 02 and the body lightly doped region 21, the width L-2 of the heavily doped region 22 before etching is greater than or equal to the width L-4 of the drain region 40, and the width L-4 of the drain region 40 is greater than the width L-3 of the source region 30.
[0080] For example, taking the prepared semiconductor device as an NMOS transistor as an example, refer to Figure 4 , the source region 30 and the drain region 40 of the semiconductor device can be formed on the upper surface of the semiconductor substrate 01 in the same process, and the source region 30 and the drain region 40 can both include an N-type heavily doped region N+, and finally a lateral semiconductor device can be obtained. The gate (not shown in the figure) of the lateral semiconductor device can be connected to the polysilicon gate 12 through the gate contact hole H-1, the source (not shown in the figure) can be connected to the source region 30 through the source contact hole H-3, and the drain (not shown in the figure) can be connected to the drain region 40 through the drain contact hole H-4. When a positive voltage is applied between the drain and the source, and the voltage between the gate and the source is greater than the threshold voltage, a lateral N-type channel can be formed in the semiconductor substrate 01 and turned on, and the current flows from the drain region 40 to the source region 30.
[0081] Based on the above embodiments, continue to refer to Figure 4, a semiconductor substrate 01 is provided, and a gate trench 02, a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02 are formed on the semiconductor substrate 01, including: providing a semiconductor substrate 01, and performing ion implantation and diffusion on the upper surface of the semiconductor substrate 01 to form a drift region 03; etching the surface of the drift region 03 to form a first trench 105; filling the first trench 105 with an insulating material to form a shallow trench isolation STI; forming a gate trench 02 on one side of the shallow trench isolation STI, and exposing the sidewall of the shallow trench isolation STI; forming a gate oxide layer 11 on the inner wall of the gate trench 02; then forming a polysilicon gate 12 in the gate oxide layer 11, and forming a field plate gate 50 above the shallow trench isolation STI. When forming a body lightly doped region 21 in the semiconductor substrate 01, ion implantation needs to be performed on a side of the gate trench 02 away from the shallow trench isolation STI to form a body lightly doped region 21.
[0082] Exemplarily, when the prepared semiconductor device is an NMOS transistor, the drift region 03 may be an N-type drift region N-drift.
[0083] It should be noted that Figure 4 Different patterns filled in the shallow trench isolation STI and the gate oxide layer 11 only represent different structures. The shallow trench isolation STI and the gate oxide layer 11 can be made of the same material or different materials, which is not limited in the embodiment of the present invention.
[0084] Optional, continue to refer to Figure 4 After forming a body lightly doped region 21 in the semiconductor substrate 01, and before forming a source region 30 and a heavy doped region 22 on the upper surface of the body lightly doped region 21, the preparation method further includes: forming a transition region 23 in the body lightly doped region 21; wherein the carrier concentration of the transition region 23 is less than the carrier concentration of the heavy doped region 22, and greater than the carrier concentration of the body lightly doped region 21. Forming the source region 30 and the heavy doped region 22 on the upper surface of the body lightly doped region 21, respectively, includes: forming the source region 30 and the heavy doped region 22 on the upper surface of the transition region 23, respectively, so that the source region 30 and the heavy doped region 22 are connected to the body lightly doped region 21 through the transition region 23.
[0085] The doping type of the transition region 23 is the same as the doping type of the lightly doped body region 21 and the heavily doped body region 22. In the vertical direction, the maximum depth of the transition region 23 may be less than or equal to the maximum depth of the body contact hole H-2, or may be greater than the maximum depth of the body contact hole H-2, that is, the transition region 23 may be penetrated by the body contact hole H-2, or may not be penetrated by the body contact hole H-2, which is not limited in the embodiment of the present invention.
[0086] Specifically, by setting a transition region 23 between the source region 30 and the lightly doped region 21 of the body, and between the heavily doped region 22 and the lightly doped region 21 of the body, it is beneficial to increase the threshold voltage and avoid mis-conduction of the device; it is also beneficial to form ohmic contact and reduce contact resistance. When a large number of carriers are generated in the body region 20 due to radiation, a large number of carriers can be quickly extracted, thereby reducing the generation of large parasitic BJT currents.
[0087] Optional, Figure 5 is a structural schematic diagram of another semiconductor device manufacturing process provided by an embodiment of the present invention, with reference to Figure 5 , removing the unreacted metal layer, and etching the heavily doped region 22 to form a body contact hole H-2, including: removing the unreacted metal layer; after removing the unreacted metal layer, forming an insulating dielectric layer ILD on the surface of the semiconductor substrate 01; forming a photoresist PR on the surface of the insulating dielectric layer ILD, and patterning the photoresist PR; etching the area not covered by the photoresist PR to form a body contact hole H-2 in the insulating dielectric layer ILD, and then using the insulating dielectric layer ILD as a mask, continuing to etch the heavily doped region 22 to form a body contact hole H-2 in the heavily doped region 22.
[0088] Exemplarily, after removing the unreacted metal layer and the barrier layer 101 above the heavily doped region 22, an insulating dielectric layer ILD is first formed, and then a photoresist PR is formed. Then, a mask is placed above the photoresist PR, and the photoresist PR is patterned through exposure and development to expose the area to be etched. The insulating dielectric layer ILD is etched using the photoresist PR as a mask to form a body contact hole H-2 in the insulating dielectric layer ILD; then, the heavily doped region 22 is continuously etched using the insulating dielectric layer ILD as a mask to form a body contact hole H-2 in the heavily doped region 22. In this way, it is beneficial to reduce the number of times the photoresist PR needs to be formed to form a deeper body contact hole H-2, which is beneficial to reducing the process and improving production efficiency.
[0089] In an optional embodiment, after removing the unreacted metal layer and before forming the insulating dielectric layer ILD on the surface of the semiconductor substrate 01 , the process further includes: forming a silicon nitride layer (not shown) on the upper surface of the heavily doped region 22 .
[0090] The silicon nitride layer can be used as an etching stop layer.
[0091] Exemplarily, the insulating dielectric layer ILD above the heavily doped region 22 is etched using the photoresist PR as a mask, and after etching to the silicon nitride layer, the etching is switched to gas etching, for example, carbon tetrafluoride and oxygen can be used to etch the silicon nitride layer and the heavily doped region 22, and form a body contact hole H-2 in the heavily doped region 22. If the barrier layer 101 is not removed before the insulating dielectric layer ILD is formed on the surface of the semiconductor substrate 01, the gas etching can sequentially etch the silicon nitride layer, the barrier layer 101 and the heavily doped region 22.
[0092] In another optional embodiment, the insulating dielectric layer ILD is etched using the photoresist PR as a mask, and while the body contact hole H-2 is formed in the insulating dielectric layer ILD, the gate contact hole H-1, the drain contact hole H-4 and the field plate contact hole H-5 can also be formed in the same process. This is conducive to reducing the number of processes and improving production efficiency.
[0093] In another optional embodiment, the gate contact hole H-1, the drain contact hole H-4, the field plate contact hole H-5 and the body contact hole H-2 can be formed in different processes to avoid the metal silicide 60 under the gate contact hole H-1, the drain contact hole H-4 and the field plate contact hole H-5 being etched when the silicon nitride layer and the heavily doped region 22 are etched, thereby contaminating the production line.
[0094] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device. Figure 6 is a schematic diagram of a semiconductor device provided by an embodiment of the present invention, with reference to Figure 6 The semiconductor device includes: a semiconductor substrate 01; a gate trench 02, and a gate oxide layer 11 and a polysilicon gate 12 located in the gate trench 02, wherein the gate oxide layer 11 wraps the polysilicon gate 12; a body region 20, which is arranged adjacent to the gate trench 02 in a horizontal direction; wherein the body region 20 includes a heavily doped region 22 and a lightly doped region 21, and a heavily doped region 22 and a source region 30 are arranged above the lightly doped region 21, and the source region 30 is located between the heavily doped region 22 and the gate trench 02; the body region 20 also includes a body contact hole H-2, and the body contact hole H-2 is reused as a source contact hole H-3, and the source region 30 is connected to the source contact hole H-3 through the heavily doped region 22.
[0095] The semiconductor device may be a vertical semiconductor device or a horizontal semiconductor device.
[0096] Exemplarily, metal silicide 60 is disposed on the upper surfaces of the polysilicon gate 12 and the source region 30 ; and metal silicide 60 is not disposed on the upper surface of the heavily doped region 22 .
[0097] In an optional embodiment, a transition region 23 is provided between the body lightly doped region 21 and the body heavy doped region 22, and between the body lightly doped region 21 and the source region 30, and the carrier concentration of the transition region 23 is less than the carrier concentration of the body heavy doped region 22, and greater than the carrier concentration of the body lightly doped region 21. The doping type of the transition region 23 is the same as the doping type of the body lightly doped region 21 and the body heavy doped region 22.
[0098] The semiconductor device provided by the embodiment of the present invention has a body region including a body contact hole, and a deep hole contact window can be formed in the body region. When a large number of carriers are generated in the body region due to the influence of radiation, a large number of carriers can be quickly transmitted to the body contact hole through the deep hole contact window, thereby avoiding the generation of large current of the parasitic BJT, which may cause damage to the semiconductor device and shorten the service life. In addition, by reusing the body contact hole as a source contact hole, when a large number of carriers are generated in the body region due to the influence of radiation, a large number of carriers can be avoided from flowing out through the source region, causing the parasitic BJT to be turned on, resulting in an amplification effect and causing large current of the parasitic BJT to be generated.
[0099] In an optional embodiment, continue to refer to Figure 6 The semiconductor substrate 01 includes an N-type substrate or a P-type substrate; the semiconductor device also includes an epitaxial layer 201 located above the semiconductor substrate 01 ; the gate trench 02 and the body region 20 are both located on the upper surface of the epitaxial layer 201 .
[0100] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 6 , the semiconductor substrate 01 may be an N-type substrate N-sub, which is a low-resistance substrate; the epitaxial layer 201 may be an N-type epitaxial layer N-epi, which has a higher resistivity than the N-type substrate N-sub; the source region 30 includes an N-type heavily doped region N+; the body heavily doped region 22 includes a P-type heavily doped region P+; and the body lightly doped region 21 includes a P-type lightly doped region PB. The semiconductor device may be a vertical semiconductor device, and a vertical conductive channel may be formed between the source region 30 and the semiconductor substrate 01.
[0101] In yet another optional embodiment, Figure 7 is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention, referring to Figure 7 The semiconductor device further includes: a drift region 03 located in the semiconductor substrate 01, the gate trench 02 and the body region 20 are both located in the drift region 03; the drift region 03 is also provided with a drain region 40 and a shallow trench isolation STI; the drain region 40, the shallow trench isolation STI, the gate trench 02 and the body region 20 are arranged adjacent to each other in sequence along the horizontal direction; and a field plate gate 50 is also arranged above the shallow trench isolation STI.
[0102] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 7, the semiconductor substrate 01 may be P-sub; the drift region 03 may be an N-type drift region N-drift; the source region 30 and the drain region 40 may both include an N-type heavily doped region N+; the heavily doped region 22 may include a P-type heavily doped region P+; the lightly doped region 21 may include a P-type lightly doped region PB. The semiconductor device may be a lateral semiconductor device, and a lateral conductive channel may be formed between the source region 30 and the drain region 40.
[0103] Based on the above embodiment, the semiconductor substrate 01 also includes an isolation layer 04, a buried layer 05, and a deep well region 06 connected to the buried layer 05; the isolation layer 04 is located below the drift region 03; the buried layer 05 is located below the isolation layer 04; the deep well region 06 extends in a vertical direction and is connected to the buried layer 05; the deep well region 06 is not connected to the drift region 03.
[0104] For example, taking the semiconductor device as an NMOS transistor as an example, continue to refer to Figure 7 , the isolation layer 04 can be a P-type isolation layer Pbot, the buried layer 05 can be an N-type buried layer NBL, and the deep well region 06 can be an N-type deep well region DNW. The isolation layer 04 and the drift region 03 can form a reverse bias to prevent the semiconductor device from leaking to the semiconductor substrate 01; the buried layer 05 and the isolation layer 04 can form a reverse bias to prevent the semiconductor substrate 01 from leaking to the semiconductor device. Among them, the deep well region 06 can provide an electrical signal to the buried layer 05, so that the buried layer 05 and the isolation layer 04 are reverse biased, which is beneficial to reducing leakage; it is also beneficial to signal interference from the external environment and the signal stability of the semiconductor device.
[0105] In an optional embodiment, a first heavily doped region 701 is provided on the upper surface of the deep well region 06, and a first heavily doped contact hole H-701 may be provided above the first heavily doped region 701, which is conducive to providing electrical signals to the deep well region 06 and the buried layer 05. On this basis, a first well region 07 may be provided between the first heavily doped region 701 and the deep well region 06, and the deep well region 06 may be formed by multiple ion implantations, which is conducive to reducing the difficulty of implantation. When the deep well region 06 is an N-type deep well region DNW, the first well region 07 may be an N-type well region NW, and the first heavily doped region 701 may include an N-type heavily doped region N+.
[0106] In another optional embodiment, a second well region 08 and a second heavily doped region 801 located on the upper surface of the second well region 08 are further provided on the upper surface of the semiconductor substrate 01, and a second heavily doped contact hole H-801 may be further provided above the second heavily doped region 801 to provide an electrical signal to the semiconductor substrate 01, for example, to be grounded, which is beneficial to maintaining the stability of the semiconductor device. When the semiconductor substrate 01 is a P-type substrate P-sub, the second well region 08 may be a P-type well region PW, and the second heavily doped region 801 may include a P-type heavily doped region P+.
[0107] The semiconductor device provided in the embodiment of the present invention is manufactured by adopting the method for preparing the semiconductor device provided in any embodiment of the present invention, and has the functional modules and beneficial effects capable of executing the method for preparing the semiconductor device provided in the embodiment of the present invention. For the contents not fully described in the embodiment of the semiconductor device, refer to the description of the method for preparing the semiconductor device above, and will not be repeated here. Similarly, the method for preparing the semiconductor device provided in the embodiment of the present invention also has the corresponding technical features and beneficial effects of the semiconductor device. For the contents not fully described in the embodiment of the method for preparing the semiconductor device, refer to the description of the semiconductor device above, and will not be repeated here.
[0108] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A method for preparing a semiconductor device, characterized in that: include: Providing a semiconductor substrate, and forming a gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench on the semiconductor substrate; forming a body lightly doped region in the semiconductor substrate; forming a source region and a heavily doped region on the upper surface of the body lightly doped region; forming a barrier layer on the upper surface of the heavily doped region; After forming the barrier layer, depositing a metal layer and annealing, so that metal silicide is formed on the surfaces of the polysilicon gate and the source region; After forming the metal silicide, the unreacted metal layer is removed, and the heavily doped region is etched to form a body contact hole; wherein, along the arrangement direction of the gate trench and the lightly doped region, the width of the body contact hole is smaller than the width of the heavily doped region before etching; and the body contact hole is reused as a source contact hole.
2. The method for preparing a semiconductor device according to claim 1, wherein: Along the vertical direction, the maximum depth of the body contact hole is less than the maximum depth of the body lightly doped region.
3. The method for preparing a semiconductor device according to claim 1, characterized in that: A semiconductor substrate is provided, and a gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed on the semiconductor substrate, comprising: Providing the semiconductor substrate; wherein the semiconductor substrate comprises an N-type substrate or a P-type substrate; Performing epitaxial growth on the semiconductor substrate to form an epitaxial layer; A gate trench, a gate oxide layer and a polysilicon gate located in the gate trench are formed in the epitaxial layer.
4. The method for preparing a semiconductor device according to claim 1, wherein: A source region and a heavily doped region are formed on the upper surface of the lightly doped region, respectively, including: A source region and a heavily doped region are respectively formed on the upper surface of the body lightly doped region, and a drain region is formed on a side of the gate trench away from the body lightly doped region; wherein, along the arrangement direction of the gate trench and the body lightly doped region, the width of the heavily doped region before etching is greater than or equal to the width of the drain region, and the width of the drain region is greater than the width of the source region.
5. The method for preparing a semiconductor device according to claim 1, characterized in that: After forming a body lightly doped region in the semiconductor substrate and before forming a source region and a body heavy doped region on the upper surface of the body lightly doped region respectively, the method further includes: A transition region is formed in the body lightly doped region; wherein the carrier concentration of the transition region is less than the carrier concentration of the body heavy doped region, and greater than the carrier concentration of the body lightly doped region; A source region and a heavily doped region are formed on the upper surface of the lightly doped region, respectively, including: A source region and a heavily doped region are respectively formed on the upper surface of the transition region, so that both the source region and the heavily doped region are connected to the lightly doped region through the transition region.
6. The method for preparing a semiconductor device according to claim 1, wherein: Removing the unreacted metal layer and etching the heavily doped region to form a body contact hole, comprising: removing the unreacted metal layer; After removing the unreacted metal layer, forming an insulating dielectric layer on the surface of the semiconductor substrate; forming a photoresist on the surface of the insulating dielectric layer, and patterning the photoresist; The area not covered by the photoresist is etched to form the body contact hole in the insulating dielectric layer, and then the heavily doped region is further etched using the insulating dielectric layer as a mask to form the body contact hole in the heavily doped region.
7. A semiconductor device, characterized in that: Prepared by the method for preparing a semiconductor device according to any one of claims 1 to 6; The semiconductor device comprises: Semiconductor substrate; A gate trench, and a gate oxide layer and a polysilicon gate located in the gate trench; the gate oxide layer wraps the polysilicon gate; A body region is arranged adjacent to the gate trench in a horizontal direction; wherein the body region includes a heavily doped region and a lightly doped region, the heavily doped region and the source region are arranged above the lightly doped region, and the source region is located between the heavily doped region and the gate trench; the body region also includes a body contact hole, the body contact hole is reused as a source contact hole, and the source region is connected to the body contact hole through the heavily doped region.
8. The semiconductor device according to claim 7, characterized in that The semiconductor substrate includes an N-type substrate or a P-type substrate; The semiconductor device further comprises an epitaxial layer located above the semiconductor substrate; the gate trench and the body region are both located on the upper surface of the epitaxial layer.
9. The semiconductor device according to claim 7, characterized in that The semiconductor device further comprises: a drift region located in the semiconductor substrate; the gate trench and the body region are both located in the drift region; The drift region is also provided with a drain region and a shallow trench isolation; the drain region, the shallow trench isolation, the gate trench and the body region are arranged adjacent to each other in sequence along the horizontal direction; and a field plate grid is also arranged above the shallow trench isolation.
10. The semiconductor device according to claim 9, characterized in that The semiconductor substrate further comprises an isolation layer, a buried layer, and a deep well region connected to the buried layer; The isolation layer is located below the drift region; the buried layer is located below the isolation layer; the deep well region extends in a vertical direction and is connected to the buried layer; the deep well region is not connected to the drift region.