Gate circuit device structure and technology of CFET

Abstract

The invention discloses a gate circuit device structure and process of a CFET, and relates to the technical field of semiconductors, the gate circuit device structure comprises a substrate, the top of the substrate is wrapped by an N channel field effect transistor # imgabs0 # and a P channel field effect transistor # imgabs1 # which are connected in parallel through an insulating layer; the N channel field effect transistor # imgabs2 # and the P channel field effect transistor # imgabs3 # share the same source electrode S, and the N channel field effect transistor # imgabs4 # and the P channel field effect transistor # imgabs5 # share the same drain electrode D; a grid electrode # imgabs7 # of the N-channel field effect transistor # imgabs6 # and a grid electrode # imgabs9 # of the P-channel field effect transistor # imgabs8 # are separated from each other, and the grid electrode # imgabs10 # and the grid electrode # imgabs11 # which are separated from each other form a separation grid structure. According to the invention, the original planar CMOS unit is folded in half to form a three-dimensional device which is vertically stacked upwards, and the grid electrodes of the dielectric isolation P-type and N-type field effect transistor devices are adopted to form a separation grid structure, so that the planar area of CFET integration can be saved, the integration density can be improved, the channel process can be shortened, and the chip precision can be improved; and the circuit performance and the circuit design flexibility can be maintained.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a CFET gate circuit device structure and process. Background Art

[0002] Complementary field effect transistor (CFET), as a stacked semiconductor device, brings new possibilities to the design and manufacture of integrated circuits with its unique vertical complementary structure. The structural design of CFET helps to reduce parasitic effects and gradually improve the performance and power efficiency of semiconductor components. Combined with new technologies such as adaptive design and back power supply, CFET is expected to become an advanced process that may replace the gate-all-around (GAA) device in the next decade.

[0003] In CMOS design, since the gate electrical signals of most P devices and N devices are the same, and the process of the common gate structure is simple, in the current CFET research, research institutions usually use the common gate structure as the basic unit of the circuit to design the circuit. Even if the gate signals of the P device and the N device are different, it is only necessary to introduce structures such as dummy gate (DG) and diffusion break (DB).

[0004] However, the existing CFET method of introducing a false gate and a diffusion interruption structure easily causes the circuit to lose its electrical performance and the advantages of the overall area of ​​the circuit structure to a certain extent, which is not conducive to optimizing the spatial structure and circuit function of the CFET device. Summary of the invention

[0005] The object of the present invention is to provide a gate circuit device structure and process that can save the plane area of ​​CFET integration, improve the integration density, and reduce the channel process, so as to solve the problems raised in the above background technology.

[0006] On the one hand, in order to achieve the above-mentioned object, the present invention provides a gate circuit device structure of CFET, the device structure includes a substrate, the substrate as a basic support structure can be used as a base component for thin film growth and photolithography, the top of the substrate is wrapped with an N-channel field effect transistor connected in parallel through an insulating layer and P-channel FET ; The substrate is conductive and can form electron or hole carriers to realize the normal operation of electronic devices. The substrate includes silicon-based substrates, III-V compound substrates and wide bandgap substrates; Among them, the silicon-based substrate is made of silicon or sapphire. The substrate made of crystalline silicon has good thermal stability and crystal structure stability. Therefore, the crystalline silicon substrate has good chemical stability at room temperature and is not easy to react with acids, alkalis and other substances. The main components of sapphire crystal are , It is composed of three oxygen atoms and two aluminum atoms combined in the form of covalent bonds. Its crystal structure is a hexagonal lattice structure, which can improve the wear resistance of the substrate and reduce the degree of wear during the use of the substrate.

[0007] The III-V compound substrate includes III-V compounds, such as gallium nitride and indium phosphide. The chemical expression of gallium nitride is GaN; the chemical expression of indium phosphide is InP. Among them, the band gap energy of gallium nitride is about 3.4 electron volts, which is larger than the band gap energy of 1.1 electron volts of silicon and 0.67 electron volts of germanium. Therefore, gallium nitride devices can operate at higher frequencies. At the same time, combined with its luminescence performance, it can meet the use requirements of semiconductor electronic devices. CFETs using III-V compound substrates can improve the scalability of usage scenarios.

[0008] The energy band gap of indium phosphide is about 1.35 electron volts, so the energy band gap of indium phosphide is between that of silicon and gallium nitride. Substrates made of indium phosphide can be used in high-frequency, high-speed gate circuit device structures. At the same time, they have high electron mobility, which enables gate circuit devices to be transmitted faster in semiconductors under the action of electric fields, which is beneficial to improving the response speed and performance of the device. In addition, indium phosphide also has good optical properties and thermal stability, and can maintain its performance in high-temperature environments, which is beneficial to maintaining the stability of CFET gate circuit devices when used under high-temperature conditions.

[0009] When a wide bandgap material such as silicon carbide or silicon nitride is used to manufacture the substrate, since the bandgap width of silicon carbide can reach 3.2 electron volts, the substrate made of silicon carbide can operate at a higher voltage and temperature than the substrate made of crystalline silicon, which greatly improves the efficiency and energy consumption ratio of power devices. At the same time, due to the good thermal conductivity of silicon carbide materials, the heat generated in high-power applications can be effectively managed and dispersed, which is conducive to improving the reliability and life of the device; When gallium oxide is used to manufacture the substrate, the electrical breakdown strength and thermal stability of the substrate can be improved because the band gap width of gallium oxide is approximately 4.5 electron volts to 4.9 electron volts.

[0010] N-channel field effect transistor The source of the P-channel field effect transistor is connected through a wire The source electrode of the two field effect tubes is shared; Similarly, use wires to connect the N-channel field effect transistor The drain of the P-channel field effect transistor The drains are connected to each other, which can realize N-channel field effect transistor The drain of the P-channel field effect transistor Drain sharing, assuming the common drain is D; Using insulating dielectric to isolate N-channel field effect transistors P-channel FET The gates of both, where the N-channel FET The gate is , P-channel field effect transistor The gate is , separated gates With gate forming a split-gate structure; The gate With gate The electrical signals connected are different from each other, and by ensuring that the gate With gate The connected level signal is always complementary and can match the N-channel field effect transistor P-channel FET The turn-off voltage of the two makes the P-channel field effect transistor When a negative voltage is connected, the N-channel field effect transistor remains on. It also remains in the on state when connected to a high level, thereby maintaining the on state of the TG gate circuit; At the same time, when the P-channel FET When a positive voltage is connected, it will turn off and the N-channel field effect transistor When the low level is connected, the TG gate circuit is also kept in the off state, so that the TG gate circuit can be turned on in the N-channel field effect transistor. P-channel FET When receiving signals of different levels, the on or off state is maintained to realize the switching function of the TG gate circuit.

[0011] As a further solution of the present invention: N-channel field effect transistor The gate The control signal is C, P channel field effect transistor The gate The received control signal is C', and the control signal C and the control signal C' are always level signals with opposite levels; The control signal C and the control signal C' are complementary signals. When the control signal C is at a high level, the control signal C' is at a low level. When the control signal C is at a low level, the control signal C′ is at a high level.

[0012] As a further solution of the present invention: the gate With gate A dielectric layer is formed between the gate electrodes. With gate The dielectric layer is a non-conductive thin film material, and the dielectric layer is made of any one of silicon dioxide, silicon nitride, aluminum oxide, low dielectric constant dielectric and high dielectric constant material; low dielectric constant dielectrics include organic silicon, silicon fluoride and polyimide, which can effectively reduce parasitic capacitance, thereby increasing signal transmission speed and reducing power consumption; High dielectric constant dielectrics include any one of hafnium oxide, titanium oxide, zirconium oxide, tantalum pentoxide, barium strontium titanate, strontium titanate, and lead titanate, and are coated with fluorine between the separated gate structures by vacuum coating PVD or chemical vapor deposition CVD, among which atomic layer deposition ALD process is more widely used.

[0013] As a further solution of the present invention: the gate With gate Vertical stacking from bottom to top, gate With gate Cross-lead gate signals are arranged by vertically stacking N-channel field effect transistors from bottom to top. The drain of the P-channel field effect transistor The gate can reduce the spreading area of ​​the gate circuit device on the top projection plane and vertically expand the stacking height of the gate circuit device, which can reduce the parasitic effects generated during the use of the CFET device and is conducive to gradually improving the performance and power efficiency.

[0014] On the other hand, the present invention also provides a CFET gate circuit device process, comprising the following steps: Manufacturing a substrate, the substrate comprising a top silicon layer and a back substrate composited on the top silicon layer, and the support base of the gate circuit device can be formed by completing the manufacturing of the substrate; Implementing SOI process on substrate and manufacturing SOI crystalline silicon substrate, adding insulating material between top silicon and back substrate, is conducive to reducing parasitic capacitance between top silicon and back substrate. Implementing SOI process on substrate can achieve dielectric isolation inside substrate, completely eliminate parasitic latch effect in CMOS circuit, and on the other hand, is conducive to improving integration density and response speed of gate circuit devices; A mask is made by isotropically depositing a thin layer on the top of an SOI crystalline silicon substrate using chemical vapor deposition. The mask includes a substrate, a light shielding layer, and a protective film, wherein the substrate is supported by quartz or soda material; the substrate is a photosensitive blank plate that can maintain optical transmittance, reduce thermal expansion, and increase the flatness and wear resistance of the mask; The shading layer is mainly divided into hard shading layer and latex shading layer. The latex shading layer is mainly used in scenes such as PCB and touch control, while the hard shading layer is often formed by chrome plating on the substrate due to its high mechanical strength and durability of the chrome plate and its ability to form fine patterns. The protective film is a mask protective film with light resistance and high light transmittance, which can protect the mask surface; The insulating layer is etched and silicon fins and shallow trenches are formed under the mask. By wrapping the gate around the vertical silicon fins, the current flow between the source region and the drain region in the gate circuit can be controlled, so that the silicon fins can better control the channel, reduce leakage current, and improve the overall performance of the circuit composed of field effect transistors. At the same time, it is beneficial to increase the transistor density in order to better control the electrical characteristics.

[0015] A metal wire structure is pre-buried in the insulating layer and in the shallow trench isolation oxide portion to form a buried power rail BPR, wherein the metal wire structure is an initial metal wire, which is convenient for depositing the gate metal of the upper device; Manufacturing dummy gates and internal spacers. By manufacturing dummy gates, the arrangement positions of two gates in the metal separation gate structure can be marked. By manufacturing internal spacers, the capacitance of the drain and source on both sides of the device can be reduced, thereby improving the stability of the metal separation gate structure. A bottom epitaxial layer, a bottom contact layer, a top epitaxial layer and a top contact layer are sequentially grown on the insulating layer 2; Re-make the metal separation gate structure to isolate the gate signal, and lead out the gate signal separately through the contact interconnection line; Re-manufacture the metal separation gate structure and the contact interconnection line. By transforming the common gate structure of the existing CFET into a metal separation gate structure, the relative isolation of the gates between different field effect transistors can be achieved. By connecting different gates of the metal separation gate structure through the contact interconnection line, the connection of the metal separation gate structure can be achieved. The insulating layer, the bottom epitaxial layer, the bottom contact layer, the top epitaxial layer and the top contact layer are polished by chemical mechanical planarization (CMP) technology, which is beneficial to maintaining the flatness of the surface of the insulating layer.

[0016] As a further solution of the present invention: the method for isolating the gate signal comprises the following steps: Isolation Gate With gate Signal, using insulating medium as internal isolation component to isolate the gate With gate The electrical signals between them improve the stability of the metal separation gate structure; The lower gate signal is led out. The lower gate signal serves as a separate gate signal port of the metal isolation gate structure and can be used as an isolation gate to reduce the overall space of the device compared to the common gate structure.

[0017] As a further solution of the present invention: isolating the gate With gate The signal method comprises the following steps: Etch away the outer periphery of the P channel layer , which facilitates the deposition of a new layer layer As a protective layer; ALD technology is used to deposit a new layer layer As a protective layer for gate circuit devices, it enhances the external protection capability of the devices; The new layer As a gate With gate The dielectric layer, isolating the gate With gate The electrical signal between the two electrodes can reduce the parasitic effect. In the new layer The upper device gate metal is deposited on the upper device to serve as the connection and positioning end of the upper device gate interconnection line.

[0018] As a further solution of the present invention: the method for extracting the lower layer gate signal comprises the following steps: A gate-isolated mask is manufactured on top of the insulating layer. By manufacturing the mask, the optical transmittance can be maintained, the thermal expansion rate can be reduced, the flatness and wear resistance of the mask can be increased, and the ability to form fine patterns can be improved, thereby improving the light resistance of the device; A window is etched to lead out the gate electrical signal of the lower layer device, and the window can reserve a lead wire space for leading out the gate electrical signal of the lower layer device; Etch out the window layer , to open a window to facilitate maintaining the conductivity of the wiring when connecting the gate electrical signal of the lower layer device; Depositing nitride on the top of the mask as a device protection layer can improve the surface protection strength of the gate circuit device; A gate through hole is etched at one end of the mask, and a wiring channel for isolating the gate connection can be formed by etching the gate through hole.

[0019] A metal channel is etched along the gate through hole to serve as a connection path for connecting the isolation gate to facilitate rapid wiring of the isolation gate structure; A metal channel is deposited to form a deposition portion, and the deposition portion can fix the gate of the isolation gate.

[0020] As a further solution of the present invention: the method for extracting the lower layer gate signal also includes: After the deposition of the gate metal of the upper device is completed, polishing the gate metal of the upper device is beneficial to maintaining the flatness of the surface of the gate metal of the upper device; After the deposition portion is formed, polishing the deposition portion is beneficial to maintaining the flatness of the surface of the deposition portion.

[0021] As a further solution of the present invention: the method for extracting the lower layer gate signal also includes: The top of the deposition portion is connected to a contact interconnection line, wherein the contact interconnection line includes a first contact interconnection line and a second contact interconnection line, and the first contact interconnection line and the second contact interconnection line respectively lead out a gate signal for connecting the gate signal.

[0022] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention folds the original planar CMOS unit in half to form a three-dimensional device that is stacked vertically upward, and uses dielectric isolation of the gates of P-type and N-type field effect transistor devices to form a separated gate structure, which is different from the common gate structure of the traditional CFET. By decomposing the vertical common gate structure of the traditional CFET tube into two independent effective gates, the plane area of ​​CFET integration can be saved, the integration density can be improved, the channel process can be reduced, and the chip precision can be improved, which is conducive to maintaining circuit performance and circuit design flexibility.

[0023] 2. The present invention separates the gate signals of the P device and the N device by adopting a separated gate structure. The separated gate structure can be used for gate circuit devices with different gate signals, including but not limited to TG and TBUF standard library gate circuits. Any circuit designed with the basic structure of CFET can adopt the device structure and process proposed by the present invention. Therefore, the gate circuit device structure and process provided by the present invention not only have strong adaptability to various occasions, but also have strong scalability. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 This is the traditional TG gate circuit layout with common gate structure; Figure 2 The TG gate circuit layout with a separated gate in the present invention; Figure 3 is an equivalent circuit diagram of the TG gate circuit layout in the present invention; Figure 4 This is the traditional TBUF three-state gate circuit layout; Figure 5 The circuit layout of the TBUF tri-state gate with a separated gate in the present invention; Figure 6 It is the equivalent circuit diagram of the TBUF tri-state gate layout in the present invention; Figure 7 Schematic diagram of SOI crystalline silicon substrate for traditional XOR gate device; Figure 8 For the present invention Figure 7 Etch away Schematic diagram of XOR gate device of the layer; Fig. 9 For the present invention Figure 8 New Schematic diagram of XOR gate device of the layer; Fig.10 The present invention Fig. 9 Schematic diagram of an XNOR gate device in which an upper gate metal is deposited; Fig.11 For the present invention Fig.10 Schematic diagram of XNOR gate device with polished upper gate metal; Fig.12 For the present invention Fig.11 Schematic diagram of an XNOR gate device in which the gate isolation mask is fabricated; Fig.13 For the present invention Fig.12 Schematic diagram of etching of XOR gate device with gate electrical signal channel drawn out; Fig.14 For the present invention Fig.13 Etch out the window Schematic diagram of XOR gate device of the layer; Fig.15 For the present invention Fig.14 Schematic diagram of an XNOR gate device in which a nitride layer is deposited; Fig.16 For the present invention Fig.15 A mask layout having a gate through hole therein; Fig.17 For the present invention Fig.16 Schematic diagram of an XNOR gate device with a metal channel etched out; Fig.18 For the present invention Fig.17 Schematic diagram of XOR gate device after depositing metal vias; Fig.19 For the present invention Fig.18 Schematic diagram of the XOR gate device after polishing; Fig. 20 For the present invention Fig.19 Schematic diagram of gate circuit device with upper contact interconnection line added.

[0025] In the figure: 1, substrate; 2, insulation layer; 3, fin; 4, shallow trench; 5, layer 6. layer ; 7. Gate metal; 8. Mask; 9. Window; 10. layer ; 11. device protection layer; 12. gate through hole; 13. metal channel; 14. deposition part; 15. first contact interconnection line; 16. second contact interconnection line. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be understood by people with general skills in the field to which the present invention belongs. "Including" and similar words used in this article mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0027] Embodiment 1: like Figure 1 The figure shows a conventional TG gate circuit layout with a common gate structure, and provides a CFET gate circuit device structure, including N-channel field effect transistors connected in parallel. and P-channel FET ; N-channel field effect transistor The source of the P-channel field effect transistor is connected through a wire The source electrode of the two field effect tubes is shared; Similarly, use wires to connect the N-channel field effect transistor The drain of the P-channel field effect transistor The drains are connected to each other to realize N-channel field effect transistor The drain of the P-channel field effect transistor Drain sharing, assuming the common drain is D; N-channel field effect transistor and P-channel FET The surfaces of both are wrapped with an insulating layer 2, and a substrate 1 is formed at the bottom of the insulating layer 2. The substrate 1 is conductive and can be used as a base component for thin film growth and photolithography as a basic supporting structure, and can form carriers of electrons or holes to achieve normal operation of electronic devices; The substrate 1 is a silicon-based substrate, a III-V compound substrate and a wide bandgap substrate, wherein the silicon-based substrate is made of silicon or sapphire. The substrate 1 made of crystalline silicon has good thermal stability and crystal structure stability. Therefore, the crystalline silicon substrate has good chemical stability at room temperature and is not easy to react with acids, alkalis and other substances. Silicon can grow single crystals by the floating zone method, and It is composed of three oxygen atoms and two aluminum atoms bonded in a covalent bond form, and its crystal structure is a hexagonal lattice structure, which can improve the wear resistance of the substrate 1 and reduce the degree of wear of the substrate 1 during use; The III-V compound substrate includes gallium nitride and indium phosphide. The chemical expression of gallium nitride is GaN, and the chemical expression of indium phosphide is InP. Among them, gallium nitride has a wider band gap energy of about 3.4 electron volts. Compared with the band gap energy of 1.1 electron volts of crystalline silicon and the band gap energy of 0.67 electron volts of germanium, the energy band gap of gallium nitride is larger, which enables gallium nitride devices to operate at higher frequencies. By combining its luminescence performance, it can be used in the field of optoelectronic devices.

[0028] When indium phosphide is used to manufacture the substrate 1, since the energy band gap of indium phosphide is about 1.35 electron volts, the energy band gap of indium phosphide is between that of silicon and gallium nitride. When indium phosphide is used to manufacture the substrate 1, it is beneficial for the substrate 1 to adapt to the high-frequency and high-speed gate circuit device structure. At the same time, since indium phosphide has a high electron mobility, the gate circuit device can be transmitted faster in the semiconductor under the action of the electric field, thereby improving the response speed and performance of the device. In addition, indium phosphide also has good optical properties and thermal stability, and can maintain its performance stability in a high temperature environment, which is beneficial for maintaining the stability of the CFET gate circuit device when used under high temperature conditions; When a wide bandgap material such as silicon carbide or silicon nitride is used to manufacture the substrate 1, since the bandgap width of silicon carbide can reach 3.2 electron volts, the substrate 1 made of silicon carbide can operate at a higher voltage and temperature than the substrate 1 made of crystalline silicon, which greatly improves the efficiency and energy consumption ratio of the power device. At the same time, since the thermal conductivity of silicon carbide material is good, the heat generated in high-power applications can be effectively managed and dispersed, which is conducive to improving the reliability and life of the device; When gallium oxide is used to manufacture the substrate 1 , since the band gap width of gallium oxide is about 4.5 electron volts to 4.9 electron volts, the electrical breakdown strength and thermal stability of the substrate 1 can be improved.

[0029] In the existing common-gate structure circuit, two additional devices need to be added to the N device and the P device. and To match the common-gate structure, short-circuiting is usually used to make it ineffective, and additional devices are added and The overall volume of the common-gate structure circuit and the flattened area in the top-view projection are additionally enlarged.

[0030] like Figure 2 The TG gate circuit layout with a separated gate in the present invention is shown, and the N-channel field effect transistor is isolated by an insulating medium. P-channel FET The gates of both, where the N-channel FET The gate is , P-channel field effect transistor The gate is , separated gates With gate forming a split-gate structure; N-channel field effect transistor The gate P-channel FET The gate The connected electrical signals are different from each other. In the split gate, no additional devices are needed, and only a pair of split gate structures are used. The circuit function can be realized because the gate With gate The connected electrical signals are different from each other, so it is necessary to ensure that the gate With gate The input level signal is always complementary, so it can match the N-channel field effect transistor P-channel FET The turn-off voltage of the two makes the P-channel field effect transistor When a negative voltage is connected, the N-channel field effect transistor remains on. It also remains in the on state when connected to a high level, thereby maintaining the on state of the TG gate circuit; At the same time, when the P-channel FET When a positive voltage is connected, it will turn off and the N-channel field effect transistor When the low level is connected, the TG gate circuit is also kept in the off state, so that the TG gate circuit can be turned on in the N-channel field effect transistor. P-channel FET When receiving signals of different levels, the on or off state is maintained to realize the switching function of the TG gate circuit.

[0031] like Figure 3 The equivalent circuit diagram of the TG gate circuit layout in the present invention is shown, and the N-channel field effect transistor The gate The control signal is C, P channel field effect transistor The gate The received control signal is C'; The control signal C and the control signal C' are complementary signals, that is, the control signal C and the control signal C' are always level signals with opposite levels. When the control signal C is low level 0, the control signal C' is high level 1, and when the control signal C is high level 1, the control signal C' is low level, so that the N-channel field effect transistor in the TG gate circuit and P-channel FET It can be turned off or on at the same time to achieve switching control of the circuit.

[0032] Preferably, the gate With gate A dielectric layer is formed between the gate electrodes. With gate The dielectric layer is a non-conductive thin film material, and the dielectric layer can be made of any one of silicon dioxide, silicon nitride, aluminum oxide, low dielectric constant dielectric and high dielectric constant material; Among them, low dielectric constant media include organic silicon, silicon fluoride and polyimide. By using low dielectric constant media to make the dielectric layer, parasitic capacitance can be effectively reduced, thereby increasing signal transmission speed and reducing power consumption; High dielectric constant dielectrics include any one of hafnium oxide, titanium oxide, zirconium oxide, tantalum pentoxide, barium strontium titanate, strontium titanate, and lead titanate, and are coated with fluorine between the separated gate structures by vacuum coating PVD or chemical vapor deposition CVD, among which atomic layer deposition ALD process is more widely used.

[0033] Preferably, the gate With gate Vertical stacking from bottom to top, gate With gate Cross-lead gate signals are arranged by vertically stacking N-channel field effect transistors from bottom to top. The drain of the P-channel field effect transistor The gate can reduce the spreading area of ​​the gate circuit device on the top projection plane and vertically expand the stacking height of the gate circuit device, which can reduce the parasitic effects generated during the use of the CFET device and is conducive to gradually improving the performance and power efficiency.

[0034] like Figure 7 The figure shows a schematic diagram of a SOI crystalline silicon substrate of a conventional XOR gate device. The present invention provides a gate circuit device process of a CFET, including manufacturing a substrate 1, wherein the substrate 1 includes a top silicon layer and a back substrate composited on the top silicon layer. By completing the manufacturing of the substrate, a supporting base of the gate circuit device can be formed; Implementing the SOI process on substrate 1 and manufacturing an SOI crystalline silicon substrate, by adding insulating material between the top silicon and the back substrate, is beneficial to reducing the parasitic capacitance between the top silicon and the back substrate. By implementing the SOI process on substrate 1, dielectric isolation inside substrate 1 can be achieved, and the parasitic latch effect in the CMOS circuit can be completely eliminated. On the other hand, it is beneficial to improve the integration density and response speed of gate circuit devices.

[0035] like Fig.12 The present invention is shown Fig.11 A schematic diagram of an XNOR gate device in which the gate isolation mask is fabricated is shown, and a thin layer is isotropically deposited on the top of an SOI crystalline silicon substrate using chemical vapor deposition to fabricate a mask 8. The present invention uses chemical vapor deposition to isotropically deposit a thin layer on the top of an SOI crystalline silicon substrate to fabricate a mask 8; The mask 8 includes a substrate, a light shielding layer and a protective film, wherein the substrate is supported by quartz or soda material; the substrate is a photosensitive blank plate, which can maintain optical transmittance, reduce thermal expansion rate, and increase the flatness and wear resistance of the mask 8; The shading layer is mainly divided into hard shading layer and latex shading layer. The latex shading layer is mainly used in scenes such as PCB and touch control, while the hard shading layer is often formed by chrome plating on the substrate due to its high mechanical strength and durability of the chrome plate and its ability to form fine patterns. The protective film is a mask protective film with light resistance and high light transmittance, which can protect the surface of the mask 8.

[0036] like Figure 8 The present invention is shown Figure 7 Etch away Schematic diagram of an XNOR gate device of a layer, etching an insulating layer 1 and forming a fin 3 and a shallow trench 4 under a mask 8, by surrounding the gate with a vertical silicon fin 3, the current flow between the source region and the drain region in the gate circuit can be controlled, so that the silicon fin 3 can better control the channel, reduce leakage current, improve the overall performance of the circuit composed of the field effect transistor, and at the same time help to increase the transistor density and better control the electrical characteristics; A metal wire structure is embedded in the insulating layer 2 and the shallow trench 4 to isolate the oxide, forming a buried power rail BPR. The metal wire structure is an initial metal wire, and then a dummy gate and an internal spacer are manufactured. By manufacturing the dummy gate, the arrangement positions of the two gates in the metal separation gate structure can be marked. By manufacturing the internal spacer, the capacitance on both sides of the device can be reduced, and the use stability of the metal separation gate structure can be improved. A bottom epitaxial layer, a bottom contact layer, a top epitaxial layer and a top contact layer are sequentially grown on the insulating layer; this enables the field effect transistor to have a higher breakdown voltage or breakdown current processing capability, which is beneficial to improving the overall performance of the field effect transistor; The metal separation gate structure is remade to isolate the gate signal, and the gate signal is led out separately through the contact interconnection line.

[0037] By transforming the common gate structure of the existing CFET into a metal separated gate structure, the relative isolation of the gates between different field effect transistors can be achieved, and the connection of the metal separated gate structure can be achieved by connecting different gates of the metal separated gate structure through contact interconnection lines; Etch away the outer periphery of the P channel layer 5. It can make room for re-deposition layer 6.

[0038] like Fig. 9 The present invention is shown Figure 8 New Schematic diagram of the XOR gate device of the layer, using ALD technology to re-deposit a new layer layer 6. As an isolation layer; Preferably, the new layer 6 as gate With gate The dielectric layer, isolating the gate With gate The electrical signal between layer 6 As a high dielectric constant dielectric layer, it is beneficial to improve the stability of the metal separation gate structure.

[0039] like Fig.10 The present invention shown Fig. 9 Schematic diagram of an XNOR gate device in which an upper gate metal 7 is deposited. layer Depositing an upper device gate metal 7 on 6; Lead out the lower gate signal, which is a separate gate signal port of the metal isolation gate structure and can be used as an isolation gate to reduce the overall space of the device compared with the common gate structure; A gate-isolated mask 8 is manufactured on top of the insulating layer 2. By manufacturing the mask 8, the optical transmittance can be maintained, the thermal expansion coefficient can be reduced, the flatness and wear resistance of the mask 8 can be increased, and the ability to form fine patterns can be achieved, thereby improving the light resistance of the device.

[0040] like Fig.14 The present invention shown Fig.13 Etch out the window Schematic diagram of an XNOR gate device of a lower layer, a window 9 is etched to lead out a gate electrical signal of a lower layer device, and the window 9 can reserve a lead wire space for leading out the gate electrical signal of the lower layer device; Etch out window 9 layer 10, to open the window 9, so as to maintain the conductivity of the wiring when connecting the gate electrical signal of the lower layer device.

[0041] like Fig.15 The present invention is shown Fig.14Schematic diagram of an XNOR gate device with a nitride layer deposited in the middle, depositing nitride on the top of the mask 8 as a gate circuit device protection layer 11 can improve the surface protection strength of the gate circuit device.

[0042] like Fig.16 The present invention is shown Fig.15 A mask plate with a gate through hole 12 is opened in the middle, and the gate through hole 12 is etched at one end of the mask plate 8. By etching the gate through hole 12, a wiring channel for isolating the gate connection can be formed.

[0043] like Fig.13 The present invention is shown Fig.12 Schematic diagram of etching of an XOR gate device with a gate electrical signal channel drawn out, a metal channel 13 is etched along the gate through hole 12 as a connection path for connecting the isolation gate wiring, which facilitates rapid wiring of the isolation gate structure.

[0044] like Fig.17 The present invention is shown Fig.16 Schematic diagram of an XNOR gate device with a metal channel 13 etched out, wherein the metal channel 13 serves as a gate electrical signal channel to facilitate isolation gate routing.

[0045] like Fig.18 The present invention is shown Fig.17 Schematic diagram of an XNOR gate device after depositing metal through holes, wherein a metal channel 13 is deposited to form a deposition portion 14, and the deposition portion 14 can fix the gate of the isolation gate.

[0046] like Fig.11 The present invention is shown Fig.10 Schematic diagram of an XOR gate device with an upper gate metal being polished. After the upper device gate metal 7 is completed, the upper device gate metal 7 is polished to maintain the flatness of the surface of the upper device gate metal 7.

[0047] like Fig.19 The present invention is shown Fig.18 Schematic diagram of the XNOR gate device after polishing. After the deposition portion 14 is formed, the deposition portion 14 is polished, which is beneficial to maintaining the flatness of the surface of the deposition portion 14.

[0048] like Fig. 20 The present invention is shown Fig.19 A schematic diagram of a gate circuit device with an upper contact interconnect line is added. The insulating layer, the bottom epitaxial layer, the bottom contact layer, the top epitaxial layer and the top contact layer are polished using chemical mechanical planarization (CMP) technology, which is beneficial to maintaining the flatness and polishing effect of the surface of the insulating layer 2.

[0049] The top of the deposition portion 14 is connected to the contact interconnection line, which includes a first contact interconnection line 15 and a second contact interconnection line 16. The first contact interconnection line 15 and the second contact interconnection line 16 lead out gate signals respectively for connecting the gate signals.

[0050] Embodiment 2: like Figure 6 The equivalent circuit diagram of the TBUF tri-state gate layout in the present invention is shown, including a P-channel field effect transistor , P-channel field effect transistor The drain of the P-channel field effect transistor is electrically connected to Vdd. The source of the P-channel field effect transistor is electrically connected The drain of the P-channel field effect transistor The gate of the P-channel field effect transistor is electrically connected The source and N-channel field effect transistor The drain of the P-channel field effect transistor The source of the signal output terminal Y and the N-channel field effect transistor are connected respectively The drain; N-channel field effect transistor The source of the N-channel field effect transistor is electrically connected The drain of N-channel field effect transistor The source of the N-channel field effect transistor is electrically connected to Vss. The gate of the P-channel field effect transistor is electrically connected The gate and input terminal A; P-channel field effect transistor The drain of the P-channel field effect transistor is connected to the pull-up voltage Vdd. The gate and N-channel field effect transistor The gate of the N-channel field effect transistor is electrically connected to The source of the FET is connected to Vss and N-channel FET A signal input terminal C is formed therebetween; like Figure 4 The figure shows the circuit layout of the traditional common-gate structure TBUF tri-state gate. In the common-gate structure, the gate signals of a pair of N devices and P devices cannot be paired, so two additional devices need to be added. and To match the common-gate structure, a short-circuit method is usually used to make it invalid. Therefore, the volume of the N device and the P device in the common-gate structure occupies a large space, which is not conducive to improving the integration of the gate circuit.

[0051] like Figure 5 The circuit diagram of the TBUF tri-state gate with a separation gate in the present invention is shown. In the separation gate, no additional devices are needed, and only a pair of separation gate structures are used. The circuit function can be realized. At the same time, in the circuit of the separated gate structure, the N device and the P device need to be connected to different electrical signals, which can save the space occupied by the gate circuit device volume, which is beneficial to improve the spatial integration of the gate circuit device. At the same time, it can improve the integration density, reduce the channel process and improve the chip accuracy, which is beneficial to maintain the circuit performance and the flexibility of circuit design.

[0052] Although the embodiments of the present invention are described in detail above, it is obvious to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein may have other embodiments and may be implemented or realized in a variety of ways.

Claims

1. A gate circuit device structure of a CFET, characterized in that: include: The substrate has an N-channel field effect transistor connected in parallel wrapped on the top of the substrate through an insulating layer. and P-channel FET ; N-channel field effect transistor P-channel FET Sharing the same source S, N-channel field effect transistor P-channel FET Share the same drain D; N-channel field effect transistor The gate P-channel FET The gate Separate gates With gate forming a split-gate structure; The gate With gate The incoming electrical signals are different from each other.

2. A CFET gate circuit device structure according to claim 1, characterized in that: N-channel field effect transistor The gate The control signal received is C, P channel field effect transistor The gate The received control signal is C'; the control signal C and the control signal C' are complementary signals.

3. A CFET gate circuit device structure according to claim 2, characterized in that: Gate With gate A dielectric layer is formed between the gate electrodes. With gate The electrical signal between.

4. The gate circuit device structure of a CFET according to claim 1, characterized in that: Gate With gate Vertical stacking from bottom to top, gate With gate Cross-lead gate signals.

5. A CFET gate circuit device process for manufacturing the CFET gate circuit device structure according to any one of claims 1 to 4, characterized in that: The steps include: manufacturing a substrate; Performing an SOI process on the substrate and manufacturing an SOI crystalline silicon substrate; A mask is made by isotropically depositing a thin layer on top of an SOI crystalline silicon substrate using chemical vapor deposition; Etching the insulating layer and forming silicon fins and shallow trenches under the mask; Pre-embed a metal wire structure in the insulating layer and in the shallow trench isolation oxide to form a buried power rail BPR; Fabricating dummy gates and internal spacers; sequentially growing a bottom epitaxial layer, a bottom contact layer, a top epitaxial layer and a top contact layer on the insulating layer; Re-make the metal separation gate structure to isolate the gate signal, and lead out the gate signal separately through the contact interconnection line; The insulating layer, the bottom epitaxial layer, the bottom contact layer, the top epitaxial layer and the top contact layer are polished by chemical mechanical planarization (CMP) technology.

6. A CFET gate circuit device process according to claim 5, characterized in that: The method for isolating a gate signal comprises the following steps: Isolation Gate With gate Signal; Lead out the lower gate signal.

7. A CFET gate circuit device process according to claim 6, characterized in that: Isolation Gate With gate The signal method comprises the following steps: Etch away the outer periphery of the P channel layer ; ALD technology is used to deposit a new layer layer ; The new layer As a gate With gate The dielectric layer, isolating the gate With gate The electrical signal between layer The upper device gate metal is deposited thereon.

8. A CFET gate circuit device process according to claim 7, characterized in that: The method for extracting the lower layer gate signal comprises the following steps: A mask for manufacturing gate isolation on top of the insulating layer; Etch a window to lead out the gate electrical signal of the underlying device; Etch out the window layer , to open the window; Depositing nitride on the top of the mask as a device protection layer; etching a gate via at one end of the mask; Etching a metal channel along the gate through hole; A metal channel is deposited to form a deposition portion.

9. The CFET gate device process according to claim 8, characterized in that: The method for extracting the lower layer gate signal also includes: After the deposition of the gate metal of the upper device is completed, polishing the gate metal of the upper device; After the deposition portion is formed, the deposition portion is polished.

10. The CFET gate device process according to claim 8, characterized in that: The method for extracting the lower layer gate signal also includes: The top of the deposition portion is connected to the contact interconnection line, and the contact interconnection line includes a first contact interconnection line and a second contact interconnection line, and the first contact interconnection line and the second contact interconnection line lead out gate signals respectively.

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