Preparation method of semiconductor structure

Abstract

The invention provides a preparation method of a semiconductor structure, and the method comprises the steps: providing a substrate which comprises an active region, and the active region comprises an array region and a peripheral region surrounding the periphery of the array region; an array transistor and a first peripheral transistor are formed, the conduction type of a channel region of the array transistor is the same as that of a channel region of the first peripheral transistor, the array transistor is located in the array region, and the first peripheral transistor is located in the peripheral region; a second peripheral transistor is formed, the conduction type of the channel region of the second peripheral transistor is different from that of the channel region of the array transistor, and the second peripheral transistor is located in the peripheral region. The manufacturing process of the semiconductor structure can be effectively simplified, and the manufacturing cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data randomly at high speed and is widely used in data storage devices or apparatuses.

[0003] DRAM includes an array area and a peripheral area surrounding the array area. The array area is provided with an array circuit and multiple storage structures arranged in an array. The array circuit is used to provide a driving current for the multiple storage structures to realize the storage process of the storage structure. The peripheral area is provided with a peripheral circuit, which is used to provide a driving current for the array circuit and control the working timing of the array circuit. In the related art, the circuit structures in the array area and the peripheral area are prepared separately using different processes.

[0004] However, the manufacturing process of the above DRAM is relatively complicated and the manufacturing cost is relatively high. Summary of the invention

[0005] The present disclosure provides a method for preparing a semiconductor structure, which can effectively simplify the manufacturing process of the semiconductor structure and reduce the preparation cost.

[0006] In a first aspect, the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0007] Providing a substrate, the substrate comprising an active area, the active area comprising an array area and a peripheral area surrounding the array area;

[0008] forming an array transistor and a first peripheral transistor, wherein the conductive type of the channel region of the array transistor is the same as the conductive type of the channel region of the first peripheral transistor, the array transistor is located in the array region, and the first peripheral transistor is located in the peripheral region;

[0009] A second peripheral transistor is formed, the conductivity type of the channel region of the second peripheral transistor is different from the conductivity type of the channel region of the array transistor, and the second peripheral transistor is located in the peripheral region.

[0010] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure forms a substrate, and divides the active area of ​​the substrate into an array area and a peripheral area, and uses the substrate to form a structural foundation for supporting the array transistor, the first peripheral transistor, and the second peripheral transistor formed subsequently. By preparing part of the structure of the array transistor and part of the structure of the first peripheral transistor or the second peripheral transistor at the same time, compared with preparing the two separately, the present disclosure can effectively reduce the process steps of the semiconductor structure. By forming the second peripheral transistor, the first peripheral transistor and the second peripheral transistor with different conductivity types in the channel region can be formed in the peripheral area, completing the structural preparation of the semiconductor structure in the peripheral area. Based on this, the present disclosure can effectively simplify the process of the semiconductor structure and reduce its preparation cost.

[0011] The construction of the present disclosure as well as other inventive objects and advantageous effects thereof will be more clearly understood through the description of the preferred embodiments in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of a process for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0014] Figure 2 A schematic diagram of a process of providing a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0015] Figure 3 A schematic diagram of a process of forming an array transistor and a first peripheral transistor in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0016] Figure 4 A schematic diagram of a process for forming a first peripheral well region and an array well region in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0017] Figure 5 A schematic diagram of a process for forming a first peripheral gate structure and an array gate structure in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0018] Figure 6 A schematic diagram of a process of forming a second peripheral transistor in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0019] Figure 7A schematic diagram of a process for forming a second peripheral well region in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0020] Figure 8 A schematic diagram of a process for forming a peripheral contact structure and an array contact structure in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure;

[0021] Fig. 9 A schematic diagram of a process for forming a bit line, a capacitor, an interconnect structure and a peripheral circuit in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0022] Fig.10 A regional distribution diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Fig.11 A schematic structural diagram of a substrate for providing a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Fig.12 A schematic structural diagram of forming a first mask layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0025] Fig.13 A schematic diagram of a structure for forming an array well region, a first peripheral well region and an isolation well of a semiconductor structure provided in an embodiment of the present disclosure;

[0026] Fig.14 A schematic structural diagram of removing the first mask layer of the semiconductor structure provided by an embodiment of the present disclosure;

[0027] Fig.15 A schematic structural diagram of forming a second mask layer of a semiconductor structure provided by an embodiment of the present disclosure;

[0028] Fig.16 A schematic diagram of a structure for forming a second peripheral well region of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Fig.17 A schematic structural diagram of removing the second mask layer of the semiconductor structure provided by an embodiment of the present disclosure;

[0030] Fig.18 A schematic diagram of a structure for forming a groove of a semiconductor structure provided by an embodiment of the present disclosure;

[0031] Fig.19 A schematic structural diagram of a semiconductor structure provided in an embodiment of the present disclosure that forms an array gate structure, a first peripheral gate structure, and a second peripheral gate structure;

[0032] Fig. 20 A schematic diagram of a structure of forming an array source region, an array drain region, a first peripheral source region and a first peripheral drain region of a semiconductor structure provided by an embodiment of the present disclosure;

[0033] Fig.21 A schematic diagram of a structure for forming a second peripheral source region and a second peripheral drain region of a semiconductor structure provided by an embodiment of the present disclosure;

[0034] Fig. 22 A schematic structural diagram of a dielectric layer formed in a semiconductor structure provided by an embodiment of the present disclosure;

[0035] Fig.23 A schematic diagram of a structure for forming a trench in a semiconductor structure provided by an embodiment of the present disclosure;

[0036] Fig.24 A schematic structural diagram of forming a first conductive layer of a semiconductor structure provided in an embodiment of the present disclosure;

[0037] Fig.25 A schematic diagram of a structure forming an array contact structure and a peripheral contact structure of a semiconductor structure provided by an embodiment of the present disclosure;

[0038] Fig.26 A schematic diagram of a structure for forming a second conductive layer of a semiconductor structure provided in an embodiment of the present disclosure;

[0039] Fig. 27 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure that forms a bit line, a first capacitor conductive layer, a peripheral circuit and an interconnection structure;

[0040] Fig.28 A schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure that forms a bit line, a capacitor, a peripheral circuit and an interconnection structure;

[0041] Fig.29 A schematic structural diagram of forming an array channel and a first peripheral channel of a semiconductor structure provided by another embodiment of the present disclosure;

[0042] Fig.30 A schematic structural diagram of forming a second peripheral channel of a semiconductor structure provided by another embodiment of the present disclosure;

[0043] Fig.31 A schematic structural diagram of a groove formed in a semiconductor structure provided by another embodiment of the present disclosure;

[0044] Fig.32 A schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure that forms an array gate structure, a first peripheral gate structure, and a second peripheral gate structure;

[0045] Fig.33 A schematic structural diagram of forming an array source region, an array drain region, a first peripheral source region and a first peripheral drain region of a semiconductor structure provided by another embodiment of the present disclosure;

[0046] Fig.34 A schematic structural diagram of forming a second peripheral source region and a second peripheral drain region of a semiconductor structure provided by another embodiment of the present disclosure;

[0047] Fig.35 A schematic structural diagram of forming an array well region and a first peripheral well region of a semiconductor structure provided by another embodiment of the present disclosure;

[0048] Fig.36 A schematic structural diagram of forming a second peripheral well region of a semiconductor structure provided by another embodiment of the present disclosure;

[0049] Fig.37 A schematic diagram of a structure for forming an array source region, an array drain region, and a second peripheral channel of a semiconductor structure provided by another embodiment of the present disclosure;

[0050] Fig.38 A schematic structural diagram of a semiconductor structure provided by another embodiment of the present disclosure that forms an array gate structure, a first peripheral gate structure, and a second peripheral gate structure;

[0051] Fig.39 A schematic diagram of a structure of a semiconductor structure provided by another embodiment of the present disclosure that forms a first peripheral source region and a second peripheral source region;

[0052] Fig.40 A schematic diagram of the structure of a semiconductor structure providing a second peripheral source region and a second peripheral source region according to another embodiment of the present disclosure.

[0053] Description of reference numerals:

[0054] 100, substrate; 200, array transistor; 300, first peripheral transistor; 400, second peripheral transistor; 500, isolation well; 600, bit line; 700, capacitor; 701, first capacitor conductive layer; 702, capacitor dielectric layer; 703, second capacitor conductive layer; 800, interconnect structure; 900, peripheral circuit; 101, first mask layer; 1011, first mask opening; 102, second mask layer; 1021, second mask opening; 103, dielectric layer; 1031, groove; 104, first conductive layer; 105, second conductive layer; 106, array contact structure; 107, peripheral contact structure; 108, groove; 2 01, sensing amplifier circuit; 202, sub-word line driving circuit; 203, anti-fuse circuit; 204, input-output circuit; AA, array area; AW, array well area; AS, array source area; AD, array drain area; ACH, array channel; AG, array gate structure; PA1, first peripheral area; PW1, first peripheral well area; PS1, first peripheral source area; PD1, first peripheral drain area; PCH1, first peripheral channel; PG1, first peripheral gate structure; PA2, second peripheral area; PW2, second peripheral well area; PS2, second peripheral source area; PD2, second peripheral drain area; PCH2, second peripheral channel; PG2, second peripheral gate structure. DETAILED DESCRIPTION

[0055] DRAM includes an array area and a peripheral area surrounding the array area. The array area is provided with an array circuit and a plurality of storage structures arranged in an array. The array circuit is used to provide a driving current for the plurality of storage structures to realize the storage process of the storage structure. A peripheral circuit is provided in the peripheral area. The peripheral circuit is used to provide a driving current for the array circuit and control the working timing of the array circuit. Among them, the peripheral circuit includes sub-circuits with different driving functions, and the plurality of sub-circuits can provide driving signals with different functions for the array circuit. The array circuit in the array area includes a plurality of storage transistors, and the storage structure may include any one of a capacitor and a magnetic tunnel junction. The sources (or drains) of the plurality of storage transistors are connected to the plurality of storage structures in a one-to-one correspondence, and the drains (or sources) and gates of the plurality of storage transistors are all connected to different sub-circuits of the peripheral circuit.

[0056] When the peripheral circuit is working, a subcircuit inputs a storage signal (or a read signal) to the source of the array transistor, and another subcircuit inputs a drive signal to the gate of the array transistor. When the drive signal acts on the array transistor to make it in a conductive state, the storage signal (or the read signal) is written into the storage structure through the drain of the array transistor to achieve signal storage (or reading). The multiple subcircuits in the peripheral circuit may include peripheral transistors with different conductivity types in the channel region, such as N-type transistors and P-type transistors. The storage transistor in the array region may be an N-type transistor or a P-type transistor.

[0057] In the related art, the circuit structures in the array area and the peripheral area are prepared separately using different processes. Specifically, the array transistor is an N-type transistor as an example. For example, when preparing an N-type array transistor, it is necessary to use a mask layer to cover the peripheral area, and perform operations such as etching and doping on the substrate of the array area to form the structure of the array transistor. When preparing peripheral transistors, it is also necessary to use a mask layer to cover the array area, and etch and dope the substrate of the peripheral area. In addition, the N-type peripheral transistors and P-type peripheral transistors with different conductivity types in the channel region also need to be doped separately. Therefore, in the above process, the mask layer needs to be used multiple times, and the preparation process is relatively cumbersome, resulting in a high process cost for the semiconductor structure.

[0058] The method for preparing a semiconductor structure provided by an embodiment of the present disclosure forms a substrate, and divides the active area of ​​the substrate into an array area and a peripheral area, and uses the substrate to form a structural foundation for supporting the array transistor, the first peripheral transistor, and the second peripheral transistor formed subsequently. By preparing part of the structure of the array transistor and part of the structure of the first peripheral transistor or the second peripheral transistor at the same time, compared with preparing the two separately, the present disclosure can effectively reduce the process steps of the semiconductor structure. By forming the second peripheral transistor, the first peripheral transistor and the second peripheral transistor with different conductivity types in the channel region can be formed in the peripheral area, completing the structural preparation of the semiconductor structure in the peripheral area. Based on this, the present disclosure can effectively simplify the process of the semiconductor structure and reduce its preparation cost.

[0059] In order to make the purpose, technical solution and advantages of the present disclosure clearer, the technical solution in the embodiment of the present disclosure will be described in more detail below in conjunction with the drawings in the preferred embodiments of the present disclosure. In the drawings, the same or similar reference numerals throughout represent the same or similar parts or parts with the same or similar functions. The described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. The embodiments described below with reference to the drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limitations on the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure. The embodiments of the present disclosure are described in detail below in conjunction with the drawings.

[0060] The present disclosure embodiment provides a method for preparing a semiconductor structure. The semiconductor structure may be a memory, and the memory may include a DRAM, a static random access memory (Static Random Access Memory, SRAM for short), a flash memory, an electrically erasable programmable read-only memory (EEPROM for short), a phase change random access memory (PRAM for short), or a magnetoresistive random access memory (MRAM for short). The present disclosure embodiment does not limit the specific type of memory. Below, the semiconductor structure is DRAM as an example for explanation.

[0061] Reference Figure 1 As shown, the method for preparing a semiconductor structure provided by an embodiment of the present disclosure includes:

[0062] S100: providing a substrate, the substrate comprising an active region, the active region comprising an array region and a peripheral region surrounding the array region. Figure 2 As shown, providing a substrate 100 includes: S101: providing an initial substrate. S102: performing a doping process on the initial substrate to form a substrate, wherein the doped region forms an active region.

[0063] The ion doping type of the substrate 100 is different from the ion doping type of the first peripheral well region (Periphery Well 1, PW1 for short), and is the same as the ion doping type of the second peripheral well region (Periphery Well 2, PW2 for short).

[0064] Combination Fig.21 As shown, the initial substrate provided in the embodiment of the present disclosure may be single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound or silicon on insulator (SOI), etc., or other materials known to those skilled in the art. The initial substrate may provide a structural basis for supporting the array transistor 200, the first peripheral transistor 300 and the second peripheral transistor 400 that are subsequently arranged. The initial substrate may be formed by deposition. For example, it may be a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD).

[0065] Reference Fig.10 and Fig.11 As shown, the active region of the substrate 100 can be formed by doping the initial substrate, and the ion doping type of the active region can be adjusted by controlling the doped ions. In this embodiment, the ions doped in the active region can be group III elements (B or Ga), and the formation of a P-type active region (P-sub) is used as an example for explanation. In other embodiments, the ions doped in the active region can be group V elements (As or P), thereby forming an N-type active region.

[0066] The active area may include an array area (AA) and a peripheral area (PA), and the peripheral area is arranged at the periphery of the array area AA. The peripheral area may include a first peripheral area PA1 and a second peripheral area PA2, and the first peripheral area PA1 is arranged at the periphery of the array area AA, and the second peripheral area PA2 is arranged at the periphery of the first peripheral area PA1. A sense amplifier circuit 201 (SA) and a sub word line driver circuit 202 (SWD) are arranged in the first peripheral area PA1. An antifuse circuit 203 (Antifuse) and an input-output circuit 204 (I / O) are arranged in the second peripheral area PA2. The antifuse circuit 203 and the input-output circuit 204 in the second peripheral area PA2 are connected to the sense amplifier circuit 201 and the sub word line driver circuit 202 in the first peripheral area PA1 to realize the control of the signal writing in the first peripheral area PA1. Based on the fact that a plurality of circuits are arranged in the peripheral region, the above-mentioned circuits may include peripheral transistors, and the peripheral transistors include a first peripheral transistor 300 and a second peripheral transistor 400 having different conductivity types in the channel region. Below, the first peripheral transistor 300 is an N-type transistor, and the second peripheral transistor 400 is a P-type transistor. The ion doping type of the first peripheral well region PW1 of the first peripheral transistor 300 is P-type, which is the same as the ion doping type of the active region of the substrate 100. The ion doping type of the second peripheral well region PW2 of the second peripheral transistor 400 is N-type, which is different from the ion doping type of the active region of the substrate 100.

[0067] In this embodiment, combined with Fig.10 , Fig.21 and Fig.28As shown, the array area AA includes a plurality of repeated storage units, each of which includes a storage structure and an array transistor 200. The disclosed embodiment is described by taking the storage structure as a capacitor 700 as an example. Among them, the gate of the array transistor 200 is connected to the word line (Word Line, referred to as WL), the source is connected to the bit line 600 (Bit Line, referred to as BL), and the drain is connected to the capacitor 700. The word line is connected to the sub-word line driving circuit 202 of the first peripheral area PA1, and the sub-word line driving circuit 202 controls the signal writing on the word line. The bit line 600 is connected to the sensing amplifier circuit 201 of the first peripheral area PA1, and the sensing amplifier circuit 201 controls the signal writing or signal reading on the bit line 600. The voltage signal on the word line can control the opening or closing of the array transistor 200, read the data information stored in the capacitor 700 through the bit line 600, or write the data information into the capacitor 700 through the bit line 600 for storage.

[0068] Continue to refer to Figure 1 As shown, after forming the substrate 100, the following further includes: S200: forming an array transistor and a first peripheral transistor, wherein the conductive type of the channel region of the array transistor is the same as the conductive type of the channel region of the first peripheral transistor, the array transistor is located in the array region, and the first peripheral transistor is located in the peripheral region. Both the array transistor 200 and the first peripheral transistor 300 are N-type transistors.

[0069] Optional, see Figure 3 As shown, an array transistor 200 and a first peripheral transistor 300 are formed, including:

[0070] S201: forming a first peripheral well region and an array well region, wherein the first peripheral well region is located in the peripheral region and the array well region is located in the array region. Figure 4 As shown, a first peripheral well region PW1 and an array well region AW are formed, including:

[0071] S2011: forming a first mask layer on the substrate, wherein the first mask layer exposes a portion of the peripheral region and a portion of the array region.

[0072] Reference Fig.12 As shown, the first mask layer 101 can be formed by deposition, and the first mask layer 101 has a first mask opening 1011, and the first mask opening 1011 corresponds to a portion of the peripheral area and a portion of the array area AA, forming an exposed portion of the peripheral area and a portion of the array area AA. The material of the first mask layer 101 can include but is not limited to silicon nitride and silicon oxynitride.

[0073] S2012: performing doping treatment on the exposed peripheral area and array area along the first mask layer to form a first peripheral well area in the peripheral area and an array well area in the array area; the first peripheral well area and the array well area have the same ion doping type.

[0074] Reference Fig.13 As shown, along the first mask opening 1011 of the first mask layer 101, ion doping is performed on the exposed portion of the array area AA and the peripheral area. The doped ions can be ions of group III elements, thereby forming a P-type first peripheral well area PW1 in the peripheral area and a P-type array well area (Array Well, AW for short) in the array area AA.

[0075] It should be noted that the method for preparing the semiconductor structure further includes forming an isolation well 500, which is formed simultaneously with the first peripheral well region PW1. In this embodiment, the isolation well 500 is located between the peripheral region and the array region AA.

[0076] Optionally, the first mask opening 1011 of the first mask layer 101 also corresponds to exposing a portion of the substrate 100, and doping the exposed substrate 100, thereby forming an isolation well 500 in the substrate 100. The exposed substrate 100 is located between the peripheral area and the array area AA. Therefore, the formed isolation well 500 is located between the isolation area and the array area AA, so as to electrically isolate the device structures in the array area AA and the peripheral area (for example, the array transistor 200 in the array area AA and the first peripheral transistor 300 and the second peripheral transistor 400 in the peripheral area), thereby improving the electrical stability of the semiconductor structure.

[0077] In some other embodiments, the isolation well 500 is located between the first peripheral transistor 300 and the second peripheral transistor 400, and the first mask opening 1011 also exposes the substrate 100 located between the first peripheral transistor 300 and the second peripheral transistor 400, so that during the doping process, an isolation well 500 is formed in the substrate 100 between the two. The isolation well 500 can effectively isolate the first peripheral transistor 300 and the second peripheral transistor 400, thereby improving the electrical stability of both. Since the isolation well 500 is formed synchronously with the array well region AW and the first peripheral well region PW1, the ion doping type of the isolation well 500 is the same as that of the array well region AW and the first peripheral well region PW1. In this embodiment, the isolation well 500 is a P-type doping region in the substrate 100.

[0078] It should be noted that the ion doping depth of the isolation well 500 is greater than the ion doping depth of the array well region AW and the first peripheral well region PW1, so that the isolation effect of the isolation well 500 can be guaranteed. The disclosed embodiment does not limit the specific value of the above-mentioned ion doping depth. In this embodiment, the isolation well 500 can also be a ring structure surrounding the array transistor, the first peripheral transistor and / or the second peripheral transistor to ensure the isolation effect of the isolation well 500.

[0079] In the present disclosure, a first mask layer 101 is used to expose part of the array area AA and part of the peripheral area, thereby simultaneously forming the first peripheral well area PW1 and the array well area AW. In this way, compared with the related art, the array well area AW of the array transistor 200 and the peripheral well area of ​​the peripheral transistor are separately doped and formed. The present disclosure can effectively reduce the process steps of the semiconductor structure, reduce the difficulty of preparation, and reduce the preparation cost. At the same time, the isolation well 500 is prepared simultaneously with the array well area AW and the first peripheral well area PW1, which can also achieve the effect of simplifying the process.

[0080] After forming the array well region AW, the first peripheral well region PW1 and the isolation well 500, the first mask layer 101 may be removed to form Fig.14 The structure shown in .

[0081] Continue to refer to Figure 3 As shown, after the array well region AW and the first peripheral well region PW1 are formed, it also includes: S202: forming a first peripheral gate structure and an array gate structure, the first peripheral gate structure is located on the substrate, the array gate structure is located in the substrate, and the array gate structure corresponds to the array channel of the array well region, and the first peripheral gate structure corresponds to the first peripheral channel of the first peripheral well region.

[0082] Among them, refer to Figure 5 As shown, a first peripheral gate structure PG1 and an array gate structure AG are formed. Specifically, it includes:

[0083] S2021: forming a groove in the substrate of the array well region. Fig.18 As shown, the groove can be formed by etching. The depth of the groove 108 is less than the depth of the array well region AW, and the groove 108 can allow the array gate structure AG to be located therein, thereby forming a buried gate structure.

[0084] S2022: forming a stack layer on the substrate, the stack layer comprising an initial gate dielectric layer, an initial gate semiconductor layer, an initial diffusion barrier layer and an initial gate metal layer stacked in sequence in a direction away from the substrate.

[0085] S2023: removing part of the stacked layers, retaining the stacked layers corresponding to the first peripheral channel to form a first peripheral gate structure, and retaining the stacked layers located in the groove to form an array gate structure.

[0086] Reference Fig.19As shown, the stack layer can be a whole layer covering the surface of the substrate 100, and the portion of the stack layer corresponding to the groove 108 is filled in the groove 108. Afterwards, part of the stack layer is removed by mask etching, and only the stack layer corresponding to the groove 108 is retained to form an array gate structure AG, and the stack layer corresponding to the first peripheral channel PCH1 in the first peripheral well region PW1 is retained to form a first peripheral gate structure PG1. Among them, the array gate structure AG is a buried gate structure in the groove 108, which can effectively reduce the space occupied by the array gate structure AG, help to improve the structural integration in the array area AA, and thus reduce the volume of the semiconductor structure.

[0087] In some embodiments, the material of the initial gate semiconductor layer may be silicon oxide, the material of the initial gate semiconductor layer may be polysilicon, the material of the initial diffusion barrier layer may be titanium nitride, and the material of the initial gate metal layer may be tungsten or copper. The initial diffusion barrier layer may effectively block the metal ions of the initial gate metal layer from diffusing into the gate semiconductor layer, thereby ensuring the structural stability of the subsequently formed array gate structure AG and the first peripheral gate structure PG1.

[0088] In the present disclosure, the array gate structure AG and the first peripheral gate structure PG1 are formed simultaneously, which helps to reduce the process steps of the semiconductor structure.

[0089] Continue to refer to Figure 3 As shown, after the array gate structure AG and the first peripheral gate structure PG1 are formed, it also includes: S203: forming an array source region, an array drain region, a first peripheral source region and a first peripheral drain region, the array source region and the array drain region are both located in the array well region and are respectively located on opposite sides of the array channel, the first peripheral source region and the first peripheral drain region are both located in the first peripheral well region and are respectively located on opposite sides of the first peripheral channel.

[0090] Among them, the array well region AW, the array source region (Array Source, AS for short), the array channel (Array Channel, ACH for short), the array drain region (Array Drain, AD for short) and the array gate structure (Array Gate, AG) together form the array transistor 200, and the first peripheral well region PW1, the first peripheral source region (Periphery Source 1, PS1 for short), the first peripheral channel (Periphery Channel 1, PCH1 for short), the first peripheral drain region (Periphery Drain 1, PD1 for short) and the first peripheral gate structure (Periphery Gate 1, PG1 for short) together form the first peripheral transistor 300.

[0091] Reference Fig. 20As shown, the array source region AS, the array drain region AD, the first peripheral source region PS1 and the first peripheral drain region PD1 can be formed by mask doping, and the ion doping types of the above regions are the same, and are different from the ion doping types of the array well region AW and the first peripheral well region PW1. In the embodiment of the present disclosure, the ion doping types of the array source region AS, the array drain region AD, the first peripheral source region PS1 and the first peripheral drain region PD1 are all N-type for explanation. The array channel ACH can be located in the array well region AW, corresponding to the bottom position of the array gate structure AG, and located between the array source region AS and the array drain region AD. The first peripheral channel PCH1 is located in the first peripheral well region PW1, corresponding to the first peripheral gate structure PG1, and is located between the first peripheral source region PS1 and the first peripheral drain region PD1.

[0092] In the present disclosure, the array source region AS, the array drain region AD, the first peripheral source region PS1 and the first peripheral drain region PD1 are formed simultaneously, which can effectively reduce the process steps of the semiconductor structure.

[0093] The array transistor 200 and the first peripheral transistor 300 can be formed synchronously through the above process. On the basis of the above process, some processes can be further added to prepare the second peripheral transistor 400. Part of the process of the second peripheral transistor 400 can also be completed synchronously with the process of the array transistor 200 and the first peripheral transistor 300, thereby further simplifying the process steps of the semiconductor structure.

[0094] Next, the process of manufacturing the second peripheral transistor 400 is described in detail.

[0095] Reference Figure 1 As shown, the method for preparing the semiconductor structure further includes: S300: forming a second peripheral transistor, the conductivity type of the channel region of the second peripheral transistor is different from the conductivity type of the channel region of the array transistor, and the second peripheral transistor is located in the peripheral region.

[0096] The second peripheral transistor 400 may include a second peripheral well region PW2, a second peripheral gate structure (Periphery Gate 2, PG2 for short), a second peripheral source region (Periphery Source 2, PS2 for short), a second peripheral drain region (Periphery Drain 2, PD2 for short) and a second peripheral channel (Periphery Channel 2, PCH2 for short). Figure 6 As shown, before forming the second peripheral gate structure PG2, it also includes:

[0097] S301: forming a second peripheral well region, wherein the second peripheral well region is located in the peripheral region and is spaced apart from the first peripheral well region, and a second peripheral channel is located in the second peripheral well region.

[0098] Optional, see Figure 7 As shown, a second peripheral well region PW2 is formed, including:

[0099] S3011: forming a second mask layer, wherein the second mask layer exposes a portion of the peripheral area. Fig.15 As shown, the second mask layer can be formed by deposition, and the second mask opening of the second mask layer corresponds to a portion of the peripheral area.

[0100] S3012: Perform doping on the exposed peripheral region along the second mask layer to form a second peripheral well region in the peripheral region. The second peripheral well region has a different ion doping type from the first peripheral well region. Fig.16 As shown, the exposed peripheral region is doped along the second mask opening 1021 to form a second peripheral well region PW2. In this embodiment, the ion doping type of the second peripheral well region PW2 can be N-type.

[0101] It should be noted that the first peripheral transistor 300 and the second peripheral transistor 400 can form a CMOS (Complementary Metal Oxide Semiconductor) together, and the second peripheral well region PW2 can be formed by doping to form a double well region structure of the CMOS. That is, the CMOS includes the first peripheral well region PW1 and the second peripheral well region PW2 of different ion doping types at the same time.

[0102] After forming the second peripheral well region PW2, the second mask layer 102 is removed to form Fig.17 structure.

[0103] In some embodiments, the isolation well 500 may not be formed synchronously with the array well region AW and the first peripheral well region PW1, and the isolation well 500 may be formed synchronously with the second peripheral well region PW2. In this way, during the formation of the array transistor 200 and the first peripheral transistor 300, the position of the isolation well 500 in the substrate 100 may be reserved, and during the formation of the second peripheral well region PW2, the second mask opening 1021 of the second mask layer 102 simultaneously exposes part of the peripheral region and the reserved position of the isolation well 500, so that during the doping process, the second peripheral well region PW2 and the isolation well 500 may be formed. In this embodiment, the ion doping type of the isolation well 500 is the same as the ion doping type of the second peripheral well region PW2, that is, N-type. The ion doping depth of the isolation well 500 may also be greater than the ion doping depth of the array well region AW, the first peripheral well region PW1, and the second peripheral well region PW2 to ensure the isolation effect.

[0104] In other embodiments, the first peripheral transistor 300 may be directly formed in part of the peripheral region, that is, without forming the first peripheral well region PW1, and using the P-type active region as the well region of the first peripheral transistor 300. This structure forms a single well region structure of CMOS.

[0105] For the above-mentioned CMOS double well region structure or single well region structure, the first peripheral transistor 300 and the second peripheral transistor 400 formed subsequently are both located in the region isolated by the isolation well 500. That is, there is an isolation well 500 between the second peripheral transistor 400 and the first peripheral transistor 300 or the array transistor 200. Fig.17 The first peripheral well region PW1 shown in the figure is located on the side of the second peripheral well region PW2 close to the array well region AW, and an isolation well 500 is provided between the first peripheral well region PW1 and the array well region AW. In other embodiments, the second peripheral well region PW2 may be located on the side of the first peripheral well region PW1 close to the array well region AW, and an isolation well 500 may also be provided between the second peripheral well region PW2 and the array well region AW. The present disclosure is not limited to the illustrated positional relationship.

[0106] After forming the second peripheral well region PW2, refer to Figure 6 As shown, the step of forming the second peripheral transistor 400 further includes:

[0107] S302: forming a second peripheral gate structure, the second peripheral gate structure being located on the substrate and corresponding to the second peripheral channel of the peripheral region. The second peripheral gate structure is formed synchronously with the first peripheral gate structure. Figure 5 As shown, it specifically includes: S2024: removing part of the stack layer, retaining the stack layer corresponding to the second peripheral channel, and forming a second peripheral gate structure.

[0108] Reference Fig.19 As shown, in the step of removing the stacked layers, a portion of the stacked layers corresponding to the second peripheral channel PCH2 of the second peripheral well region PW2 may be retained, thereby forming a second peripheral gate structure PG2.

[0109] Continue to refer to Figure 6 As shown, after forming the second peripheral gate structure PG2, it also includes: S303: forming a second peripheral source region and a second peripheral drain region, the second peripheral source region and the second peripheral drain region are both located in the peripheral region and are respectively located on opposite sides of the second peripheral channel. The second peripheral source region PS2 and the second peripheral drain region PD2 have different ion doping types from the array source region AS, so they need to be doped in steps. Fig. 20As shown, during the doping process of the array source region AS, the array drain region AD, the first peripheral source region PS1 and the first peripheral drain region PD1, a mask layer (not shown in the figure) may be used to shield the second peripheral well region PW2 and the second peripheral gate structure PG2. Fig.21 As shown, during the doping process of the second peripheral source region PS2 and the second peripheral drain region PD2, a mask layer (not shown) can also be used to shield the array source region AS, the array drain region AD, the first peripheral source region PS1 and the first peripheral drain region PD1.

[0110] The ion doping type of the second peripheral source region PS2 and the second peripheral drain region PD2 may be P type. The second peripheral well region PW2 , the second peripheral source region PS2 , the second peripheral channel PCH2 , the second peripheral drain region PD2 and the second peripheral gate structure PG2 together form a second peripheral transistor 400 .

[0111] In the above embodiment, the array channel ACH, the first peripheral channel PCH1 and the second peripheral channel PCH2 are not doped, but are formed in their respective corresponding well regions. In other embodiments, the above three can also be doped to improve the electrical properties of the three. The doping process of the array channel ACH, the first peripheral channel PCH1 and the second peripheral channel PCH2 is described in detail below.

[0112] Reference Fig.29 and Fig.30 As shown, on the basis of the structure of forming the array well region AW, the first peripheral well region PW1 and the second peripheral well region PW2 (the second peripheral well region PW2 may not be provided, that is, it is carried out on the basis of the structure of the single well region of CMOS), a mask layer (not shown in the figure) is used to shield the second peripheral well region PW2, and the array well region AW and the first peripheral well region PW1 are doped to form the array channel ACH and the first peripheral channel PCH1. Among them, the ion doping type of the array channel ACH and the first peripheral channel PCH1 is the same as the ion doping type of the array well region AW and the first peripheral well region PW1, that is, P type. Compared with the ion doping concentration of the well region, the ion doping concentration of the array channel ACH and the first peripheral channel PCH1 is higher, so that the punch-through phenomenon of the source and drain regions can be effectively prevented, and the electrical performance of the array transistor 200 and the first peripheral transistor 300 can be improved.

[0113] Reference Fig.31As shown, after forming the array channel ACH and the first peripheral channel PCH1, a mask layer (not shown in the figure) can be used to shield the array well area AW and the first peripheral well area PW1, and the second peripheral well area PW2 can be doped to form the second peripheral channel PCH2. Among them, the ion doping type of the second peripheral channel PCH2 is the same as the ion doping type of the second peripheral well area PW2, that is, N-type. Compared with the ion doping concentration of the second peripheral well area PW2, the ion doping concentration of the second peripheral channel PCH2 is higher, which can also prevent the source and drain regions of the second peripheral transistor 400 from punching through, and improve the electrical performance of the second peripheral transistor 400.

[0114] Reference Fig.32 As shown, the process of forming the array gate structure AG, the first peripheral gate structure PG1 and the second peripheral gate structure PG2 is the same as in the above embodiment, and the only difference is that the groove 108 forming the array gate structure AG is opened in the array channel ACH formed by doping.

[0115] Reference Fig.33 and Fig.34 As shown, the process of forming the array source region AS, the array drain region AD, the first peripheral source region PS1 and the second peripheral source region PS2 is the same, and the second peripheral well region PW2, the second peripheral channel PCH2 and the second peripheral gate structure PG2 are shielded by a mask layer, and the array well region AW and the first peripheral well region PW1 are doped to form the array source region AS and the array drain region AD, which are respectively located on both sides of the above-mentioned array channel ACH, thereby forming the array transistor 200. At the same time, the first peripheral source region PS1 and the first peripheral drain region PD1 are formed, which are respectively located on both sides of the above-mentioned first peripheral channel PCH1, thereby forming the first peripheral transistor 300. Afterwards, the array transistor 200 and the first peripheral transistor 300 formed by shielding the mask layer are doped on the second peripheral well region PW2 to form the second peripheral source region PS2 and the second peripheral drain region PD2, which are respectively located on both sides of the above-mentioned second peripheral channel PCH2, thereby forming the second peripheral transistor 400.

[0116] Combination Fig.10 As shown, in the present disclosure, the first peripheral transistor 300 is located in the first peripheral area PA1 or the second peripheral area PA2. The second peripheral transistor 400 is located in the first peripheral area PA1 or the second peripheral area PA2. The first peripheral transistor 300 and the second peripheral transistor 400 can be located in the first peripheral area PA1 at the same time, and can also be located in the second peripheral area PA2 at the same time. Of course, one can also be located in the first peripheral area PA1 and the other can be located in the second peripheral area PA2, and the present disclosure is not limited to this.

[0117] In some embodiments of the present disclosure, a partial structure of the array transistor 200 and a partial structure of the second peripheral transistor 400 may be prepared simultaneously to reduce the process steps of the semiconductor structure. Specific descriptions are as follows:

[0118] The array transistor 200 and the first peripheral transistor 300 are formed, including: forming an array well region AW and a first peripheral well region PW1, wherein the array well region AW is located in the array region AA, and the first peripheral well region PW1 is located in the peripheral region. Fig.35 As shown, in this embodiment, the array transistor 200 and the first peripheral transistor 300 are both N-type transistors, and the array well region AW and the first peripheral well region PW1 are both P-type doped regions of the substrate 100. During the doping process, a mask layer (not shown in the figure) can be used to block part of the peripheral region, exposing the array region AA and part of the peripheral region. After simultaneous doping, the array well region AW is formed in the exposed array region AA, and the first peripheral well region PW1 is formed in the exposed peripheral region. Compared with the separate preparation of the array well region AW and the first peripheral well region PW1, the above preparation method can effectively simplify the process of the semiconductor structure.

[0119] Reference Fig.36 As shown, forming a second peripheral transistor 400 includes: forming a second peripheral well region PW2, the second peripheral well region PW2 is located in the peripheral region and is spaced apart from the first peripheral well region PW1. During the doping process, a mask layer (not shown in the figure) can be used to shield the array well region AW and the first peripheral well region PW1, exposing part of the peripheral region, and after doping, forming the second peripheral well region PW2 in the exposed peripheral region.

[0120] After forming the second peripheral well region PW2, the method further includes: forming an array source region AS, an array drain region AD and a second peripheral channel PCH2, wherein the array source region AS and the array drain region AD are both located in the array well region AW, an array channel is provided between the array source region AS and the array drain region AD, and the second peripheral channel PCH2 is located in the second peripheral well region PW2. Fig.37 As shown, the array source region AS, the array drain region AD and the second peripheral channel PCH2 are formed by simultaneous doping, and the ion doping types of the three can be the same. In this embodiment, the ion doping types of the three are all N-type. In this way, the manufacturing process of the semiconductor structure can be simplified.

[0121] After forming the array source region AS, the array drain region AD and the second peripheral channel PCH2, it also includes: forming an array gate structure AG, a first peripheral gate structure PG1 and a second peripheral gate structure PG2, the array gate structure AG is located in the substrate 100 and corresponds to the array channel, the first peripheral gate structure PG1 and the second peripheral gate structure PG2 are both located on the substrate 100, the first peripheral gate structure PG1 corresponds to the first peripheral channel PCH1, and the second peripheral gate structure PG2 corresponds to the second peripheral channel PCH2. Its structure can be referred to Fig.38 As shown, the array gate structure AG is a buried gate structure, and the first peripheral gate structure PG1 and the second peripheral gate structure PG2 can be disposed on the substrate 100. The structures and arrangements of the three are the same as those in the above embodiment, and will not be described again.

[0122] Among them, in some embodiments, the array gate structure AG can be formed synchronously with the first peripheral gate structure PG1 and the second peripheral gate structure PG2, that is, the gate dielectric layer, gate semiconductor layer, diffusion barrier layer and gate metal layer of the three can be deposited and formed synchronously to simplify the process of the three. In other embodiments, the array gate structure AG can also be formed step by step with the first peripheral gate structure PG1 and the second peripheral gate structure PG2, that is, the gate dielectric layer, gate semiconductor layer, diffusion barrier layer and gate metal layer of the three can be deposited and formed in different steps. In this way, the requirements of the three for different deposition parameters of the gate dielectric layer, gate semiconductor layer, diffusion barrier layer and gate metal layer can be met, and the needs of adjusting the gate performance of each can be met. In addition, the step-by-step formation can also make the partial structures of the three synchronously prepared with the remaining structures in the semiconductor structure, meeting the various requirements of the preparation of the semiconductor structure. For example, the gate semiconductor layer of the first peripheral gate structure PG1 and / or the second peripheral gate structure PG2 can be synchronously prepared with the semiconductor contact layer of the bit line contact structure in the semiconductor structure. The present disclosure is only described by this example and is not limited to it.

[0123] The array gate structure AG, the first peripheral gate structure PG1 and the second peripheral gate structure PG2 are formed, and the first peripheral source region PS1 and the first peripheral drain region PD1 are formed. The first peripheral source region PS1 and the first peripheral drain region PD1 are both located in the first peripheral well region PW1, and there is a first peripheral channel between the first peripheral source region PS1 and the first peripheral drain region PD1. Fig.39As shown, the ion doping type of the first peripheral source region PS1 and the first peripheral drain region PD1 can be N-type, which is the same as the ion doping type of the second peripheral channel PCH2, and they can be doped separately, that is, the doping process of the first peripheral source region PS1 and the first peripheral drain region PD1 can also be completed before the step of forming the array source region AS, the array drain region AD and the second peripheral channel PCH2, and the ion doping of the first peripheral source region PS1 and the first peripheral drain region PD1 can also be performed simultaneously with the step of forming the array source region AS, the array drain region AD and the second peripheral channel PCH2.

[0124] After forming the second peripheral well region PW2 and the second peripheral channel PCH2, the second peripheral source region PS2 and the second peripheral drain region PD2 are formed. The second peripheral source region PS2 and the second peripheral drain region PD2 are both located in the second peripheral well region PW2. There is a second peripheral channel PCH2 between the second peripheral source region PS2 and the second peripheral drain region PD2. The structure can be referred to Fig.40 As shown, the ion doping type of the second peripheral source region PS2 and the second peripheral drain region PD2 may be P type.

[0125] Among them, the array well region AW, the array source region AS, the array channel, the array drain region AD and the array gate structure AG together form an array transistor 200; the first peripheral well region PW1, the first peripheral source region PS1, the first peripheral channel PCH1, the first peripheral drain region PD1 and the first peripheral gate structure PG1 together form a first peripheral transistor 300; the second peripheral well region PW2, the second peripheral source region PS2, the second peripheral channel PCH2, the second peripheral drain region PD2 and the second peripheral gate structure PG2 together form a second peripheral transistor 400.

[0126] In this embodiment, after forming the array well region AW, the array well region AW may be doped to form an array channel. After forming the first peripheral well region PW1, the first peripheral well region PW1 may be doped to form a first peripheral channel PCH1.

[0127] In the following, the first peripheral transistor 300 and the second peripheral transistor 400 are simultaneously located in the first peripheral area PA1, or simultaneously located in the second peripheral area PA2. Both can be used as components of the circuit in the first peripheral area PA1 (or, the second peripheral area PA2), and the drain of the first peripheral transistor 300 and the source of the second peripheral transistor 400 are connected to form a CMOS structure.

[0128] Reference Figure 1 As shown, in the method for preparing the semiconductor structure disclosed in the present invention, after forming the second peripheral transistor 400, the method further includes:

[0129] S400: forming a plurality of peripheral contact structures and a plurality of array contact structures on a substrate; the array source region and the array drain region are respectively connected to different array contact structures, and the first peripheral source region, the first peripheral drain region, the second peripheral source region and the second peripheral drain region are respectively connected to different peripheral contact structures.

[0130] Optional, see Figure 8 As shown, a peripheral contact structure 107 and an array contact structure 106 are formed, including:

[0131] S401: forming a dielectric layer, the dielectric layer covering the substrate, the array transistor, the first peripheral transistor and the second peripheral transistor. Fig. 22 As shown, the dielectric layer 103 can be formed by deposition, and its material can be silicon nitride.

[0132] S402: forming a trench in the dielectric layer, wherein the trench exposes the first peripheral source region, the first peripheral drain region, the second peripheral source region, the second peripheral drain region, the array source region, and the array drain region. Fig.23 As shown, the channel can be formed by mask etching. The present disclosure does not limit the width of the groove 1031, but the increase in the width of the groove 1031 to a certain extent helps to improve the conductive performance of the subsequently formed array contact structure 106 and the peripheral contact structure 107.

[0133] S403: Fill the trench with a first conductive layer, form a peripheral contact structure with the first peripheral source region, the first peripheral drain region, the second peripheral source region, and the second peripheral drain region, and form an array contact structure with the first conductive layer connected to the array source region and the array drain region. Fig.24 and Fig.25 As shown, the first conductive layer 104 can cover the surface of the dielectric layer 103 and fill the groove 1031. Then, through the chemical mechanical polishing process (CMP), part of the first conductive layer 104 is removed along the surface of the dielectric layer 103, and the first conductive layer 104 retained in the groove 1031 forms an array contact structure 106 and a peripheral contact structure 107 respectively.

[0134] Continue to refer to Figure 1 As shown, after the peripheral contact structure 107 and the array contact structure 106 are formed, the following further includes:

[0135] S500: forming bit lines, capacitors, interconnection structures and peripheral circuits; the array contact structure connected to the array source region is connected to the bit line, and the array contact structure connected to the array drain region is connected to the capacitor; the peripheral contact structures connected to the first peripheral source region and the second peripheral drain region are both connected to the peripheral circuit; the peripheral contact structures connected to the first peripheral drain region and the second peripheral source region are both connected to the interconnection structure.

[0136] Optionally, the capacitor 700 includes a first capacitor conductive layer 701, a capacitor dielectric layer 702 and a second capacitor conductive layer 703;

[0137] Reference Fig. 9 As shown, a bit line 600, a capacitor 700, an interconnect structure 800 and a peripheral circuit 900 are formed, including:

[0138] S501: forming a second conductive layer on the dielectric layer. Fig.26 As shown, the second conductive layer 105 can be formed by deposition, and the entire layer covers the surface of the dielectric layer 103 .

[0139] S502: remove part of the second conductive layer, retain the second conductive layer corresponding to the array source region to form a bit line; retain the second conductive layer corresponding to the array drain region to form a first capacitor conductive layer; retain the second conductive layer corresponding to the first peripheral source region and the second peripheral drain region to form a peripheral circuit; retain the second conductive layer corresponding to the first peripheral drain region and the second peripheral source region to form an interconnection structure. The structure can refer to Fig. 27 shown.

[0140] S503: forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer.

[0141] S504: forming a second capacitor conductive layer, the second capacitor conductive layer is located on the capacitor dielectric layer. Its structure can refer to Fig.28 shown.

[0142] In the above embodiment, the bit line 600, the interconnection structure 800 and the peripheral circuit 900 are formed synchronously with the first capacitor conductive layer 701 of the capacitor 700, so that the manufacturing process of the semiconductor structure can be effectively simplified. In other embodiments, the bit line 600, the interconnection structure 800 and the peripheral circuit 900 can also be formed synchronously with the second capacitor conductive layer 703 of the capacitor 700, and the present disclosure does not limit this.

[0143] In the description of the embodiments of the present disclosure, it should be understood that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or it can be indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to the specific circumstances. The orientation or position relationship indicated by the terms "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present disclosure. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise precisely and specifically specified.

[0144] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present disclosure described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an active area, the active area comprising an array area and a peripheral area surrounding the array area; forming an array transistor and a first peripheral transistor, wherein the conductive type of a channel region of the array transistor is the same as the conductive type of a channel region of the first peripheral transistor, the array transistor is located in the array region, and the first peripheral transistor is located in the peripheral region; A second peripheral transistor is formed, the conductivity type of the channel region of the second peripheral transistor being different from the conductivity type of the channel region of the array transistor, and the second peripheral transistor is located in the peripheral region.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming the array transistor and the first peripheral transistor includes: forming a first peripheral well region and an array well region, wherein the first peripheral well region is located in the peripheral region and the array well region is located in the array region; Forming a first peripheral gate structure and an array gate structure, wherein the first peripheral gate structure is located on the substrate, the array gate structure is located in the substrate, and the array gate structure corresponds to the array channel of the array well region, and the first peripheral gate structure corresponds to the first peripheral channel of the first peripheral well region; forming an array source region, an array drain region, a first peripheral source region and a first peripheral drain region, wherein the array source region and the array drain region are both located in the array well region and are respectively located on two opposite sides of the array channel, and the first peripheral source region and the first peripheral drain region are both located in the first peripheral well region and are respectively located on two opposite sides of the first peripheral channel; The array well region, the array source region, the array channel, the array drain region and the array gate structure together form the array transistor, and the first peripheral well region, the first peripheral source region, the first peripheral channel, the first peripheral drain region and the first peripheral gate structure together form the first peripheral transistor.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that: The second peripheral transistor is formed, comprising: forming a second peripheral gate structure, the second peripheral gate structure being located on the substrate and corresponding to a second peripheral channel of the peripheral region; A second peripheral source region and a second peripheral drain region are formed, wherein the second peripheral source region and the second peripheral drain region are both located in the peripheral region and are respectively located at two opposite sides of the second peripheral channel.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: Before forming the second peripheral gate structure, the method further includes: forming a second peripheral well region, the second peripheral well region being located in the peripheral region and spaced apart from the first peripheral well region, and the second peripheral channel being located in the second peripheral well region; The second peripheral well region, the second peripheral source region, the second peripheral channel, the second peripheral drain region and the second peripheral gate structure together form the second peripheral transistor.

5. The method for preparing a semiconductor structure according to claim 3 or 4, characterized in that: After forming the second peripheral transistor, the method further includes: forming a plurality of peripheral contact structures and a plurality of array contact structures on the substrate; The array source region and the array drain region are respectively connected to different array contact structures, and the first peripheral source region, the first peripheral drain region, the second peripheral source region and the second peripheral drain region are respectively connected to different peripheral contact structures.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that: After forming the peripheral contact structure and the array contact structure, the method further includes: forming bit lines, capacitors, interconnect structures, and peripheral circuits; The array contact structure connected to the array source region is connected to the bit line, and the array contact structure connected to the array drain region is connected to the capacitor; the peripheral contact structures connected to the first peripheral source region and the second peripheral drain region are both connected to the peripheral circuit; and the peripheral contact structures connected to the first peripheral drain region and the second peripheral source region are both connected to the interconnection structure.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 4, characterized in that: The peripheral area includes a first peripheral area and a second peripheral area, the first peripheral area is arranged around the periphery of the array area, and the second peripheral area is arranged around the periphery of the first peripheral area; The first peripheral transistor is located in the first peripheral region or the second peripheral region; And / or, the second peripheral transistor is located in the first peripheral region or the second peripheral region.

8. The method for preparing a semiconductor structure according to claim 4, characterized in that: Providing the substrate, including: providing an initial substrate; Performing a doping process on the initial substrate to form the substrate, wherein the doped region forms the active region; The ion doping type of the substrate is different from the ion doping type of the first peripheral well region, and is the same as the ion doping type of the second peripheral well region.

9. The method for preparing a semiconductor structure according to claim 2, characterized in that: The first peripheral well region and the array well region are formed, comprising: forming a first mask layer on the substrate, wherein the first mask layer exposes a portion of the peripheral area and a portion of the array area; Performing doping treatment on the exposed peripheral region and the array region along the first mask layer to form the first peripheral well region in the peripheral region and the array well region in the array region; The first peripheral well region and the array well region have the same ion doping type.

10. The method for preparing a semiconductor structure according to claim 4, characterized in that: The second peripheral well region is formed, comprising: forming a second mask layer, wherein the second mask layer exposes a portion of the peripheral area; Performing doping treatment on the exposed peripheral region along the second mask layer to form the second peripheral well region in the peripheral region; The second peripheral well region and the first peripheral well region have different ion doping types.

11. The method for preparing a semiconductor structure according to claim 3, characterized in that: The first peripheral gate structure and the array gate structure are formed, comprising: forming a groove in the substrate of the array well region; forming a stack layer on the substrate, the stack layer comprising an initial gate dielectric layer, an initial gate semiconductor layer, an initial diffusion barrier layer and an initial gate metal layer stacked in sequence in a direction away from the substrate; Part of the stacked layer is removed, and the stacked layer corresponding to the first peripheral channel is retained to form the first peripheral gate structure, and the stacked layer located in the groove is retained to form the array gate structure.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that: The second peripheral gate structure is formed simultaneously with the first peripheral gate structure; The second peripheral gate structure is formed, comprising: A portion of the stacked layer is removed, and the stacked layer corresponding to the second peripheral channel is retained to form the second peripheral gate structure.

13. The method for preparing a semiconductor structure according to claim 1, characterized in that: Forming the array transistor and the first peripheral transistor includes: forming an array well region and a first peripheral well region, wherein the array well region is located in the array region and the first peripheral well region is located in the peripheral region; Forming the second peripheral transistor includes: forming a second peripheral well region, the second peripheral well region being located in the peripheral region and spaced apart from the first peripheral well region; forming an array source region, an array drain region and a second peripheral channel, wherein the array source region and the array drain region are both located in the array well region, an array channel is provided between the array source region and the array drain region, and the second peripheral channel is located in the second peripheral well region; forming an array gate structure, a first peripheral gate structure, and a second peripheral gate structure, wherein the array gate structure is located in the substrate and corresponds to the array channel, the first peripheral gate structure and the second peripheral gate structure are both located on the substrate, the first peripheral gate structure corresponds to the first peripheral channel, and the second peripheral gate structure corresponds to the second peripheral channel; forming a first peripheral source region and a first peripheral drain region, wherein the first peripheral source region and the first peripheral drain region are both located in the first peripheral well region, and the first peripheral channel is provided between the first peripheral source region and the first peripheral drain region; forming a second peripheral source region and a second peripheral drain region, wherein the second peripheral source region and the second peripheral drain region are both located in the second peripheral well region, and the second peripheral channel is provided between the second peripheral source region and the second peripheral drain region; Among them, the array well region, the array source region, the array channel, the array drain region and the array gate structure together form the array transistor; the first peripheral well region, the first peripheral source region, the first peripheral channel, the first peripheral drain region and the first peripheral gate structure together form the first peripheral transistor; the second peripheral well region, the second peripheral source region, the second peripheral channel, the second peripheral drain region and the second peripheral gate structure together form the second peripheral transistor.

14. The method for preparing a semiconductor structure according to claim 6, characterized in that: Forming the peripheral contact structure and the array contact structure includes: forming a dielectric layer, wherein the dielectric layer covers the substrate, the array transistor, the first peripheral transistor and the second peripheral transistor; forming a trench in the dielectric layer, the trench exposing the first peripheral source region, the first peripheral drain region, the second peripheral source region, the second peripheral drain region, the array source region, and the array drain region; A first conductive layer is filled in the groove, and the first conductive layer connected to the first peripheral source region, the first peripheral drain region, the second peripheral source region and the second peripheral drain region forms the peripheral contact structure, and the first conductive layer connected to the array source region and the array drain region forms the array contact structure.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: The capacitor comprises a first capacitor conductive layer, a capacitor dielectric layer and a second capacitor conductive layer; Forming the bit line, the capacitor, the interconnect structure and the peripheral circuit, comprising: forming a second conductive layer on the dielectric layer; Removing part of the second conductive layer, retaining the second conductive layer correspondingly connected to the array source region to form the bit line; retaining the second conductive layer correspondingly connected to the array drain region to form the first capacitor conductive layer; retaining the second conductive layer correspondingly connected to the first peripheral source region and the second peripheral drain region to form the peripheral circuit; retaining the second conductive layer correspondingly connected to the first peripheral drain region and the second peripheral source region to form the interconnection structure; forming a capacitor dielectric layer, wherein the capacitor dielectric layer is located on the first capacitor conductive layer; A second capacitor conductive layer is formed, wherein the second capacitor conductive layer is located on the capacitor dielectric layer.

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