Method for improving yield and reliability of chip

Abstract

The invention provides a method for improving the yield and reliability of chips, and the method comprises the steps: providing a wafer of at least one lot, the wafer comprises a plurality of chips, and each chip comprises a plurality of storage units comprising flash memories; performing a wafer acceptance test, and recording a threshold voltage when the storage unit of each wafer is in a programming state; generating an additional file according to the serial number of the lot, the serial number of the wafer and the threshold voltage when the storage unit of the corresponding wafer is in the programming state; the additional file is substituted into a first yield test, and in the first yield test, threshold voltage when a storage unit of a wafer is in a programming state is inherited as a parameter to enter a subsequent programming voltage adjustment process; a programming voltage adjusting process is carried out; and performing a second yield test, and adjusting an adjustment formula of the threshold voltage according to a test result in the second yield test. According to the invention, the programming condition can be finely adjusted according to the process difference so as to obtain the most suitable working condition, and the yield and reliability are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for improving chip yield and reliability. Background Art

[0002] NORD memory cell durability is directly related to program depth. Excessive programming operations will cause the memory cell transistor distribution to deteriorate, reducing its durability.

[0003] Due to process deviation, there are differences in programming characteristics between wafer to wafer (wafer to wafer) / lot to lot (wafer group to wafer group), some are stronger and some are weaker. Using uniform programming conditions will cause the weaker ones to lose yield and the stronger ones to have poor durability.

[0004] See also Figure 1 ,The current situation: a platform uses unified programming conditions, and process improvements need to be adjusted between different products, and reliability failures often occur.

[0005] At the same time, due to variations within the online process control range, the programming characteristics of wafers and wafers / wafer groups and wafer groups will also be different.

[0006] In order to solve the above problems, a new method to improve chip yield and reliability needs to be proposed. Summary of the invention

[0007] In view of the shortcomings of the prior art mentioned above, the purpose of the present invention is to provide a method for improving chip yield and reliability, which is used to solve the problem in the prior art that due to process deviation, there are differences in programming characteristics, some are stronger and some are weaker. Using unified programming conditions will cause the weaker ones to lose yield and the stronger ones to have poor durability.

[0008] To achieve the above objectives and other related objectives, the present invention provides a method for improving chip yield and reliability, comprising:

[0009] Step 1: providing a wafer of at least one lot, wherein the wafer comprises a plurality of chips, each of the chips comprising a plurality of storage units including flash memory;

[0010] Step 2: Performing a wafer acceptance test to record the threshold voltage of each memory cell of the wafer when it is in a programmed state;

[0011] Step 3, generating an additional file with the lot number, the wafer number and the threshold voltage of the corresponding storage unit of the wafer when it is in a programming state;

[0012] Step 4: Perform yield test and programming voltage adjustment:

[0013] Substituting the additional file into a first yield test, taking the threshold voltage of the memory cell of the wafer in a programming state as a parameter in the first yield test to enter the subsequent programming voltage adjustment process;

[0014] Performing the programming voltage adjustment process;

[0015] A second yield test is performed, and in the second yield test, the threshold voltage adjustment formula is adjusted according to the test result.

[0016] Preferably, step 2 further comprises the step of screening the threshold voltages that meet the standards, and obtaining the average value and standard deviation of the threshold voltages in each programming state after screening.

[0017] Preferably, in step three, it is determined whether the threshold voltage in the programming state meets the standard according to the 3-sigma rule.

[0018] Preferably, an inspection step is also included between step three and step four: determining whether the test values ​​of the wafer acceptance test meet the specification standards, and determining whether the parts with problems in the test are checked and processed; if not, re-performing the wafer acceptance test in step two; if so, performing the first yield test in step four.

[0019] Preferably, the programming voltage adjustment process in step four and the second yield test also include an inspection step: determining whether the test values ​​of the first yield test meet the specification standards, and determining whether the problematic parts of the test are checked and processed; if not, re-performing the first yield test and the programming voltage adjustment process in step four; if yes, performing the second yield test in step four.

[0020] Preferably, the threshold voltage of the memory cell of the wafer inherited in step 4 when it is in a programming state is used as a parameter to enter the subsequent programming voltage adjustment process by a table lookup method.

[0021] Preferably, the threshold voltage of the memory cell of the wafer inherited in step 4 when it is in a programming state is substituted into an empirical formula as a parameter to enter the subsequent programming voltage adjustment process.

[0022] Preferably, before the second yield test, the adjustment of the bit line programming voltage in the programming voltage adjustment process in step 4 includes: VBLP=default value+weight*VTP, VBLP is the bit line programming voltage, defaultvalue is the platform experience value, and VTP is the inherited threshold voltage.

[0023] Preferably, after the second yield test, the adjustment of the bit line programming voltage in the programming voltage adjustment process in step four includes: VBLP=default value+weight*VTP+weight*standardbin fail, VBLP is the bit line programming voltage, default value is the platform experience value, VTP is the inherited threshold voltage, and standardbinfail is the current number of failures.

[0024] As described above, the method for improving chip yield and reliability of the present invention has the following beneficial effects:

[0025] The present invention can fine-tune programming conditions according to process differences to obtain the most suitable working conditions and improve yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of wafer acceptance testing and yield testing of the prior art is shown;

[0027] Figure 2 It is a schematic diagram of the method for improving chip yield and reliability of the present invention. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0029] See also Figure 2 The present invention provides a method for improving chip yield and reliability, comprising:

[0030] Step 1: providing at least one lot of wafers, wherein the wafer includes a plurality of chips, each chip including a plurality of storage units including flash memory, such as MCU, etc.;

[0031] Step 2: Perform wafer acceptance test to record the threshold voltage of each wafer memory cell when it is in a programmed state;

[0032] In some embodiments, step 2 further includes the step of screening threshold voltages that meet the standards, and obtaining the average value and standard deviation of the threshold voltages in each programming state after screening.

[0033] Step 3: Generate an additional file with the lot number, the wafer number and the threshold voltage of the corresponding wafer memory cell when it is in the programming state;

[0034] In some embodiments, in step 3, whether the threshold voltage in the programming state meets the standard is determined according to the 3-sigma rule. The 3-sigma principle is also called the Laida criterion. It first assumes that a set of detection data contains only random errors, calculates and processes them to obtain the standard deviation, and determines an interval according to a certain probability. It is believed that any error exceeding this interval is not a random error but a gross error, and the data containing the error should be eliminated. In other embodiments, other well-known data processing methods can also be used.

[0035] In some embodiments, an inspection step is also included between step three and step four: determining whether the test values ​​of the wafer acceptance test meet the specification standards, and determining whether the parts with problems in the test are checked and processed; if not, re-performing the wafer acceptance test in step two; if so, performing the first yield test in step four.

[0036] Step 4: Perform yield test and programming voltage adjustment:

[0037] Substituting the additional file into the first yield test, taking the threshold voltage of the memory cell of the inherited wafer in the programming state in the first yield test as a parameter to enter the subsequent programming voltage adjustment process;

[0038] Perform programming voltage adjustment process;

[0039] A second yield test is performed. In the second yield test, the threshold voltage adjustment formula is adjusted according to the test results. The programming conditions can be dynamically adjusted according to the characteristics of different wafers, which will be able to well control the yield and improve reliability.

[0040] In some embodiments, the programming voltage adjustment process in step four and the second yield test also include an inspection step: determining whether the test values ​​of the first yield test meet the specification standards, and determining whether the parts of the test with problems are checked and processed; if not, re-performing the first yield test and programming voltage adjustment process in step four; if so, performing the second yield test in step four.

[0041] In some embodiments, the threshold voltage of the memory cell of the inherited wafer in step 4 when in a programming state is used as a parameter to enter the subsequent programming voltage adjustment process by a table lookup method, and this method is applicable to parameters corresponding to known threshold voltages.

[0042] In some embodiments, the threshold voltage of the memory cell of the inherited wafer in the programming state in step 4 is substituted into an empirical formula as a parameter to enter the subsequent programming voltage adjustment process.

[0043] In some embodiments, before the second yield test, the bit line programming voltage is adjusted in the programming voltage adjustment process in step 4, including: VBLP = default value + weight * VTP, VBLP is the bit line programming voltage, default value is the platform experience value, and VTP is the inherited threshold voltage. The adjustment of the bit line programming voltage has little effect on the memory cell. In other embodiments, other programming voltages can also be adjusted according to actual needs.

[0044] In some embodiments, after the second yield test, the adjustment of the bit line programming voltage in the programming voltage adjustment process in step four includes: VBLP=default value+weight*VTP+weight*standard bin fail, VBLP is the bit line programming voltage, default value is the platform experience value, VTP is the inherited threshold voltage, and standard bin fail is the current number of failures.

[0045] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0046] In summary, the present invention can fine-tune programming conditions according to process differences to obtain the most suitable working conditions and improve yield and reliability. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0047] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for improving chip yield and reliability, characterized in that: At least: Step 1: providing a wafer of at least one lot, wherein the wafer comprises a plurality of chips, each of the chips comprising a plurality of storage units including flash memory; Step 2: Performing a wafer acceptance test to record the threshold voltage of each memory cell of the wafer when it is in a programmed state; Step 3, generating an additional file with the lot number, the wafer number and the threshold voltage of the corresponding storage unit of the wafer when it is in a programming state; Step 4: Perform yield test and programming voltage adjustment: Substituting the additional file into a first yield test, taking the threshold voltage of the memory cell of the wafer in a programming state as a parameter in the first yield test to enter the subsequent programming voltage adjustment process; Performing the programming voltage adjustment process; A second yield test is performed, and in the second yield test, the threshold voltage adjustment formula is adjusted according to the test result.

2. The method for improving chip yield and reliability according to claim 1, characterized in that: Step 2 also includes the step of screening the threshold voltages that meet the standards, and obtaining the average value and standard deviation of the threshold voltages in each programming state after screening.

3. The method for improving chip yield and reliability according to claim 2, characterized in that: In step three, it is determined whether the threshold voltage in the programming state meets the standard according to the 3-sigma rule.

4. The method for improving chip yield and reliability according to claim 1, characterized in that: Between step 3 and step 4, there is also an inspection step: determining whether each test value of the wafer undergoing the test meets the specification standard, and determining whether the part with a problem in the test is inspected and processed; If not, the wafer acceptance test in step 2 is performed again; if so, the first yield test in step 4 is performed.

5. The method for improving chip yield and reliability according to claim 1, characterized in that: The programming voltage adjustment process in step 4 and the second yield test also include an inspection step: determining whether each test value of the first yield test meets the specification standard, and determining whether the part with problems in the test is inspected and processed; If not, re-performing the first yield test and the programming voltage adjustment process in step 4; If yes, the second yield test in step 4 is performed.

6. The method for improving chip yield and reliability according to claim 1, characterized in that: The threshold voltage of the memory cell of the wafer inherited in step 4 when it is in a programming state is used as a parameter to enter the subsequent programming voltage adjustment process by looking up a table.

7. The method for improving chip yield and reliability according to claim 1, characterized in that: The threshold voltage of the memory cell of the wafer inherited in step 4 when in a programming state is substituted into an empirical formula as a parameter to enter the subsequent programming voltage adjustment process.

8. The method for improving chip yield and reliability according to claim 1, characterized in that: Before the second yield test, the adjustment of the bit line programming voltage in the programming voltage adjustment process in step 4 includes: VBLP=defaultvalue+weight*VTP, VBLP is the bit line programming voltage, default value is the platform experience value, and VTP is the inherited threshold voltage.

9. The method for improving chip yield and reliability according to claim 1 or 8, characterized in that: In step 4, relevant failure examples of the second yield test are used as input to adjust the adjustment formula of the threshold voltage.

10. The method for improving chip yield and reliability according to claim 9, characterized in that: After the second yield test, the adjustment of the bit line programming voltage in the programming voltage adjustment process in step four includes: VBLP=default value+weight*VTP+weight*standard bin fail, VBLP is the bit line programming voltage, defaultvalue is the platform experience value, VTP is the inherited threshold voltage, and standard bin fail is the current number of failures.

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