Manufacturing method of semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and aims to improve the yield of the semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: forming a fin-shaped structure on a semiconductor substrate; the fin-shaped structure comprises first sacrificial layers and channel layers which are alternately stacked, and second sacrificial layers and third sacrificial layers which are alternately stacked. The material of one of the second sacrificial layer and the third sacrificial layer comprises silicon or germanium silicon, and the material of the other comprises germanium silicon or germanium. The difference value between the germanium content in the second sacrificial layer and the germanium content in the third sacrificial layer is smaller than 15%, and the second sacrificial layer is doped with an etching auxiliary agent. And forming a mask structure across the fin-shaped structure. And selectively removing the second sacrificial layer at least under the accelerated etching action of the etching auxiliary agent so as to form a first medium filling region. And forming a first middle dielectric isolation layer in the first dielectric filling area. And removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer which are not covered by the mask structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device. Background Art

[0002] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby facilitating the improvement of the operating performance and integration of the semiconductor device.

[0003] However, the existing method for manufacturing the three-dimensional stacked complementary transistor has high requirements on the processing technology, which makes the manufacturing of the three-dimensional stacked complementary transistor relatively difficult, resulting in a low yield of the three-dimensional stacked complementary transistor. Summary of the invention

[0004] The purpose of the present invention is to provide a method for manufacturing a semiconductor device, which is used to alleviate the problems in the prior art that the stress distribution and stress matching between films need to be considered due to the large material difference between the second sacrificial layer and the third sacrificial layer, and reduce the limitation of the critical thickness of epitaxy. In addition, the difficulty of manufacturing the middle dielectric isolation layer is reduced, and the yield of the semiconductor device is improved.

[0005] In order to achieve the above-mentioned object, the present invention provides a method for manufacturing a semiconductor device, which comprises: first, forming a fin structure on a semiconductor substrate. Along the thickness direction of the semiconductor substrate, the fin structure comprises an alternately stacked first sacrificial layer and a channel layer, and an alternately stacked second sacrificial layer and a third sacrificial layer. The alternately stacked first sacrificial layer and the channel layer are located on both sides of the alternately stacked second sacrificial layer and the third sacrificial layer along the thickness direction. The film layers located at the bottom and top layers of the alternately stacked first sacrificial layer and the channel layer are both first sacrificial layers. The film layers located at the bottom and top layers of the alternately stacked second sacrificial layer and the third sacrificial layer are both second sacrificial layers. The material of one of the second sacrificial layer and the third sacrificial layer comprises silicon or silicon germanium, and the material of the other comprises silicon germanium or germanium. The difference in the germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching auxiliary agent. Next, a mask structure is formed across the fin structure. Next, at least under the accelerated etching action of the etching auxiliary agent, the second sacrificial layer is selectively removed to form a first dielectric filling area. The third sacrificial layer is retained. Next, a first middle dielectric isolation layer is formed in the first dielectric filling region. Next, the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer not covered by the mask structure are removed. Next, a first source region and a first drain region are formed on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer. Next, an insulating layer is formed on the first source region and the first drain region. Next, a second source region and a second drain region are formed on the insulating layer and on both sides of the remaining first sacrificial layer and the channel layer above the remaining first middle dielectric isolation layer. The conductivity type of the second source region and the second drain region is opposite to the conductivity type of the first source region and the first drain region.

[0006] In the case of adopting the above technical solution, in the manufacturing method provided by the present invention, the first sacrificial layer, the second sacrificial layer and the third sacrificial layer have different functions respectively. Specifically, the remaining channel layer (the remaining channel layer is used to form the channel region) will be released by selectively removing the portion of the first sacrificial layer corresponding to the gate formation region, so as to form a gate stack structure surrounding the periphery of the remaining channel layer. Subsequently, the first middle dielectric isolation layer for isolating the gate stack structure of the upper device included in the three-dimensional stacked complementary transistor from the gate stack structure of the lower device will be formed by selectively etching the second sacrificial layer. As for the above-mentioned third sacrificial layer, the position where the portion of the third sacrificial layer corresponding to the gate formation region is located may subsequently form a gate stack structure, or may form an insulating dielectric material for isolation. Based on this, the existing manufacturing method completely achieves sufficient etching selectivity of the three by limiting the types of materials of the first sacrificial layer, the second sacrificial layer and the third sacrificial layer. In the manufacturing method provided by the present invention, when the material of one of the second sacrificial layer and the third sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%. At this time, the material difference between the second sacrificial layer and the third sacrificial layer is small, and the corresponding lattice difference between the two is also small. When the material used for epitaxy to manufacture the second sacrificial layer and the third sacrificial layer is large, it can alleviate the problems of stress distribution and stress matching between films that need to be considered in the prior art due to the large material difference between the second sacrificial layer and the third sacrificial layer, and reduce the limitation of the critical thickness of epitaxy. There is no need to form more layers of second sacrificial layers and third sacrificial layers with smaller layer thicknesses as in the existing manufacturing method, or there is no need to form a fixed number of second sacrificial layers and third sacrificial layers due to the critical thickness limitation, resulting in a smaller thickness of the insulating layer used to isolate the first source region and the first drain region, and the second source region and the second drain region, to prevent leakage.

[0007] Furthermore, the second sacrificial layer is doped with an etching auxiliary agent. With such a configuration, the second sacrificial layer can be selectively removed at least under the accelerated etching effect of the etching auxiliary agent, and the third sacrificial layer can be retained to improve the yield of the semiconductor device. In addition, the manufacturing method provided by the present invention is to form the first middle dielectric isolation layer in advance before the source and drain etching. At this time, although the aspect ratio of the fin-shaped structure may still be large, during the etching of the insulating dielectric material used to manufacture the first middle dielectric isolation layer, even if the insulating dielectric material at the bottom of the gap between adjacent fin-shaped structures is not completely removed, it will not affect the formation of the first source region and the first drain region of the subsequent lower device, and will not affect the contact between the first source region and the first drain region of the lower device and the first channel region respectively; and the insulating dielectric material remaining at the bottom of the gap between adjacent fin-shaped structures can further isolate different semiconductor devices formed based on different fin-shaped structures, reduce the risk of leakage, and increase the yield of the manufactured semiconductor device while also helping to improve the working performance of the manufactured semiconductor device.

[0008] In one example, the etching auxiliary agent is an N-type dopant.

[0009] In one example, a wet etching process or an isotropic dry etching process is used to selectively remove the second sacrificial layer.

[0010] In one example, the doping concentration of the etching auxiliary agent in the second sacrificial layer is greater than or equal to 1E18 cm -3 , and less than or equal to 1E19cm -3 .

[0011] In one example, when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution includes a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0012] In one example, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 , and He.

[0013] In one example, the thickness of the second sacrificial layer and / or the third sacrificial layer is greater than or equal to 10 nm and less than or equal to 30 nm.

[0014] In one example, an in-situ doping method is used to dope the etching auxiliary agent into the second sacrificial layer.

[0015] In one example, the second sacrificial layer and the third sacrificial layer are made of the same material.

[0016] In one example, the material of the first sacrificial layer is the same as the material of the third sacrificial layer.

[0017] In one example, after removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the third sacrificial layer that are not covered by the mask structure, before forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the method for manufacturing a semiconductor device further includes: removing the edge portions on both sides of each remaining first sacrificial layer along the length direction of the fin structure to form a second dielectric filling region. Next, an inner sidewall is formed in the second dielectric filling region.

[0018] In one example, the mask structure includes a sacrificial gate.

[0019] In one example, while the first middle dielectric isolation layer is formed in the dielectric filling region, gate sidewalls are formed at least on two sides of the mask structure along the length direction of the fin structure.

[0020] In one example, the material of the first middle dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

[0021] In one example, after forming the second source region and the second drain region, the method for manufacturing a semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate. Next, removing the mask structure. Next, removing the remaining first sacrificial layer, and removing the remaining third sacrificial layer. Next, forming a gate stack structure at least surrounding the periphery of the remaining channel layer.

[0022] In one example, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after removing the mask structure and before removing the remaining first sacrificial layer, the method for manufacturing a semiconductor device includes: removing the third sacrificial layer to form a third dielectric filling region. Next, forming a second middle dielectric isolation layer in the third dielectric filling region.

[0023] In one example, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after forming the first middle dielectric isolation layer in the first dielectric filling region, before forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the method for manufacturing a semiconductor device includes: selectively removing the third sacrificial layer to form a third dielectric filling region. Forming a second middle dielectric isolation layer in the third dielectric filling region. Removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer, and the second middle dielectric isolation layer that are not covered by the mask structure.

[0024] Furthermore, after forming the second source region and the second drain region, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate, removing the mask structure, removing the remaining first sacrificial layer, and forming a gate stack structure surrounding the periphery of the remaining channel layer.

[0025] In one example, the material of the second middle dielectric isolation layer is the same as the material of the first middle dielectric isolation layer.

[0026] In one example, the dielectric constant of the material of the second middle dielectric isolation layer is smaller than the dielectric constant of the material of the first middle dielectric isolation layer.

[0027] In one example, the material of the first middle dielectric isolation layer includes at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0029] Figure 1 A flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 2 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 1 ;

[0031] Figure 3 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 ;

[0032] Figure 4 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 ;

[0033] Figure 5 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 4 ;

[0034] Figure 6 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 5 ;

[0035] Figure 7 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 6 ;

[0036] Figure 8A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 7 ;

[0037] Fig. 9 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 8 ;

[0038] Fig.10 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 9 ;

[0039] Fig.11 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 ;

[0040] Fig.12 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 one;

[0041] Fig.13 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 two;

[0042] Fig.14 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 three;

[0043] Fig.15 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 Four;

[0044] Fig.16 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 five;

[0045] Fig.17 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 six;

[0046] Fig.18 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 seven;

[0047] Fig.19A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 eight;

[0048] Fig. 20 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 10 Nine;

[0049] Fig.21 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 ten;

[0050] Fig. 22 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 eleven;

[0051] Fig.23 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 twelve;

[0052] Fig.24 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 Thirteen;

[0053] Fig.25 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 fourteen;

[0054] Fig.26 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 fifteen;

[0055] Fig. 27 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 sixteen;

[0056] Fig.28 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 XVII;

[0057] Fig.29 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 eighteen;

[0058] Fig.30A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 2 nineteen;

[0059] Fig.31 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 ten;

[0060] Fig.32 A schematic diagram of the structure of a semiconductor device manufactured by the manufacturing method provided by an embodiment of the present invention during the manufacturing process Figure 3 eleven.

[0061] Figure numerals: 11 is a semiconductor substrate, 12 is a fin structure, 13 is a first sacrificial layer, 14 is a channel layer, 15 is a second sacrificial layer, 16 is a third sacrificial layer, 17 is a shallow trench isolation structure, 18 is a mask structure, 19 is a first dielectric filling area, 20 is a first middle dielectric isolation layer, 21 is a first source region, 22 is a first drain region, 23 is an insulating layer, 24 is a second source region, 25 is a second drain region, 26 is a second dielectric filling area, 27 is an inner side wall, 28 is a gate side wall, 29 is an interlayer dielectric layer, 30 is a gate stack structure, 31 is a third dielectric filling area, and 32 is a second middle dielectric isolation layer. DETAILED DESCRIPTION

[0062] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concept of the present invention.

[0063] Various structural schematic diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for a clearer expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0064] In the context of the present invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0066] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] The three-dimensional stacked complementary transistor includes vertically stacked N-type transistors and P-type transistors, eliminating the lateral spacing between the N-type transistors and the P-type transistors, which allows the effective channel width to be further increased, thereby facilitating the improvement of the operating performance and integration of the semiconductor device.

[0068] However, the existing manufacturing methods of three-dimensional stacked complementary transistors have high requirements on the processing technology, which makes it difficult to manufacture three-dimensional stacked complementary transistors and is not conducive to improving the working performance of three-dimensional stacked complementary transistors. Among them, the existing manufacturing methods of three-dimensional stacked complementary transistors mainly include the following two integration schemes:

[0069] The first method: using a monolithic method to manufacture a three-dimensional stacked complementary transistor. Specifically, taking the N-type transistor and the P-type transistor as ring-gate transistors, and the P-type transistor is located above the N-type transistor as an example, the process of manufacturing a three-dimensional stacked complementary transistor using the existing manufacturing method is described: First, a fin structure is formed on a semiconductor substrate. The fin structure includes at least two stacked layers. Each stacked layer includes a sacrificial layer, and a channel layer located on the sacrificial layer, and the materials of the sacrificial layer and the channel layer are both semiconductor materials. Next, a sacrificial gate and sidewalls are formed across part of the fin structure. And using the sacrificial gate and the sidewall as a mask, the fin structure is selectively etched to remove the portion of the fin structure exposed outside the sacrificial gate and the sidewall. Then, a first semiconductor material for manufacturing the source region and the drain region included in the N-type transistor is formed on the semiconductor substrate. At this time, since the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor and the P-type transistor are exposed after being etched, the remaining parts of these sacrificial layers and the channel layer can be used as seed layers for the epitaxial growth of the first semiconductor material. Therefore, the first semiconductor material is formed not only on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the N-type transistor after being etched, but also on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched. Next, it is necessary to remove the first semiconductor material located on both sides of the remaining parts of the sacrificial layer and the channel layer corresponding to the P-type transistor after being etched, and the remaining parts of the first semiconductor material form the source region and the drain region included in the N-type transistor. Then, an epitaxial isolation layer is formed covering the surface of the source region and the drain region of the N-type transistor away from the substrate; and the source region and the drain region of the P-type transistor are formed on the epitaxial isolation layer by an epitaxial growth process. Finally, the sacrificial gate and the part of the sacrificial layer located in the gate formation area are removed; and a gate stack structure surrounding the periphery of the channel area is formed to obtain a three-dimensional stacked complementary transistor.

[0070] The second method is to use a sequential method to manufacture a three-dimensional stacked complementary transistor. This method is to form the bottom transistor according to the manufacturing process of conventional semiconductor devices, and after forming the corresponding contact electrodes of the bottom transistor, use wafer-to-wafer bonding technology to cover a semiconductor layer on the top of the bottom transistor by wafer transfer. Then, the top transistor is integrated based on the semiconductor layer, and the top gate and bottom gate are connected to obtain a three-dimensional stacked complementary transistor.

[0071] It can be seen from the manufacturing process of the first method mentioned above that in the first method of manufacturing a three-dimensional stacked complementary transistor, an epitaxial process is required to form a channel layer and a sacrificial layer of a semiconductor material. However, epitaxial materials need to consider issues such as stress distribution and stress matching between thin films, which brings great technical challenges to the manufacture of three-dimensional stacked complementary transistors. In addition, in the first manufacturing method mentioned above, the structure has a large aspect ratio. When making the middle dielectric isolation (Middle Dielectric Isolation, which can be abbreviated as MDI) used to isolate the upper and lower devices, after forming the sacrificial gate and etching the source and drain, the depth and width of the gap between adjacent fin structures are relatively large, which easily leads to the difficulty of cleaning the insulating dielectric material located at the bottom of the gap between adjacent fin structures after filling the insulating dielectric material used to manufacture the middle dielectric isolation, thereby affecting the formation of the source and drain regions of the subsequent lower device and affecting the device performance. In addition, in order to form the above-mentioned middle dielectric isolation, it is necessary to add at least another sacrificial layer of material. At this time, in the current manufacturing method, there are at least three different semiconductor materials in the channel layer and sacrificial layer grown by epitaxy, which further increases the difficulty of epitaxy. Secondly, due to the limitation of the critical thickness of epitaxy, when the difference between different materials is large, if the quality of the formed film layer is to be guaranteed, the thickness of the film layer formed in a single time can only be reduced. Based on this, if only a fixed number of overlapping sacrificial layers are formed at the position corresponding to the middle dielectric isolation, the thickness of the insulating layer isolating the first source region and the first drain region, and the second source region and the second drain region will also be small, making it difficult to prevent leakage. If the insulating layer is to be guaranteed to have sufficient follow-up, it is necessary to alternately form more sacrificial layers, resulting in a complicated process.

[0072] If the above-mentioned middle dielectric isolation is not formed, on the one hand, it will affect the leakage or interference between the upper and lower layer devices. On the other hand, when the upper and lower layer devices use different metal gate materials, it is necessary to fill the gate formation area with protective materials such as spin-coated carbon and perform back etching to expose only the nanostructure of the upper layer device. At this time, if there is no middle dielectric isolation, when the above-mentioned protective material is etched back, the part of the protective material located under the nanostructure included in the upper layer device is difficult to clean, thereby affecting the subsequent formation of the first layer of metal gate and affecting device performance.

[0073] As for the second method of manufacturing the three-dimensional stacked complementary transistor mentioned above, the bonding scheme it adopts has technical challenges such as alignment, and has high requirements on the process, which makes the manufacturing of the three-dimensional stacked complementary transistor more difficult and is not conducive to improving the working performance of the three-dimensional stacked complementary transistor.

[0074] In order to solve the above technical problems, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Among them, in the method for manufacturing a semiconductor device provided by an embodiment of the present invention, the difference in the germanium content in the second sacrificial layer and the third sacrificial layer is less than 15%. At this time, the material difference between the second sacrificial layer and the third sacrificial layer is small, which can alleviate the problems of stress distribution and stress matching between films that need to be considered due to the large material difference between the second sacrificial layer and the third sacrificial layer in the prior art. In addition, before the source and drain etching is performed, the formation operation of the first middle dielectric isolation layer is performed in advance, which will not affect the formation of the first source region and the first drain region of the subsequent lower layer device, and the contact between the two and the first channel region, thereby increasing the yield of the manufactured semiconductor device.

[0075] like Figure 1 As shown, an embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 2 to 32 The manufacturing process is described in detail with reference to the cross-sectional view or stereoscopic view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes the following steps:

[0076] First, if Figure 2 and Figure 3 As shown, a fin structure 12 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the fin structure 12 includes an alternately stacked first sacrificial layer 13 and a channel layer 14, and an alternately stacked second sacrificial layer 15 and a third sacrificial layer 16. The alternately stacked first sacrificial layer 13 and the channel layer 14 are located on both sides of the alternately stacked second sacrificial layer 15 and the third sacrificial layer 16 along the thickness direction. The film layers located at the bottom and top layers of the alternately stacked first sacrificial layer 13 and the channel layer 14 are both the first sacrificial layer 13. The film layers located at the bottom and top layers of the alternately stacked second sacrificial layer 15 and the third sacrificial layer 16 are both the second sacrificial layer 15. The material of one of the second sacrificial layer 15 and the third sacrificial layer 16 includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium. The difference in the germanium content in the second sacrificial layer 15 and the third sacrificial layer 16 is less than 15%, and the second sacrificial layer 15 is doped with an etching auxiliary agent.

[0077] Specifically, along the thickness direction of the semiconductor substrate, the alternately stacked first sacrificial layers and channel layers located below the alternately stacked second sacrificial layers and third sacrificial layers are used to manufacture the lower layer devices in the three-dimensional stacked complementary transistor. Based on this, the number and material of the alternately stacked first sacrificial layers and channel layers located below the alternately stacked second sacrificial layers and third sacrificial layers can be determined according to the requirements for the above-mentioned lower layer devices in actual application scenarios.

[0078] Among them, the number of layers of the channel layer located below the alternately stacked second sacrificial layer and the third sacrificial layer can be one layer or multiple layers. The material of the channel layer can include any semiconductor material such as silicon, silicon germanium or germanium. In addition, since it is necessary to release the first channel region included in the lower device by removing the first sacrificial layer covered by the mask structure in the future. Moreover, when the second sacrificial layer is selectively removed, the first sacrificial layer and the third sacrificial layer need to be retained, so the material of the first sacrificial layer can be any semiconductor material that has a certain etching selectivity ratio with the materials of the channel layer and the second sacrificial layer, respectively. For example: when the material of the channel layer is silicon and the material of the second sacrificial layer is silicon germanium, the material of the first sacrificial layer can be silicon germanium or germanium, and the germanium content in the first sacrificial layer and the second sacrificial layer is different.

[0079] Secondly, in the actual application process, the material of the first sacrificial layer can be the same as the material of the third sacrificial layer; in this case, after the mask structure is removed, the remaining first sacrificial layer and the third sacrificial layer can be removed at the same time, which can improve the manufacturing efficiency and reduce the types of materials of different film layers of the fin structure, which can further alleviate the need for epitaxial materials to consider issues such as stress distribution and stress matching between films, thereby reducing the difficulty of manufacturing. Alternatively, the materials of the first sacrificial layer and the third sacrificial layer can also be different; in this case, it is convenient to release the first sacrificial layer and the third sacrificial layer separately according to different actual needs, thereby improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios.

[0080] As for the above-mentioned alternately stacked second sacrificial layer and third sacrificial layer, the first dielectric filling area for manufacturing the first middle dielectric isolation layer will be released by removing the second sacrificial layer. The alternately stacked second sacrificial layer and the third sacrificial layer are provided on the one hand to form the first middle dielectric isolation layer, and on the other hand to form an insulating layer for separating the first source region and the first drain region from the second source region and the second drain region, respectively, so that the insulating layer can have a sufficiently large thickness to ensure that the insulating layer has high insulating properties, while also reducing the difficulty of filling the first middle dielectric isolation layer, especially when the first middle dielectric isolation layer is formed at the same time as the gate sidewall (to improve manufacturing efficiency), it is prevented that the insulating dielectric material used to manufacture the gate sidewall is difficult to fill the first dielectric filling area with a large thickness, thereby reducing the manufacturing difficulty and improving the yield of the semiconductor device. Therefore, the thickness of the single-layer second sacrificial layer can refer to the thickness of the gate sidewall, and the total thickness of the alternately stacked second sacrificial layer and the third sacrificial layer can refer to the thickness of the insulating layer in the actual application scenario.

[0081] It should be noted that, because the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, the material difference between the second sacrificial layer and the third sacrificial layer is small, and the corresponding lattice difference between the two is also small. When epitaxy is used to manufacture the materials of the second sacrificial layer and the third sacrificial layer, it can alleviate the problems of stress distribution and stress matching between films in the prior art due to the large material difference between the second sacrificial layer and the third sacrificial layer, and reduce the limitation of the critical thickness of epitaxy. Based on this, the specific thickness of each second sacrificial layer and the third sacrificial layer can be determined according to the number of layers of the alternating second sacrificial layer and the third sacrificial layer in the actual application scenario, and the thickness requirements of the insulating layer, which are not specifically limited here.

[0082] Exemplarily, the thickness of the second sacrificial layer and / or the third sacrificial layer may be greater than or equal to 10 nm and less than or equal to 30 nm. For example, the thickness of the second sacrificial layer and / or the third sacrificial layer may be 10 nm, 12 nm, 15 nm, 18 nm, 20 nm, 25 nm, 28 nm or 30 nm.

[0083] In addition, in the embodiment of the present invention, the material of the second sacrificial layer may include silicon or silicon germanium, and the material of the third sacrificial layer may include silicon germanium or germanium; or, the material of the second sacrificial layer may include silicon germanium or germanium, and the material of the third sacrificial layer may include silicon germanium or germanium. In addition, it can be understood that when the difference in the germanium content in the second sacrificial layer and the third sacrificial layer is greater, the material difference between the two is greater, and the etching selectivity is greater. In addition, the type of etching auxiliary agent doped in the second sacrificial layer and the doping concentration of the etching auxiliary agent doped in the second sacrificial layer will also affect the etching rate of the second sacrificial layer. Specifically, when other factors are the same, the greater the concentration of the etching auxiliary agent doped in the second sacrificial layer, when the second sacrificial layer is selectively etched, the greater the etching rate of the etching auxiliary agent on the second sacrificial layer, and the greater the etching selectivity between the second sacrificial layer and the third sacrificial layer. Therefore, the germanium content in each of the second sacrificial layer and the third sacrificial layer, the type of etching auxiliary agent in the second sacrificial layer, and the doping concentration of the etching auxiliary agent in the second sacrificial layer can be determined according to the requirements for the etching selectivity between the second sacrificial layer and the third sacrificial layer in the actual application scenario.

[0084] Exemplarily, the materials of the second sacrificial layer and the third sacrificial layer can be the same. For example, the second sacrificial layer and the third sacrificial layer can both be silicon, silicon germanium or germanium. Of course, the materials of the second sacrificial layer and the third sacrificial layer can also be different. For example, the difference in germanium content between the second sacrificial layer and the third sacrificial layer can be 1%, 1.5%, 2%, 2.5%, 3%, 3.5%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc.

[0085] Exemplarily, the etching auxiliary agent may be an N-type dopant, such as phosphorus or arsenic.

[0086] Exemplarily, the doping concentration of the etching auxiliary agent in the second sacrificial layer may be greater than or equal to 1E18 cm -3 , and less than or equal to 1E19cm -3 For example, the doping concentration of the etching auxiliary agent in the second sacrificial layer can be 1E18cm -3 、2E18cm -3 、3E18cm -3 、4E18cm -3 、5E18cm -3 、6E18cm -3 、8E18cm -3 or 1E19cm -3 In this case, the doping concentration of the etching auxiliary agent in the second sacrificial layer is within the above range, which is conducive to preventing the etching auxiliary agent from having a weak etching auxiliary effect on the second sacrificial layer due to the low doping concentration, and is conducive to further reducing the material difference between the second sacrificial layer and the third sacrificial layer. In addition, it can also prevent the difficulty of doping the etching auxiliary agent in the second sacrificial layer due to the high doping concentration, thereby reducing the difficulty of manufacturing semiconductor devices.

[0087] In addition, along the thickness direction of the semiconductor substrate, the alternately stacked first sacrificial layer and the channel layer located above the alternately stacked second sacrificial layer and the third sacrificial layer are used to manufacture the upper device in the three-dimensional stacked complementary transistor. Based on this, the number and material of the alternately stacked first sacrificial layer and the channel layer located above the alternately stacked second sacrificial layer and the third sacrificial layer can be determined according to the requirements for the above-mentioned upper device in the actual application scenario, and no specific limitation is made here.

[0088] In the actual manufacturing process, Figure 2 As shown, epitaxy and other processes can be used to form material layers for manufacturing the alternating first sacrificial layer and channel layer, and the alternating second sacrificial layer and third sacrificial layer along the thickness direction of the semiconductor substrate 11. When forming the second sacrificial layer, an in-situ doping method can be used to dope an etching aid into the second sacrificial layer to improve manufacturing efficiency. Alternatively, after forming the second sacrificial layer, the second sacrificial layer can be doped by ion implantation or diffusion. Then, photolithography and etching processes are used to pattern the above-mentioned material layers and part of the semiconductor substrate to form fins. Next, as shown in FIG. Figure 3 As shown, a shallow trench isolation structure 17 for defining an active area can be formed between adjacent fins by using processes such as deposition and etching. The top height of the shallow trench isolation structure 17 is less than or equal to the bottom height of the first sacrificial layer 13 located at the bottom. The portion of the fin exposed outside the shallow trench isolation structure 17 is a fin-shaped structure 12.

[0089] Next, if Figure 4 As shown, a mask structure 18 is formed across the fin structure 12 .

[0090] In the actual manufacturing process, a deposition process can be used to form a mask material covering the semiconductor substrate. Then, processes such as photolithography and etching are used to selectively etch the mask material to form the above-mentioned mask structure. As for the material of the mask structure, it can be set according to actual needs, as long as it can play a protective role in the subsequent mask.

[0091] Exemplarily, the mask structure may include a sacrificial gate. The material of the sacrificial gate may include a material that is easy to remove, such as polysilicon. Secondly, the mask structure may also include a gate oxide layer and a sacrificial gate located on the gate oxide layer. The material of the gate oxide layer may include a material such as silicon oxide.

[0092] Next, if Figure 5 As shown, at least under the accelerated etching effect of the etching auxiliary agent, the second sacrificial layer 15 is selectively removed to form the first dielectric filling region 19. The third sacrificial layer 16 is retained.

[0093] Specifically, the second sacrificial layer can be selectively removed by wet etching or isotropic dry etching, etc. The specific type of etchant and etching conditions used can be determined according to the type and doping concentration of the etching auxiliary agent and the actual application scenario, and are not specifically limited here.

[0094] For example, when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution may include a mixed solution of hydrofluoric acid and hydrogen peroxide.

[0095] Exemplarily, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 and He.

[0096] Next, if Figure 6 As shown, a first middle dielectric isolation layer 20 is formed in the first dielectric filling region.

[0097] In the actual manufacturing process, the insulating dielectric material covering the semiconductor substrate can be formed by deposition and other processes. Then, the portion of the insulating dielectric material outside the first dielectric filling area can be completely removed by etching, and the first middle dielectric isolation layer can be formed based on the insulating dielectric material. Alternatively, the portion of the insulating dielectric material located in the first dielectric filling area and outside the sidewalls of the mask structure can be completely removed, and the first middle dielectric isolation layer and the gate sidewall can be formed based on the insulating dielectric material. In other words, Figure 6As shown, while the first middle dielectric isolation layer 20 is formed in the first dielectric filling region 19 , a gate sidewall 28 is formed at least on both sides of the mask structure 18 along the length direction of the fin structure 12 . At this time, the material of the gate sidewall 28 is the same as that of the first middle dielectric isolation layer 20 .

[0098] The material of the first middle dielectric isolation layer may include any insulating dielectric material as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0099] Exemplarily, the material of the first middle dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

[0100] Next, if Figures 7 to 10 As shown, the first sacrificial layer 13 , the channel layer 14 , the first middle dielectric isolation layer 20 and the third sacrificial layer 16 that are not covered by the mask structure 18 are removed.

[0101] In the actual manufacturing process, Figure 6 and Fig. 9 As shown, after forming the first middle dielectric isolation layer 20, the first sacrificial layer 13, the channel layer 14, the first middle dielectric isolation layer 20 and the third sacrificial layer 16 not covered by the mask structure 18 can be removed together to facilitate the subsequent formation of the first source region, the first drain region, the second source region and the second drain region.

[0102] Alternatively, when the material of the first sacrificial layer is different from the material of the third sacrificial layer, as Figure 7 As shown, the third sacrificial layer may be selectively removed first to form a third dielectric filling region 31; then, as shown Figure 8 As shown in FIG. 1 , a second middle dielectric isolation layer 32 is formed in the third dielectric filling region. Next, as shown in FIG. Fig.10 As shown, the first sacrificial layer 13, the channel layer 14, the first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32 that are not covered by the mask structure 18 are removed. At this time, when the gate stack structure is subsequently formed, the gate stack structure will not fill the gap between the two adjacent first middle dielectric isolation layers 20, thereby reducing parasitic capacitance and further improving the working performance of the manufactured semiconductor device.

[0103] The material of the second middle dielectric isolation layer may be the same as or different from that of the first middle dielectric isolation layer. The specific material of the second middle dielectric isolation layer may be set according to actual needs.

[0104] Illustratively, the dielectric constant of the material of the second middle dielectric isolation layer can be smaller than the dielectric constant of the material of the first middle dielectric isolation layer, so as to further reduce the parasitic capacitance between the gate stack structure included in the upper device and the gate stack structure included in the lower device in the three-dimensional stacked complementary transistor, thereby improving the operating performance of the semiconductor device.

[0105] Exemplarily, the material of the second middle dielectric isolation layer may include at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

[0106] Of course, when the material of the first sacrificial layer is different from that of the third sacrificial layer, after forming the first middle dielectric isolation layer, the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer not covered by the mask structure can be removed together.

[0107] In addition, after removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer not covered by the mask structure, before performing subsequent operations, the method for manufacturing the semiconductor device may further include the following steps: Fig.11 and Fig.13 As shown, along the length direction of the fin structure, wet etching or dry etching is used to remove the edge portions of both sides of each remaining first sacrificial layer 13 to form a second dielectric filling region 26. Next, as shown in FIG. Figures 14 to 16 As shown, deposition and etching processes can be used to form an inner sidewall 27 in the second dielectric filling region. The inner sidewall 27 can limit the length of the gate stack structure, which is beneficial to improving the working performance of the semiconductor device. The material of the inner sidewall 27 can include any insulating material such as silicon nitride, silicon oxynitride or silicon oxycarbide, as long as it can be applied to the manufacturing method provided in the embodiment of the present invention.

[0108] It should be noted that if Fig.12 and Fig.14 As shown, when the material of the first sacrificial layer 13 is the same as the material of the third sacrificial layer 16 , inner sidewalls 27 are also formed on both sides of the remaining third sacrificial layer 16 .

[0109] Next, if Fig.17 and Fig.18 As shown, epitaxial growth or other processes can be used to form a first source region 21 and a first drain region 22 on both sides of the remaining first sacrificial layer 13 and the channel layer 14 below the remaining first middle dielectric isolation layer 20. The materials of the first source region 21 and the first drain region 22 can be set according to actual needs and are not specifically limited here.

[0110] Next, if Fig.19 and Fig. 20As shown, deposition and etching processes may be used to form an insulating layer 23 on the first source region 21 and the first drain region 22. The thickness and material of the insulating layer 23 may be set according to actual requirements.

[0111] Next, if Fig.21 and Fig. 22 As shown, epitaxy or other processes can be used to form a second source region 24 and a second drain region 25 on the insulating layer 23 and on both sides of the remaining first sacrificial layer 13 and the channel layer 14 located above the remaining first middle dielectric isolation layer 20. The conductivity type of the second source region 24 and the second drain region 25 is opposite to the conductivity type of the first source region 21 and the first drain region 22. Among them, the materials of the second source region 24 and the second drain region 25 can be set according to actual needs and are not specifically limited here. The materials of the second source region 24 and the second drain region 25 can be the same as or different from the materials of the first source region 21 and the first drain region 22.

[0112] In addition, after forming the second source region and the second drain region, the method for manufacturing the semiconductor device may further include: Fig.23 and Fig.24 As shown, deposition and planarization processes can be used to form an interlayer dielectric layer 29 covering the semiconductor substrate 11 to protect the second source region 24 and the second drain region 25 from being affected by etching and cleaning operations in subsequent operations, thereby improving the yield of the semiconductor device. The top of the interlayer dielectric layer 29 is flush with the top of the mask structure 18. The material of the interlayer dielectric layer 29 can include any dielectric material such as silicon oxide or silicon nitride.

[0113] Next, if Fig.25 and Fig.26 As shown, the mask structure can be removed by dry etching or wet etching. Specifically, the structure exposed can be determined according to the previous operation steps.

[0114] For example: Fig. 9 As shown, if the second middle dielectric isolation layer is not formed, the structures exposed to the outside by removing the mask structure 18 include the remaining first sacrificial layer 13 and the remaining third sacrificial layer 16. In this case, Fig. 27 As shown, a dry etching or wet etching process can be used to remove the remaining first sacrificial layer 13 and the remaining third sacrificial layer 16. Next, as shown in FIG. Fig.31As shown, a gate stack structure 30 is formed at least around the periphery of the remaining channel layer 14 by using processes such as atomic layer deposition. At this time, if the number of layers of the second sacrificial layer 15 is at least two layers, the gate stack structure 30 also surrounds the periphery of the remaining first middle dielectric isolation layer 20. The gate stack structure 30 may include a gate dielectric layer, and a gate located on the gate dielectric layer. Among them, the material of the gate dielectric layer may be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as HfO2, ZrO2, TiO2 or Al2O3. The material of the gate may be a conductive material such as doped polysilicon, TiN, TaN or TiSiN. The thickness of the above-mentioned gate dielectric layer and gate can be set according to actual needs, and is not specifically limited here. In addition, the material and / or thickness of the gate stack structure 30 included in the three-dimensional stacked complementary transistor may be the same or different.

[0115] Alternatively, in this case (the second middle dielectric isolation layer is not formed), when the material of the first sacrificial layer is different from the material of the third sacrificial layer, after removing the mask structure and before removing the remaining first sacrificial layer, the method for manufacturing the semiconductor device may include: Fig.28 As shown in FIG. 1 , the third sacrificial layer is removed to form a third dielectric filling region 31. Next, as shown in FIG. Fig.29 As shown, a second middle dielectric isolation layer 32 is formed in the third dielectric filling region by using deposition and etching processes. Fig.32 As shown, the gate stack structure 30 only surrounds the periphery of the remaining channel layer 14 to reduce parasitic capacitance. In addition, another optional solution can be provided for reducing parasitic capacitance, thereby improving the applicability of the manufacturing method provided by the embodiment of the present invention in different application scenarios.

[0116] For example: Fig.10 and Fig.26 As shown in FIG. 1 , if the second middle dielectric isolation layer 32 is formed before forming the first source region 21 and the first drain region 22, the structures exposed to the outside by removing the mask structure 18 include the remaining first sacrificial layer 13 and the remaining second middle dielectric isolation layer 32. Meanwhile, after removing the mask structure 18, the method for manufacturing the semiconductor device may further include: Fig.30 As shown, a dry etching or wet etching process is used to remove the remaining first sacrificial layer. Fig.32 As shown, a gate stack structure 30 surrounding the remaining channel layer 14 is formed by using processes such as atomic layer deposition.

[0117] It is worth noting that Fig.10As shown, in the case where the materials of the first sacrificial layer 13 and the third sacrificial layer 16 are different, if the above-mentioned second middle dielectric isolation layer 32 is formed before forming the first source region and the first drain region, then in the process of source and drain etching, it is only necessary to etch the alternately stacked first sacrificial layer 13 and the channel layer 14, and to etch the alternately stacked first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32. Because the first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32 are both dielectric isolation layers, compared with the difficulty of etching the alternately stacked first middle dielectric isolation layer 20 and the third sacrificial layer 16, the difficulty of etching the alternately stacked first middle dielectric isolation layer 20 and the second middle dielectric isolation layer 32 is lower and easier to implement, which is conducive to reducing the manufacturing difficulty.

[0118] When the above technical solution is adopted, Figures 2 to 32As shown, in the manufacturing method provided by the embodiment of the present invention, the first sacrificial layer 13, the second sacrificial layer 15 and the third sacrificial layer 16 have different functions respectively. Specifically, the remaining channel layer 14 (the remaining channel layer 14 is used to form the channel region) will be released by selectively removing the portion of the first sacrificial layer 13 corresponding to the gate formation region, so as to form a gate stack structure 30 surrounding the periphery of the remaining channel layer 14. The first middle dielectric isolation layer 20 for isolating the gate stack structure 30 of the upper device included in the three-dimensional stacked complementary transistor from the gate stack structure 30 of the lower device will be formed by selectively etching the second sacrificial layer 15. As for the third sacrificial layer 16, the gate stack structure 30 may be formed at the position where the portion of the third sacrificial layer 16 corresponding to the gate formation region is located, and an insulating dielectric material for isolation may also be formed. Based on this, in the existing manufacturing method, the first sacrificial layer 13, the second sacrificial layer 15 and the third sacrificial layer 16 are completely restricted in the type of materials to achieve sufficient etching selectivity of the three. In the manufacturing method provided by the embodiment of the present invention, when the material of one of the second sacrificial layer 15 and the third sacrificial layer 16 includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium, the difference in germanium content between the second sacrificial layer 15 and the third sacrificial layer 16 is less than 15%. At this time, the material difference between the second sacrificial layer 15 and the third sacrificial layer 16 is small, and the corresponding lattice difference between the two is also small. When the material used for epitaxy to manufacture the second sacrificial layer 15 and the third sacrificial layer 16 is large, the problems of stress distribution and stress matching between thin films that need to be considered due to the large material difference between the second sacrificial layer 15 and the third sacrificial layer 16 in the prior art can be alleviated, and the limitation of the critical thickness of epitaxy is reduced. There is no need to form more layers of second sacrificial layers 15 and third sacrificial layers 16 with smaller layer thicknesses as in the prior manufacturing method, or there is no need to form a fixed number of second sacrificial layers 15 and third sacrificial layers 16 due to the critical thickness limitation, resulting in a smaller thickness of the insulating layer 23 used to isolate the first source region 21 and the first drain region 22, and the second source region 24 and the second drain region 25, thereby preventing leakage.

[0119] And, if Figures 2 to 32As shown, the second sacrificial layer 15 is doped with an etching aid. With this arrangement, the second sacrificial layer 15 can be selectively removed at least under the accelerated etching effect of the etching aid to form the first dielectric filling region 19 while retaining the third sacrificial layer 16, thereby improving the yield of the semiconductor device. In addition, the manufacturing method provided by the embodiment of the present invention is to form the first middle dielectric isolation layer 20 in advance before the source and drain etching. At this time, although the aspect ratio of the fin-shaped structure 12 may still be large, during the etching process of the insulating dielectric material used to manufacture the first middle dielectric isolation layer 20, even if the insulating dielectric material at the bottom of the gap between adjacent fin-shaped structures 12 is not completely removed, it will not affect the formation of the first source region 21 and the first drain region 22 of the subsequent lower-layer device, and will not affect the contact between the first source region 21 and the first drain region 22 of the lower-layer device and the first channel region respectively; and the insulating dielectric material remaining at the bottom of the gap between adjacent fin-shaped structures 12 can further isolate different semiconductor devices formed based on different fin-shaped structures 12, reduce the risk of leakage, and increase the yield of the manufactured semiconductor devices while also helping to improve the working performance of the manufactured semiconductor devices.

[0120] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0121] The embodiments of the present invention are described above. However, these embodiments are only for a clearer description and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, a person skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a fin structure on a semiconductor substrate; Along the thickness direction of the semiconductor substrate, the fin structure includes an alternately stacked first sacrificial layer and a channel layer, and an alternately stacked second sacrificial layer and a third sacrificial layer; the alternately stacked first sacrificial layer and the channel layer are located on both sides of the alternately stacked second sacrificial layer and the third sacrificial layer along the thickness direction; the film layers located at the bottom and top layers of the alternately stacked first sacrificial layer and the channel layer are both the first sacrificial layer; the film layers located at the bottom and top layers of the alternately stacked second sacrificial layer and the third sacrificial layer are both the second sacrificial layer; the material of one of the second sacrificial layer and the third sacrificial layer includes silicon or silicon germanium, and the material of the other includes silicon germanium or germanium; the difference in germanium content between the second sacrificial layer and the third sacrificial layer is less than 15%, and the second sacrificial layer is doped with an etching auxiliary agent; forming a mask structure spanning over the fin-shaped structure; At least under the accelerated etching action of the etching auxiliary agent, selectively remove the second sacrificial layer to form a first dielectric filling area; retaining the third sacrificial layer; forming a first middle dielectric isolation layer in the first dielectric filling region; removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer that are not covered by the mask structure; forming a first source region and a first drain region respectively on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer; forming an insulating layer on the first source region and the first drain region; A second source region and a second drain region are respectively formed on the insulating layer and on both sides of the remaining first sacrificial layer and the channel layer located above the remaining first middle dielectric isolation layer; the conductivity types of the second source region and the second drain region are opposite to the conductivity types of the first source region and the first drain region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The etching auxiliary agent is an N-type dopant; and / or, selectively removing the second sacrificial layer by a wet etching process or an isotropic dry etching process; And / or, the doping concentration of the etching auxiliary agent in the second sacrificial layer is greater than or equal to 1E18cm -3 , and less than or equal to 1E19cm -3 .

3. The method for manufacturing a semiconductor device according to claim 1, wherein when a wet etching process is used to selectively remove the second sacrificial layer, the wet etching solution comprises a mixed solution of hydrofluoric acid and hydrogen peroxide; Alternatively, when a dry etching process is used to selectively remove the second sacrificial layer, the etching gas includes a mixed gas of CF 4 , O 2 and He.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The thickness of the second sacrificial layer and / or the third sacrificial layer is greater than or equal to 10 nm and less than or equal to 30 nm; and / or, The etching auxiliary agent is doped into the second sacrificial layer by in-situ doping.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The second sacrificial layer and the third sacrificial layer are made of the same material; And / or, a material of the first sacrificial layer is the same as a material of the third sacrificial layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: After removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the third sacrificial layer that are not covered by the mask structure, and before respectively forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer located below the remaining first middle dielectric isolation layer, the method for manufacturing the semiconductor device further includes: Along the length direction of the fin-shaped structure, removing the edge portions on both sides of each remaining first sacrificial layer to form a second dielectric filling area; An inner sidewall is formed in the second dielectric filling region.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The mask structure includes a sacrificial gate; And or, while forming the first middle dielectric isolation layer in the dielectric filling region, a gate sidewall is formed at least on both sides of the mask structure along the length direction of the fin structure.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the first middle dielectric isolation layer includes at least one of SiN, SiCO and SiCON.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: After forming the second source region and the second drain region, the method for manufacturing the semiconductor device further includes: forming an interlayer dielectric layer covering the semiconductor substrate; removing the mask structure; removing the remaining first sacrificial layer, and removing the remaining third sacrificial layer; A gate stack structure is formed at least surrounding the remaining periphery of the channel layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: In the case where the material of the first sacrificial layer is different from the material of the third sacrificial layer, After removing the mask structure and before removing the remaining first sacrificial layer, the method for manufacturing the semiconductor device includes: removing the third sacrificial layer to form a third dielectric filling region; A second middle dielectric isolation layer is formed in the third dielectric filling region.

11. The method for manufacturing a semiconductor device according to claim 1, wherein: In the case where the material of the first sacrificial layer is different from the material of the third sacrificial layer, After forming the first middle dielectric isolation layer in the first dielectric filling region, and before forming the first source region and the first drain region on both sides of the remaining first sacrificial layer and the channel layer below the remaining first middle dielectric isolation layer, the method for manufacturing the semiconductor device comprises: selectively removing the third sacrificial layer to form a third dielectric filling region; and forming a second middle dielectric isolation layer in the third dielectric filling region; removing the first sacrificial layer, the channel layer, the first middle dielectric isolation layer and the second middle dielectric isolation layer that are not covered by the mask structure; After forming the second source region and the second drain region, the manufacturing method of the semiconductor device also includes: forming an interlayer dielectric layer covering the semiconductor substrate; removing the mask structure; removing the remaining first sacrificial layer; and forming a gate stack structure surrounding the remaining periphery of the channel layer.

12. The method for manufacturing a semiconductor device according to claim 10 or 11, characterized in that: The material of the second middle dielectric isolation layer is the same as the material of the first middle dielectric isolation layer; or the dielectric constant of the material of the second middle dielectric isolation layer is smaller than the dielectric constant of the material of the first middle dielectric isolation layer; And / or, the material of the first middle dielectric isolation layer includes: at least one of SiO2, SiN, SiCO, SiCON and SiO2-SiF4.

Images