Transistor with top gate structure, preparation method thereof and electronic equipment

Abstract

The invention relates to the field of electronic devices, in particular to a transistor with a top gate structure, a preparation method of the transistor and electronic equipment. The preparation method comprises the following steps: providing a substrate with a two-dimensional material layer on the surface; forming a patterned source electrode and a patterned drain electrode on the two-dimensional material layer; sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in an area between the source electrode and the drain electrode; the buffer layer is removed, so that the two-dimensional material layer and the seed layer are in unstressed and nondestructive contact; and sequentially forming a dielectric layer and a top gate on the seed layer to obtain the transistor with the top gate structure. According to the method, stress-free and damage-free integration of the two-dimensional material and the high-dielectric-constant dielectric medium is achieved, the two-dimensional material-dielectric medium interface state density is reduced, and good grid control performance is guaranteed.

Description

Technical Field

[0001] The present invention relates to the field of electronic devices, and in particular to a transistor with a top gate structure, a preparation method thereof, and an electronic device. Background Art

[0002] The integration of high-k dielectrics and two-dimensional materials is an important step in constructing top-gate structures in electronic devices such as two-dimensional material transistors. On the one hand, since there are no dangling bonds on the surface of two-dimensional materials, it is difficult to achieve uniform high-k dielectric deposition through traditional atomic layer deposition (ALD) technology. On the other hand, two-dimensional materials are only atomically thick, and it is necessary to minimize the stress and damage of the dielectric integration process to the two-dimensional materials, thereby reducing the interface state density between the two-dimensional material and the dielectric and achieving good gate control performance.

[0003] The existing integration processes of high-k dielectrics and two-dimensional materials are as follows: (1) Pre-deposit a 1nm thick Al, Ta or other metal as a seed layer, then oxidize it, and then deposit Al by atomic layer deposition technology. 2 O 3 , HfO 2 High Current Density in Monolayer MoS 2 Doped byAlO x .ACS nano, 2021, 15(1): 1587-1596.DOI: 10.1021 / acsnano.0c09078). This method may introduce stress and damage to the two-dimensional material when depositing metal seed layers such as Al and Ta, and introduce more interface states at the interface between the two-dimensional material and the dielectric, making it difficult to achieve good gate control performance. (2) By pre-depositing Sb with a thickness of about 1 nm, 2 O 3 , PTCA and other molecules as seed layers, and then Al is deposited by atomic layer deposition technology 2 O 3 , HfO 2 High dielectric constant top gate dielectrics (Scalable integration of hybrid high-κdielectric materials on two-dimensional semiconductors. Nature Materials, 2023, 22(9): 1078-1084. DOI: 10.1038 / s41563-023-01626-w). This method is due to Sb 2 O 3The volatilization temperature of molecules such as PTCA is low, so there are problems with thermal stability. In addition, the dielectric constant of these molecules is not high, which will reduce the equivalent oxide thickness (EOT) of the transistor. (3) By mechanical transfer, Al 2 O 3 , HfO 2 The splanchnic mesenchyme is the tissue of origin for pancreatic fibroblasts during homeostasis and tumorigenesis. Nature Communications, 2023, 14(1): 2340. DOI: 10.1038 / s41467-022-34464-6); or by mechanical transfer, HfS 2 、TaS 2 The two-dimensional Hf-based and Ta-based materials are transferred to the two-dimensional material and converted into HfO by further oxidation. 2 、 2 O 3 High dielectric constant dielectrics (Oxidation of tantalum disulfide (TaS 2 )films for gate dielectric and process design of two-dimensional field-effect device. Nanotechnology, 2022, 33(37): 375204. DOI: 10.1088 / 1361-6528 / ac75f9). This method requires the integration of high dielectric constant dielectrics and two-dimensional materials through mechanical transfer, which has problems in terms of device uniformity.

[0004] In summary, there are many problems in the integration of high dielectric constant dielectrics and two-dimensional materials in existing electronic devices such as two-dimensional material transistors, which need to be improved and developed. Summary of the invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a transistor with a top gate structure, a preparation method thereof, and an electronic device, aiming to solve the problem that the existing method introduces stress and damage to the two-dimensional material when depositing the metal seed layer.

[0006] Specifically, the technical solution of the present invention is as follows:

[0007] A first aspect of the present invention provides a method for preparing a transistor having a top gate structure, comprising the steps of:

[0008] Providing a substrate having a two-dimensional material layer on its surface;

[0009] forming a patterned source electrode and a drain electrode on the two-dimensional material layer;

[0010] forming a buffer layer and a seed layer in sequence on the two-dimensional material layer in the region between the source electrode and the drain electrode;

[0011] removing the buffer layer so that the two-dimensional material layer is in stress-free and damage-free contact with the seed layer;

[0012] A dielectric layer and a top gate are sequentially formed on the seed layer to obtain the transistor with a top gate structure.

[0013] A second aspect of the present invention provides a transistor with a top gate structure manufactured by the manufacturing method of the present invention.

[0014] A third aspect of the present invention provides an electronic device, comprising the transistor with a top-gate structure as described in the present invention.

[0015] Beneficial effects: First, the method of the present invention can reduce the stress and damage to the two-dimensional material during the deposition of the seed layer by introducing a buffer layer. After removing the buffer layer, stress-free and damage-free contact can be achieved between the two-dimensional material layer and the seed layer. The dielectric layer is subsequently deposited to achieve stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric, reduce the interface state density of the two-dimensional material-dielectric, and ensure the gate control performance of the device. Second, the method of the present invention can achieve stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric without mechanical transfer, avoiding bubbles and impurity pollution during the mechanical transfer process, and achieving large-scale uniformity; and there is no need to introduce Sb with low evaporation temperature and low dielectric constant. 2 O 3 , PTCA and other seed layers, thus having high thermal stability and not reducing the dielectric constant of the top gate structure, further ensuring the gate control performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The present invention is a schematic flow chart of a method for preparing a transistor with a top-gate structure.

[0017] Figure 2 A schematic diagram of the process flow of preparing a transistor with a top-gate structure provided by the present invention.

[0018] Figure 3 Schematic diagram of the preparation of the bottom electrode (source and drain) in Example 1.

[0019] Figure 4 Schematic diagram of the preparation of the buffer layer and the seed layer in Example 1.

[0020] Figure 5 Schematic diagram of the preparation of the top gate in Example 1.

[0021] Figure 6 The initial state of device A and the MoS 2 Transistor, initial state of device B and MoS in comparative example 1 2 Transfer characteristic curve of a transistor.

[0022] Figure 7 The MoS prepared in Example 1 and Comparative Example 1 2 MoS in transistors 2 Raman spectrum. DETAILED DESCRIPTION

[0023] The present invention provides a transistor with a top gate structure, a method for manufacturing the same, and an electronic device. To make the purpose, technical solution, and effects of the present invention clearer and more specific, the present invention is further described in detail below. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0024] The basic idea of ​​the present invention is: (1) first deposit a buffer layer on the surface of the two-dimensional material layer. The material of the buffer layer has a low melting point and vaporization temperature, so it will not damage the two-dimensional material during the deposition process and can be removed by a simple annealing process later; (2) deposit a metal seed layer on the buffer layer. The presence of the buffer layer avoids the stress and damage to the surface of the two-dimensional material during the deposition process of the metal seed layer; (3) remove the buffer layer by annealing at a relatively low temperature to achieve stress-free and damage-free contact between the two-dimensional material layer and the seed layer. (4) deposit a high dielectric constant dielectric material by ALD (atomic layer deposition) and other technologies to form a dielectric layer, thereby achieving stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric.

[0025] According to one embodiment of the present invention, a method for preparing a transistor with a top gate structure is provided, comprising the steps of:

[0026] S1. providing a substrate having a two-dimensional material layer on its surface;

[0027] S2, forming a patterned source and drain on the two-dimensional material layer;

[0028] S3, sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source electrode and the drain electrode;

[0029] S4, removing the buffer layer, so that the two-dimensional material layer and the seed layer are in stress-free and damage-free contact;

[0030] S5. Forming a dielectric layer and a top gate in sequence on the seed layer to obtain the transistor with a top gate structure.

[0031] In the embodiment of the present invention, a buffer layer is first deposited on the surface of the two-dimensional material layer, and then a metal seed layer is deposited on the buffer layer. The presence of the buffer layer avoids stress and damage to the surface of the two-dimensional material during the deposition process of the metal seed layer. In addition, the material of the buffer layer has a low melting point and vaporization temperature, so it will not damage the two-dimensional material during the deposition process, and can be subsequently removed by an annealing process at a lower temperature to achieve stress-free and damage-free contact between the two-dimensional material and the seed layer. The subsequent deposition of a high dielectric constant dielectric achieves stress-free and damage-free integration of the two-dimensional material and the high dielectric constant dielectric, reduces the interface state density of the two-dimensional material-dielectric, and ensures the gate control performance of the device.

[0032] The material of the seed layer selected in the embodiment of the present invention is aluminum oxide material (Al 2 O 3 ), Tantalum Oxide Materials (Ta 2 O 5 ), hafnium oxide materials (HfO 2 ), magnesium oxide material (MgO) or yttrium oxide material (Y 2 O 3 ), avoiding the use of Sb with low evaporation temperature and low dielectric constant 2 O 3 , PTCA and other materials, thus having high thermal stability, and will not reduce the dielectric constant of the top gate, further ensuring the gate control performance of the device. The selection principle of the seed layer material in the embodiment of the present invention is to use an insulating material with a large band gap, a high dielectric constant, and high thermal stability. These characteristics help to achieve better transistor gate control performance and better thermal stability.

[0033] In step S1, in one embodiment, the material of the two-dimensional material layer can be selected from two-dimensional materials commonly used in the prior art, preferably MoS 2 ,WSe 2 , WS 2 and other two-dimensional materials, but not limited thereto.

[0034] In the present invention, the two-dimensional material layer can be obtained by transferring to a substrate or growing directly on the surface of a substrate. The transfer or direct growth of two-dimensional materials is a conventional technique in the art and is not limited here. For example, the transfer of two-dimensional materials can be carried out by mechanical exfoliation, exfoliating and transferring the two-dimensional material (MoS 2 ,WSe 2 , WS2 ) layer on a substrate; or using a mechanical transfer method, transferring a single layer of two-dimensional material grown by chemical vapor deposition (CVD) on a substrate.

[0035] In step S2, in one embodiment, the step of forming a patterned source and drain on the two-dimensional material layer specifically includes:

[0036] S11, coating a photoresist on the two-dimensional material layer, and patterning the two-dimensional material layer using a photolithography process;

[0037] S12, evaporating electrode materials, removing the photoresist, and forming patterned source and drain electrodes.

[0038] In the present invention, photoresist and photolithography can be used to make photolithography patterns at specific locations of a substrate having a two-dimensional material layer according to specific needs. The specific shape of the photolithography pattern can be set according to actual needs, and the specific shape is not limited here. After the electrode material is evaporated, the photoresist on the two-dimensional material layer needs to be removed to form a predetermined patterned source and drain. Patterning the two-dimensional material layer using photoresist and photolithography, and the subsequent removal of the photoresist are both conventional techniques in the art and are not limited here.

[0039] In step S11, in one embodiment, photoresist is applied on the two-dimensional material layer by spin coating, and then the substrate is pre-baked, and a preset electrode pattern is exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate is obtained after development.

[0040] In step S12, in one implementation, the electrode material may be a metal material used to form a source electrode and a drain electrode, and in the present invention, Bi material and Au material are used.

[0041] In one embodiment, the photoresist may be removed by soaking in acetone to obtain a substrate having patterned source and drain electrodes.

[0042] In step S3, in one embodiment, the material of the buffer layer is selenium material or tellurium material. Selenium material or tellurium material has a low melting point and vaporization temperature, and will not generate stress and damage on the two-dimensional material during the deposition process, and can also be removed by annealing process at a lower temperature later.

[0043] In one embodiment, the material of the seed layer is aluminum oxide material, tantalum oxide material, hafnium oxide material, magnesium oxide material or yttrium oxide material. Preferably, the material of the seed layer is aluminum oxide material or tantalum oxide material.

[0044] In one embodiment, the step of sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source and the drain specifically includes:

[0045] Applying photoresist on the two-dimensional material layer, the source electrode and the drain electrode, and patterning the two-dimensional material layer using a photolithography process;

[0046] The buffer layer and the seed layer are sequentially evaporated, and the photoresist is removed, so that the buffer layer and the seed layer are sequentially formed on the two-dimensional material layer in the area between the source and the drain.

[0047] In this embodiment, the two-dimensional material layer is also patterned by using photoresist and photolithography process, and then the buffer layer and the seed layer are evaporated in sequence, and then the photoresist is removed, that is, the buffer layer and the seed layer are formed in sequence on the two-dimensional material layer in the area between the source and the drain (the buffer layer and the seed layer are not formed on the source and the drain).

[0048] In step S4, in one embodiment, the buffer layer is removed by an annealing process.

[0049] In one embodiment, the annealing process may be a vacuum annealing process or an atmosphere annealing process. Specifically, the annealing process may be selected according to the buffer layer material, and the corresponding annealing temperature may be adjusted according to the melting point of the buffer layer material, which is generally slightly lower than the melting point of the buffer layer material, and the annealing time may be determined according to the thickness of the buffer layer.

[0050] In a preferred embodiment, when a vacuum annealing process is used, the vacuum degree used is less than or equal to 1×10 -1 Pa, the annealing time is 0.5h-24h; for example, the annealing time can be 0.5h, 1h, 2h, 3h, 4h, 5h, 6h, 7h, 8h, 9h, 10h, 15h, 20h, 24h, etc.

[0051] In a preferred embodiment, when an atmosphere annealing process is adopted, the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 50° C.-1000° C., and the annealing time is 0.5 h-24 h.

[0052] In a more preferred embodiment, when an atmosphere annealing process is adopted, the gas used is a mixed gas of argon and hydrogen, the annealing temperature is 50°C-500°C, and the annealing time is 0.5h-12h. The ratio of argon to hydrogen can be 95:5, the annealing temperature can be 50°C, 100°C, 150°C, 200°C, 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, etc., and the annealing time can be 0.5h, 1h, 2h, 3h, 4h, 5h, 6h, 7h, 8h, 9h, 10h, 11h, 12h, etc.

[0053] In an embodiment of the present invention, the buffer layer is removed by an annealing process, so that stress-free and damage-free contact is achieved between the two-dimensional material layer and the seed layer, thereby avoiding the problem of damage and stress to the surface of the two-dimensional material when the seed layer is directly deposited on the two-dimensional material.

[0054] In one embodiment, the thickness of the buffer layer is 5 nm-100 nm, for example, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc. Within this thickness range, the buffer layer material can be well removed in a subsequent annealing process without affecting the electrical properties of the two-dimensional material.

[0055] In one embodiment, the seed layer has a thickness of 0.2 nm to 5 nm, for example, 0.2 nm, 0.5 nm, 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc. Within this thickness range, the seed layer can be rapidly oxidized in an air environment without additional steps, and the dielectric constant of the seed layer and the dielectric layer as a whole can be maintained at a relatively high level without affecting the voltage regulation capability of the gate.

[0056] In step S5, in one embodiment, the material of the dielectric layer is selected to have a high dielectric constant, such as HfO 2 、Al 2 O 3 、 2 O 5 etc., but not limited to these.

[0057] In one embodiment, the thickness of the dielectric layer is 1 nm-50 nm, for example, 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0058] In one embodiment, sequentially forming a dielectric layer and a top gate on the seed layer are both conventional techniques in the art and are not limited here.

[0059] In a preferred embodiment, the material of the two-dimensional material layer in the transistor with a top gate structure is MoS 2 , the material of the buffer layer is Se, and the material of the seed layer is Al 2 O 3 , the material of the dielectric layer is HfO 2The transistors made from these materials have no serious doping effect, the electrical properties before and after the deposition of the dielectric layer are well maintained, and have a smaller subthreshold swing.

[0060] In the present invention, each layer of the transistor with a top gate structure can be prepared by using a technique including magnetron sputtering, thermal evaporation, electron beam evaporation or vacuum arc evaporation. The relevant coating techniques are conventional techniques in the art and are not limited here.

[0061] According to one embodiment of the present invention, there is provided a transistor with a top gate structure manufactured by the manufacturing method of the present invention.

[0062] According to one embodiment of the present invention, there is provided an electronic device, comprising the transistor with a top-gate structure as described in the present invention.

[0063] Combination Figure 1 and Figure 2 As shown, a method for preparing a transistor with a top gate structure provided by the present invention includes:

[0064] A substrate having a two-dimensional material layer 1 on its surface is provided, and patterned metal electrodes are formed as source 2 and drain 3 by electron beam evaporation, photolithography, etc., and then a layer of buffer layer material is deposited on the two-dimensional material channel (in the area between the source 2 and the drain 3) to form a buffer layer 4. Then, a seed layer 5 is deposited on the buffer layer 4, and then the buffer layer 4 is removed by vacuum annealing or atmosphere annealing, and a high dielectric constant dielectric is deposited by atomic layer deposition technology to form a dielectric layer 6, and finally a patterned metal electrode is deposited as a top gate 7, so as to obtain a transistor with a top gate structure of the present invention.

[0065] The present invention will be further described below by means of specific examples.

[0066] Example 1

[0067] This embodiment provides a MoS with a top gate structure. 2 The preparation method of the transistor is as follows:

[0068] Step 1: Substrate cleaning: Use acetone, isopropanol and deionized water to clean SiO 2 / Si(300nm SiO 2 ) The substrate was ultrasonically cleaned for 7 min, dried with a nitrogen gun, and then cleaned with Ar plasma.

[0069] Step 2: 2D material transfer: Use mechanical exfoliation to exfoliate and transfer MoS 2 The two-dimensional material layer 11 is on the substrate;

[0070] Step 3: Preparation of bottom electrode (source and drain): 2 On the substrate of the two-dimensional material layer 11, a photoresist 12 with a thickness of 1 μm is coated by spin coating, the substrate is pre-baked, and a preset electrode pattern is exposed on the substrate by a laser direct writing photolithography machine. After development, a patterned MoS 2 The substrate of the two-dimensional material layer is deposited by electron beam evaporation in less than 10 -4 Pa vacuum degree, The electrode materials Bi and Au were evaporated at a rate of 40 nm and 20 nm respectively. Then, the photoresist was removed by immersing in acetone. 2 A patterned source electrode 13 and a drain electrode 14 are formed on the substrate. Figure 3 It is a schematic diagram of the preparation of the bottom electrode (source and drain).

[0071] Step 4, preparation of buffer layer and seed layer: On the substrate that has undergone the above steps, two photolithography processes are performed, and a photoresist 21 with a thickness of 1 μm is applied by spin coating, and the substrate is pre-baked. A preset electrode pattern is exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate with a two-dimensional material layer is obtained after development. On the above substrate, a photoresist 22 with a thickness of 1 μm is applied by spin coating, and the substrate is pre-baked to evaporate the solvent in the photoresist, and the film is dried and fixed. A preset pattern is exposed on the substrate by a laser direct writing lithography machine, and a patterned substrate is obtained after development. Then an electron beam evaporation coating machine is used to coat the substrate in a temperature less than 10 -4 Pa vacuum degree, The buffer layer material selenium (Se) is evaporated at a rate of 5 nm to form a buffer layer 23. -4 Pa vacuum degree, The Al material is evaporated at a rate of 1 nm to a thickness of 1 nm. Then, it is naturally oxidized in air to generate aluminum oxide to form a seed layer 24. Then, it is placed in acetone to remove the photoresist, forming a channel pattern with a buffer layer 23 and a seed layer 24. Figure 4 Schematic diagram of the preparation of buffer layer and seed layer.

[0072] Step 5: Annealing to remove the buffer layer: Place the substrate obtained through the above steps in an annealing furnace, and introduce argon-hydrogen mixed gas (Ar:H 2 =95:5), the annealing temperature is 150°C, the annealing time is 3h, and the buffer layer 23 is removed, so that there is stress-free and damage-free contact between the two-dimensional material layer 11 and the seed layer 24.

[0073] Step 6: HfO 2Deposition of high-k dielectric layers: HfO deposited by atomic layer deposition 2 The high dielectric constant dielectric layer 25 uses TEMAH (tetrakis(methylethylamino)hafnium) as the Hf precursor, the source bottle temperature is 120°C, reacts with water, the chamber temperature is 140°C, and 100 cycles are performed to obtain 10nm HfO 2 A high dielectric constant dielectric layer 25 .

[0074] Step 7: Preparation of top gate ( Figure 5 Schematic diagram of the preparation of the top gate): On the substrate obtained through the above steps, a photoresist 31 with a thickness of 1 μm is applied by spin coating, the substrate is pre-baked, and a preset electrode pattern is exposed on the substrate by a laser direct writing photolithography machine, and a patterned substrate is obtained after development. An electron beam evaporation coating machine is used to coat the substrate in a temperature less than 10 -4 Pa vacuum degree, The electrode material Bi material and Au material are evaporated at a rate of 40 nm and 20 nm respectively to form a top gate 32. Then, the top gate 32 is formed by immersing the electrode material in acetone to remove the photoresist. 2 transistor.

[0075] Comparative Example 1

[0076] The preparation method is the same as that in Example 1, except that in step 4, a buffer layer is not deposited but a seed layer is directly deposited on the two-dimensional material layer, and finally a comparative MoS with a top-gate structure is prepared. 2 transistor.

[0077] The device including the source and the drain prepared by steps 1 to 3 in Example 1 is defined as device A. The transfer characteristic curve of the initial state of device A is tested. Subsequently, a MoS with a top-gate structure is prepared on device A by first depositing a buffer layer and then depositing a seed layer in Example 1. 2 Transistor, Test Example 1 MoS 2 Similarly, the device including the source and drain prepared by steps 1 to 3 in Comparative Example 1 is defined as device B, and the transfer characteristic curve of device B in the initial state is tested. Subsequently, a comparative MoS transistor with a top gate structure is prepared on device B by directly depositing a seed layer on the two-dimensional material layer without depositing a buffer layer in Comparative Example 1. 2 Transistor, test MoS in Comparative Example 1 2 Transfer characteristic curve of a transistor.

[0078] Figure 6 is the initial state of device A, MoS in Example 1 2 Transistor, initial state of device B and MoS in comparative example 12 The transfer characteristic curve of the transistor is based on Figure 6 It can be seen that the initial state of device A and device B has a similar threshold voltage of about -40V. 2 The threshold voltage of the transistor has shifted seriously to the left, and the leakage current has increased by an order of magnitude (from 10 -12 The magnitude becomes 10 -11 The buffer layer is deposited first and then the seed layer is deposited. 2 The transistor has no obvious performance degradation, and the leakage current remains at 10 before and after the process. -12 Order of magnitude.

[0079] Figure 7 The MoS prepared in Example 1 and Comparative Example 1 2 MoS in transistors 2 According to the Raman spectrum Figure 7 It can be seen that in Comparative Example 1, the seed layer is deposited directly on the two-dimensional material layer, which is better than MoS 2 Initial state, MoS 2 Characteristic peak A 1g The half-peak width of the peak increases, which indicates that the lattice structure of the surface of the two-dimensional material is destroyed and the two-dimensional semiconductor material in the channel is n-doped. In Example 1, by first depositing a buffer layer and then depositing a seed layer on the buffer layer, MoS 2 The characteristic peaks remain consistent before and after the process, indicating that the performance of the two-dimensional material remains unchanged.

[0080] Example 2

[0081] The preparation method is the same as that of Example 1, except that HfO 2 The deposition of high dielectric constant dielectric layer is adjusted to Al 2 O 3 Deposition of high dielectric constant dielectric layer, specifically: deposition of Al by atomic layer deposition technology 2 O 3 High dielectric constant dielectric layer, using TMA (trimethylaluminum) as Al precursor, reacting with water, chamber temperature 120 ° C, 100 cycles, to obtain 10nm Al 2 O 3 High dielectric constant dielectric layer. Finally, a MoS with top gate structure is prepared. 2 transistor.

[0082] Example 3

[0083] The preparation method is the same as that of Example 1, except that the evaporation of the Al material in the seed layer in step 4 is adjusted to the evaporation of the Ta material, specifically: -4 Pa vacuum degree, The Ta material is evaporated at a rate of 1 nm. Then it is naturally oxidized in the air to generate tantalum oxide to form a seed layer. Finally, a MoS with a top gate structure is prepared. 2 transistor.

[0084] Example 4

[0085] The preparation method is the same as that in Example 1, except that the method of transferring the two-dimensional material in step 1 is adjusted to a mechanical transfer method, specifically: using the mechanical transfer method, a single layer of MoS grown by chemical vapor deposition (CVD) is transferred 2 The two-dimensional material layer is on the substrate. Finally, a MoS with a top gate structure is prepared. 2 transistor.

[0086] Example 5

[0087] The preparation method is the same as that of Example 1, except that the evaporation thickness of the Se material in the buffer layer in step 4 is adjusted to 20 nm, and the annealing time in step 5 is adjusted to 8 h. The specific adjustment steps are: -4 Pa vacuum degree, Se material was evaporated at a rate of 100 nm to a thickness of 20 nm. Then, a seed layer was prepared according to the method in Example 1, and then the substrate was placed in an annealing furnace, and an argon-hydrogen mixed gas (Ar:H2O) was introduced at a gas flow rate of 100 standard cubic centimeters per minute (sccm). 2 =95:5), the annealing temperature is 150°C, the annealing time is 8h, and the buffer layer is removed to make the two-dimensional material layer and the seed layer contact without stress and damage. Finally, a MoS with a top gate structure is prepared. 2 transistor.

[0088] It should be understood that the application of the present invention is not limited to the above examples. For ordinary technicians in this field, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A method for preparing a transistor having a top gate structure, characterized in that: Includes steps: Providing a substrate having a two-dimensional material layer on its surface; forming a patterned source electrode and a drain electrode on the two-dimensional material layer; forming a buffer layer and a seed layer in sequence on the two-dimensional material layer in the region between the source electrode and the drain electrode; removing the buffer layer so that the two-dimensional material layer is in stress-free and damage-free contact with the seed layer; A dielectric layer and a top gate are sequentially formed on the seed layer to obtain the transistor with a top gate structure.

2. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The material of the buffer layer is selenium material or tellurium material, and the material of the seed layer is aluminum oxide material, tantalum oxide material, hafnium oxide material, magnesium oxide material or yttrium oxide material.

3. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The thickness of the buffer layer is 5nm-100nm, the thickness of the seed layer is 0.2nm-5nm, and the thickness of the dielectric layer is 1nm-50nm.

4. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The dielectric layer is made of hafnium oxide, aluminum oxide or tantalum oxide.

5. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The buffer layer is removed by an annealing process.

6. The method for preparing a transistor with a top gate structure according to claim 5, characterized in that: The annealing process is a vacuum annealing process or an atmosphere annealing process; when the vacuum annealing process is adopted, the vacuum degree used is less than or equal to 1×10 -1 Pa, the annealing time is 0.5h-24h; when the atmosphere annealing process is adopted, the gas used is one or more of hydrogen, argon and nitrogen, the annealing temperature is 50℃-1000℃, and the annealing time is 0.5h-24h.

7. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The step of forming a patterned source electrode and a drain electrode on the two-dimensional material layer specifically includes: Applying photoresist on the two-dimensional material layer, and patterning the two-dimensional material layer using a photolithography process; The electrode material is evaporated, the photoresist is removed, and patterned source and drain electrodes are formed.

8. The method for preparing a transistor with a top gate structure according to claim 1, characterized in that: The step of sequentially forming a buffer layer and a seed layer on the two-dimensional material layer in the region between the source and the drain specifically includes: Applying photoresist on the two-dimensional material layer, the source electrode and the drain electrode, and patterning the two-dimensional material layer using a photolithography process; A buffer layer and a seed layer are sequentially evaporated, and the photoresist is removed, and a buffer layer and a seed layer are sequentially formed on the two-dimensional material layer in the region between the source electrode and the drain electrode.

9. A transistor with a top gate structure prepared by the preparation method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises the transistor with a top gate structure as claimed in claim 9.

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