Phase shifter circuit, electronic chip and phase shift regulation and control method

Abstract

The invention provides a phase shifter circuit, an electronic chip and a phase shift regulation and control method, and the phase shifter circuit comprises a coupler unit which converts a received input differential signal into an I-path differential signal and a Q-path differential signal which are orthogonal; the I-path gain amplification unit is used for adjusting the gain of the received I-path differential signal to obtain an I-path adjusting signal; the Q-path gain amplification unit is used for adjusting the gain of the received Q-path differential signal to obtain a Q-path adjustment signal; the synthesis unit is used for synthesizing the received I-path adjusting signal and the Q-path adjusting signal to obtain an output differential signal; the I-path switched capacitor array is used for changing the phase of the I-path differential signal by controlling and adjusting the capacitance accessed to the input end of the I-path gain amplification unit through a switch; and the Q-path switched capacitor array is used for changing the phase of the Q-path differential signal by controlling and adjusting the capacitance accessed to the input end of the Q-path gain amplification unit through a switch. According to the invention, the problem that the existing phase shifter cannot realize high precision is solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to a phase shifter circuit, an electronic chip and a phase shift control method. Background Art

[0002] With the continuous evolution of millimeter-wave frequency band radars, a multiple-input multiple-output (MIMO) architecture is often used to improve the performance of millimeter-wave radars. This places high demands on the performance of millimeter-wave phased arrays, especially the accuracy of phase shifters. How to achieve high-precision phase shifting on-chip is a major challenge in millimeter-wave radar design.

[0003] Traditional phase shifters are implemented based on couplers and variable gain amplifiers. The higher the phase shifting accuracy, the more difficult it is to implement, and even complex calibration assistance is required. Therefore, how to provide an easy-to-implement high-precision phase shifter is a technical problem that technical personnel in this field are eager to solve.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a phase shifter circuit, an electronic chip and a phase shift control method, so as to solve the problem that the existing phase shifter cannot achieve high precision.

[0006] To achieve the above objectives and other related objectives, the present invention provides a phase shifter circuit, the phase shifter circuit comprising: A coupler unit receives an input differential signal and converts the input differential signal into an orthogonal I-channel differential signal and a Q-channel differential signal; An I-channel gain amplification unit receives the I-channel differential signal and adjusts the gain of the I-channel differential signal to obtain an I-channel adjustment signal; A Q-path gain amplifying unit receives the Q-path differential signal and adjusts the gain of the Q-path differential signal to obtain a Q-path adjustment signal; A synthesis unit receives the I-path adjustment signal and the Q-path adjustment signal, and synthesizes the I-path adjustment signal and the Q-path adjustment signal to obtain an output differential signal; An I-channel switch capacitor array, which adjusts the size of the capacitor connected to the input end of the I-channel gain amplifier unit by switch control to change the phase of the I-channel differential signal input to the I-channel gain amplifier unit; The Q-path switch capacitor array adjusts the size of the capacitor connected to the input end of the Q-path gain amplifier unit through switch control to change the phase of the Q-path differential signal input to the Q-path gain amplifier unit.

[0007] Optionally, the I-channel gain amplification unit includes an I-channel input matching network and an I-channel variable gain amplifier, wherein the I-channel input matching network is used to match the input impedance of the I-channel variable gain amplifier, and the I-channel variable gain amplifier is used to adjust the gain of the I-channel differential signal to obtain the I-channel adjustment signal; The Q-path gain amplification unit includes a Q-path input matching network and a Q-path variable gain amplifier, wherein the Q-path input matching network is used to match the input impedance of the Q-path variable gain amplifier, and the Q-path variable gain amplifier is used to adjust the gain of the Q-path differential signal to obtain the Q-path adjustment signal.

[0008] Optionally, the I-path input matching network and the Q-path input matching network are both implemented using transformers.

[0009] Optionally, the I-channel variable gain amplifier and the Q-channel variable gain amplifier each include a first MOS tube part, a second MOS tube part, a third MOS tube part and a fourth MOS tube part, the first MOS tube part input end and the second MOS tube part input end are connected in parallel as the positive input end of the corresponding variable gain amplifier, the third MOS tube part input end and the fourth MOS tube part input end are connected in parallel as the negative input end of the corresponding variable gain amplifier, the first MOS tube part output end and the third MOS tube part output end are connected in parallel as the positive output end of the corresponding variable gain amplifier, and the second MOS tube part input end and the fourth MOS tube part input end are connected in parallel as the positive output end of the corresponding variable gain amplifier. The output end of the MOS tube section is connected in parallel with the output end of the fourth MOS tube section as the negative output end of the corresponding variable gain amplifier; wherein each MOS tube section includes M MOS tubes, M first capacitors and M resistors, the gate of each MOS tube is respectively connected to the first end of each first capacitor and the first end of each resistor, the source of each MOS tube is connected to the reference ground, the drain of each MOS tube is connected in parallel as the output end of the corresponding MOS tube section, the second end of each first capacitor is connected in parallel as the input end of the corresponding MOS tube section, the second end of each resistor receives each control signal, and M is a natural number greater than or equal to 2.

[0010] Optionally, the I-path switch capacitor array includes a positive I-path switch capacitor unit and a negative I-path switch capacitor unit, and the Q-path switch capacitor array includes a positive Q-path switch capacitor unit and a negative Q-path switch capacitor unit, and each switch capacitor unit adjusts the capacitance of the corresponding input end connected to the corresponding gain amplifier unit through switch control; wherein each switch capacitor unit includes N second capacitors and N switches, and the N second capacitors and the N switches are respectively connected in series and then connected in parallel to the corresponding input end of the corresponding gain amplifier unit, and N is a natural number greater than or equal to 1.

[0011] Optionally, the phase shifter circuit further includes: A single-ended-to-differential converter receives an input single-ended signal and converts the input single-ended signal into the input differential signal; And / or, a differential-to-single-ended converter receives the output differential signal and converts the output differential signal into an output single-ended signal.

[0012] The present invention further provides an electronic chip, comprising: a phase shifter circuit as described in any one of the above items.

[0013] Optionally, the electronic chip is a millimeter wave chip.

[0014] The present invention further provides a phase shift control method of the phase shifter circuit as described in any one of the above items, and the phase shift control method comprises: Step S1, performing switch control on the I-path switch capacitor array and the Q-path switch capacitor array, and connecting J capacitors to two input ends of the I-path gain amplifier unit and two input ends of the Q-path gain amplifier unit respectively; Step S2, obtaining a phase shift θi=2i*θ0 by adjusting the gain of the I-path gain amplifier unit and the gain of the Q-path gain amplifier unit; Step S3, keeping the gain of the I-path gain amplifier unit and the gain of the Q-path gain amplifier unit unchanged, switching and regulating the I-path switch capacitor array and the Q-path switch capacitor array, respectively connecting K capacitors to the two input ends of the I-path gain amplifier unit and the two input ends of the Q-path gain amplifier unit, so as to obtain a phase shift phase θi=(2i+1)*θ0; Wherein, J is a natural number greater than or equal to 0 and less than K, K is a natural number greater than J and less than or equal to N, N is the number of capacitors in the corresponding switch capacitor array, i represents the i-th phase shift position, θi represents the phase shift phase under the i-th phase shift position, and θ0 represents the target step size.

[0015] Optionally, the I-channel variable gain amplifier in the I-channel gain amplification unit and the Q-channel variable gain amplifier in the Q-channel gain amplification unit both include a first MOS tube portion, a second MOS tube portion, a third MOS tube portion and a fourth MOS tube portion, and each MOS tube portion includes M MOS tubes, M first capacitors and M resistors. When the gain is adjusted in step S2: The total width of the MOS tubes turned on in the first MOS tube section and the fourth MOS tube section is controlled to be W1, and the total width of the MOS tubes turned off is controlled to be W2; the total width of the MOS tubes turned on in the second MOS tube section and the third MOS tube section is controlled to be W2, and the total width of the MOS tubes turned off is controlled to be W1; wherein, W1+W2=W, W is the sum of the widths of the M MOS tubes.

[0016] Optionally, when W1=W2=W / 2, the gain of the corresponding variable gain amplifier is minimum; when W1=0 or W2=0, the gain of the corresponding variable gain amplifier is maximum.

[0017] Optionally, in step S1, the input impedance of the I-channel gain amplifier unit is , the input impedance of the Q-path gain amplifier unit , input to the scattering matrix of the I-way gain amplifier unit , input to the scattering matrix of the Q-path gain amplifier unit , the phase of the I differential signal , the phase of the Q-path differential signal ; In step S3: the input impedance of the I-channel gain amplifier unit , the input impedance of the Q-path gain amplifier unit , input to the scattering matrix of the I-way gain amplifier unit , input to the scattering matrix of the Q-path gain amplifier unit , the phase of the I differential signal , the phase of the Q-path differential signal ; The phase difference of the I-channel differential signal in step S1 and step S3 , the phase difference of the Q-path differential signal in step S1 and step S3 ; exist In the case of , with equal amplitudes; Wherein, Z0 represents the characteristic impedance of the coupler unit, Cd represents the capacitance of the second capacitor, s represents a complex frequency domain variable, ω represents the operating frequency, and j represents an imaginary unit.

[0018] As described above, the phase shifter circuit, electronic chip and phase shift control method of the present invention can achieve higher precision phase shifting by introducing a switched capacitor array and improving the structure of the variable gain amplifier, using the variable gain amplifier for coarse phase adjustment and then using the switched capacitor array for fine phase adjustment; the scheme of the present invention has low complexity and good performance, and is suitable for millimeter wave radar chips in various application directions. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Shown is a structural schematic diagram of a phase shifter circuit in an embodiment of the present invention.

[0020] Figure 2 Shown is a schematic diagram of the structure of an I-channel variable gain amplifier in an embodiment of the present invention.

[0021] Figure 3 It is a schematic diagram of the structure of the positive I path switch capacitor part in an embodiment of the present invention.

[0022] Figure 4 It is a schematic diagram of a specific implementation method of the phase shifter circuit in an embodiment of the present invention.

[0023] Figure 5 It is a schematic diagram showing a phase shifter circuit in an embodiment of the present invention introducing a phase difference through a switched capacitor array.

[0024] Explanation of component numbers: 10 phase shifter circuit, 100 coupler unit, 200 I-channel gain amplifier unit, 210 I-channel input matching network, 220 I-channel variable gain amplifier, 221 first MOS tube part, 222 second MOS tube part, 223 third MOS tube part, 224 fourth MOS tube part, 300 Q-channel gain amplifier unit, 310 Q-channel input matching network, 320 Q-channel variable gain amplifier, 400 synthesis unit, 500 I-channel switch capacitor array, 510 positive I-channel switch capacitor part, 520 negative I-channel switch capacitor part, 600 Q-channel switch capacitor array, 610 positive Q-channel switch capacitor part, 620 negative Q-channel switch capacitor part, 700 single-ended to differential converter, 800 differential to single-ended converter. DETAILED DESCRIPTION

[0025] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0026] See also Figures 1 to 5It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the form, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0027] like Figure 1 As shown, this embodiment provides a phase shifter circuit 10, including a coupler unit 100, an I-channel gain amplifier unit 200, a Q-channel gain amplifier unit 300, a synthesis unit 400, an I-channel switch capacitor array 500 and a Q-channel switch capacitor array 600, and further includes at least one of a single-ended to differential converter 700 and a differential to single-ended converter 800.

[0028] The coupler unit 100 receives the input differential signal (INP and INN) and converts the input differential signal (INP and INN) into an orthogonal I-channel differential signal (IP and IN) and a Q-channel differential signal (QP and QN). In one embodiment, the coupler unit 100 is implemented by a differential coupler; as an optional solution, the differential coupler is a two-stage cascade differential coupler, so as to overcome the frequency fluctuation caused by the process corner and the like through high robustness.

[0029] The I-channel gain amplification unit 200 receives an I-channel differential signal (IP and IN), and adjusts the gain of the I-channel differential signal (IP and IN) to obtain an I-channel adjusted signal (IGP and IGN).

[0030] As an example, Figure 1 As shown, the I-channel gain amplifier unit 200 includes an I-channel input matching network 210 and an I-channel variable gain amplifier 220. Wherein:

[0031] The I-way input matching network 210 is connected between the coupler unit 100 and the I-way variable gain amplifier 220, and is used to match the input impedance of the I-way variable gain amplifier 220, so as to match the input impedance of the I-way variable gain amplifier 220 to the characteristic impedance Z0 of the coupler unit 100 in different states. In one embodiment, the I-way input matching network 210 is implemented by a transformer. Of course, other structures that can achieve input impedance matching are also feasible, and there is no limitation to this.

[0032] The I-channel variable gain amplifier 220 is used to adjust the gain of the I-channel differential signal (IP and IN) to obtain the I-channel adjustment signal (IGP and IGN). Figure 2As shown, the I-channel variable gain amplifier 220 includes a first MOS tube part 221, a second MOS tube part 222, a third MOS tube part 223 and a fourth MOS tube part 224. The input end of the first MOS tube part 221 is connected in parallel with the input end of the second MOS tube part 222 as the positive input end (IN+) of the I-channel variable gain amplifier 220, the input end of the third MOS tube part 223 is connected in parallel with the input end of the fourth MOS tube part 224 as the negative input end (IN-) of the I-channel variable gain amplifier 220, the output end of the first MOS tube part 221 is connected in parallel with the output end of the third MOS tube part 223 as the positive output end (OUT+) of the I-channel variable gain amplifier 220, and the output end of the second MOS tube part 222 is connected in parallel with the output end of the fourth MOS tube part 224 as the negative output end (OUT-) of the I-channel variable gain amplifier 220. Specifically, each MOS tube part (i.e., the first MOS tube part 221, the second MOS tube part 222, the third MOS tube part 223, and the fourth MOS tube part 224) includes M MOS tubes MN, M first capacitors C1, and M resistors R. The gate of each MOS tube MN is respectively connected to the first end of each first capacitor C1 and the first end of each resistor R. The source of each MOS tube MN is connected to the reference ground. The drain of each MOS tube MN is connected in parallel as the output end of the corresponding MOS tube part. The second end of each first capacitor C1 is connected in parallel as the input end of the corresponding MOS tube part. The second end of each resistor R receives each control signal, wherein M is a natural number greater than or equal to 2. In practical applications, for the M MOS tubes MN, the size of each MOS tube MN is different; as an optional solution, the gate length of each MOS tube MN is consistent, and the gate width (hereinafter referred to as width) ratio satisfies 2 0 :2 1 :2 2 …:2 M-1 In this embodiment, the gain control of the I-channel variable gain amplifier 220 is achieved by designing the total width of the on MOS tubes and the total width of the off MOS tubes in each MOS tube portion, wherein each MOS tube is independently controlled based on each control signal.

[0033] The Q-path gain amplification unit 300 receives the Q-path differential signals (QP and QN), and adjusts the gains of the Q-path differential signals (QP and QN) to obtain Q-path adjustment signals (QGP and QGN).

[0034] As an example, Figure 1 As shown, the Q-path gain amplification unit 300 includes a Q-path input matching network 310 and a Q-path variable gain amplifier 320. Wherein:

[0035] The Q-path input matching network 310 is connected between the coupler unit 100 and the Q-path variable gain amplifier 320, and is used to match the input impedance of the Q-path variable gain amplifier 320, so as to match the input impedance of the Q-path variable gain amplifier 320 to the characteristic impedance Z0 of the coupler unit 100 in different states. In one embodiment, the Q-path input matching network 310 is implemented by a transformer, and of course, other structures capable of achieving input impedance matching are also feasible, and there is no limitation to this.

[0036] The Q-path variable gain amplifier 320 is used to adjust the gain of the Q-path differential signal (QP and QN) to obtain the Q-path adjustment signal (QGP and QGN). In one embodiment, the Q-path variable gain amplifier 320 includes a first MOS tube part, a second MOS tube part, a third MOS tube part and a fourth MOS tube part, the input end of the first MOS tube part is connected in parallel with the input end of the second MOS tube part as the positive input end of the Q-path variable gain amplifier 320, the input end of the third MOS tube part is connected in parallel with the input end of the fourth MOS tube part as the negative input end of the Q-path variable gain amplifier 320, the output end of the first MOS tube part is connected in parallel with the output end of the third MOS tube part as the positive output end of the Q-path variable gain amplifier 320, and the output end of the second MOS tube part is connected in parallel with the output end of the fourth MOS tube part as the negative output end of the Q-path variable gain amplifier 320. Among them, the structures of the MOS tube parts in the Q-path variable gain amplifier 320 are the same as those of the MOS tube parts in the I-path variable gain amplifier 220, and the relevant description can be found in the above text, which will not be repeated here.

[0037] The synthesis unit 400 receives the I-channel adjustment signal (IGP and IGN) and the Q-channel adjustment signal (QGP and QGN), and synthesizes the I-channel adjustment signal (IGP and IGN) and the Q-channel adjustment signal (QGP and QGN) to obtain the output differential signal (OUTP and OUTN). In one embodiment, the synthesis unit 400 is implemented by a transformer. Of course, other structures that can realize signal synthesis are also feasible and are not limited to this.

[0038] The I-channel switched capacitor array 500 adjusts the size of the capacitor connected to the input end of the I-channel gain amplifier unit 200 through switch control to change the phase of the I-channel differential signal (IP and IN) input to the I-channel gain amplifier unit 200 .

[0039] As an example, Figure 1 As shown, the I-way switch capacitor array 500 includes a positive I-way switch capacitor section 510 and a negative I-way switch capacitor section 520. Wherein:

[0040] The positive I-way switch capacitor unit 510 is connected to the positive input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210), and the phase of the positive signal IP in the I-way differential signal input to the positive input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210) is changed by adjusting the capacitance of the positive input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210) through switch control. In one embodiment, as Figure 3 As shown, the positive I-path switch capacitor unit 510 includes N second capacitors C2 and N switches S. The N second capacitors C2 and the N switches S are respectively connected in series and then connected in parallel to the positive input end of the I-path gain amplifier unit 200 (specifically, the I-path input matching network 210), wherein N is a natural number greater than or equal to 1; of course, other structures that realize capacitance value adjustment through switch control are also feasible, and there is no limitation to this.

[0041] The negative I-way switch capacitor unit 520 is connected to the negative input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210), and the phase of the negative signal IN in the I-way differential signal input to the negative input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210) is changed by adjusting the capacitance connected to the negative input terminal of the I-way gain amplifier unit 200 (specifically, the I-way input matching network 210) through switch control. It should be noted that the negative I-way switch capacitor unit 520 has the same structure as the positive I-way switch capacitor unit 510, and the relevant description can be found in the above text, which will not be repeated here.

[0042] The Q-path switched capacitor array 600 adjusts the size of the capacitor connected to the input end of the Q-path gain amplifier unit 300 through switch control to change the phase of the Q-path differential signal (QP and QN) input to the Q-path gain amplifier unit 300 .

[0043] As an example, Figure 1 As shown, the Q-path switch capacitor array 600 includes a positive Q-path switch capacitor section 610 and a negative Q-path switch capacitor section 620. Wherein:

[0044] The positive Q-path switch capacitor section 610 is connected to the positive input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310), and the phase of the positive signal QP in the Q-path differential signal input to the positive input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310) is changed by adjusting the capacitance of the positive input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310) through switch control. It should be noted that the positive Q-path switch capacitor section 610 has the same structure as the positive I-path switch capacitor section 510, and the relevant description can be found above, which will not be repeated here.

[0045] The negative Q-path switch capacitor section 620 is connected to the negative input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310), and the phase of the negative signal QN in the Q-path differential signal input to the negative input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310) is changed by adjusting the capacitance connected to the negative input terminal of the Q-path gain amplifier unit 300 (specifically, the Q-path input matching network 310) through switch control. It should be noted that the negative Q-path switch capacitor section 620 has the same structure as the positive I-path switch capacitor section 510, and the relevant description can be found above, which will not be repeated here.

[0046] In order to realize single-ended input, a single-ended-to-differential converter 700 may be designed in the phase shifter circuit 10; wherein the single-ended-to-differential converter 700 receives an input single-ended signal (INPUT) and converts the input single-ended signal (INPUT) into an input differential signal (INP and INN). In one embodiment, the single-ended-to-differential converter 700 is implemented by a transformer. Of course, other structures capable of realizing single-ended-to-differential conversion are also feasible and are not limited thereto.

[0047] In order to achieve single-ended output, a differential-to-single-ended converter 800 may be designed in the phase shifter circuit 10; wherein the differential-to-single-ended converter 800 receives the output differential signal (OUTP and OUTN) and converts the output differential signal (OUTP and OUTN) into an output single-ended signal (OUTPUT). In one embodiment, the differential-to-single-ended converter 800 is implemented using a transformer. Of course, other structures that can achieve differential-to-single-ended conversion are also feasible and are not limited thereto.

[0048] This embodiment further provides a phase shift control method of a phase shifter circuit 10 , comprising the following steps; wherein the phase shifter circuit 10 is implemented using the circuit structure described above.

[0049] Step S1: Switching and controlling the I-channel switch capacitor array 500 and the Q-channel switch capacitor array 600, respectively connecting J capacitors to the two input ends of the I-channel gain amplifier unit 200 and the two input ends of the Q-channel gain amplifier unit 300, where J is a natural number greater than or equal to 0 and less than K, and N is the number of capacitors in the corresponding switch capacitor array.

[0050] At this time, the input impedance of the I-channel gain amplifier unit 200 is , the input impedance of the Q-path gain amplifier unit 300 ; Input to the scattering matrix of I-way gain amplifier unit 200 , input to the scattering matrix of the Q-path gain amplifier unit 300 ; Phase of I differential signal , the phase of the Q-path differential signal , both have the same amplitude and a phase difference of 90°; wherein Z0 represents the characteristic impedance of the coupler unit 100, s represents a complex frequency domain variable, Cd represents the capacitance of the second capacitor, j represents an imaginary unit, and ω represents an operating frequency.

[0051] Step S2: By adjusting the gain of the I-channel gain amplifier unit 200 and the gain of the Q-channel gain amplifier unit 300, the gain of the I-channel variable gain amplifier 220 and the gain of the Q-channel variable gain amplifier 320 are actually adjusted to obtain a phase shift θi=2i*θ0, wherein i represents the i-th phase shift position, θi represents the phase shift phase under the i-th phase shift position, and θ0 represents the target step size.

[0052] Specifically, when the gain of the I-channel variable gain amplifier 220 is adjusted: the total width of the MOS tubes MN that are turned on in the first MOS tube section 221 and the fourth MOS tube section 224 is controlled to be W1, and the total width of the MOS tubes MN that are turned off is controlled to be W2; the total width of the MOS tubes MN that are turned on in the second MOS tube section 222 and the third MOS tube section 223 is controlled to be W2, and the total width of the MOS tubes MN that are turned off is controlled to be W1; W1+W2=W, W is the sum of the widths of the M MOS tubes in any MOS tube section. When W1=W2=W / 2, the gain of the I-channel variable gain amplifier 220 is the minimum; when W1=0 or W2=0, the gain of the I-channel variable gain amplifier 220 is the maximum.

[0053] When the on-off control of each MOS tube of each MOS tube section is performed based on each control signal: the on-off conditions of each MOS tube in the first MOS tube section 221 and the fourth MOS tube section 224 are the same, the on-off conditions of each MOS tube in the second MOS tube section 222 and the third MOS tube section 223 are the same, and the on-off conditions of each MOS tube in the first MOS tube section 221 and the fourth MOS tube section 224 are opposite to the on-off conditions of each MOS tube in the second MOS tube section 222 and the third MOS tube section 223; taking each MOS tube section including five MOS tubes and the width ratio of the five MOS tubes being 1:2:4:8:16 as an example, assuming that: the on-off conditions of each MOS tube in the first MOS tube section 221 and the fourth MOS tube section 224 are opposite to the on-off conditions of each MOS tube in the second MOS tube section 222 and the third MOS tube section 223 In the first MOS tube section 221 and the fourth MOS tube section 224, the third MOS tube and the fifth MOS tube are turned on, and the first MOS tube, the second MOS tube and the fourth MOS tube are turned off, then the total width W1 of the turned-on MOS tubes is 20W0, and the total width W2 of the turned-off MOS tubes is 11W0. In the second MOS tube section 222 and the third MOS tube section 223, the first MOS tube, the second MOS tube and the fourth MOS tube are turned on, and the third MOS tube and the fifth MOS tube are turned off, then the total width W2 of the turned-on MOS tubes is 11W0, and the total width W1 of the turned-off MOS tubes is 20W0, wherein W0 is the unit width. For the positive output end, the total equivalent gain of the first MOS tube part 221 and the third MOS tube part 223 is W=W1-W2=9W0, and for the negative output end, the total equivalent gain of the second MOS tube part 222 and the fourth MOS tube part 223 is W=-W1+W2=-9W0, and the two have the same amplitude and opposite signs; by changing the values ​​of W1 and W2, different gain gears can be obtained. In the gain control process, the total width of the on MOS tube and the off MOS tube corresponding to the positive input end (IN+), the negative input end (IN-), the positive output end (OUT+) and the negative output end (OUT-) of the I-channel variable gain amplifier 220 is W, and it always remains unchanged, thereby ensuring that the input and output impedance of the I-channel variable gain amplifier 220 remains unchanged at different gears.

[0054] The gain control method of the Q-path variable gain amplifier 320 is the same as the gain control method of the I-path variable gain amplifier 220. The relevant content can be found in the above text and will not be repeated here. It should be noted that W1 and W2 corresponding to the I-path variable gain amplifier 220 and W1 and W2 corresponding to the Q-path variable gain amplifier 320 can be the same or different, that is, the gain of the I-path variable gain amplifier 220 and the gain of the Q-path variable gain amplifier 320 can be the same or different, which is determined by the specific application requirements and the actual control results, and there is no limitation on this.

[0055] In practical applications, the initial phase shift is obtained by adjusting the gain of the I-channel variable gain amplifier 220 and the gain of the Q-channel variable gain amplifier 320; wherein the phase shift accuracy depends on the inverse tangent function of the ratio of the difference between W1 and W2 in the I-channel variable gain amplifier 220 and the difference between W1 and W2 in the Q-channel variable gain amplifier 320, that is, The value of .

[0056] Step S3, keeping the gain of the I-channel gain amplifier unit 200 and the gain of the Q-channel gain amplifier unit 300 unchanged, actually keeping the gain of the I-channel variable gain amplifier 220 and the gain of the Q-channel variable gain amplifier 320 unchanged, switching and regulating the I-channel switch capacitor array 500 and the Q-channel switch capacitor array 600, respectively connecting K capacitors to the two input ends of the I-channel gain amplifier unit 200 and the two input ends of the Q-channel gain amplifier unit 300, so as to obtain a phase shift phase θi=(2i+1)*θ0, where K is a natural number greater than J and less than or equal to N.

[0057] At this time, the input impedance of the I-channel gain amplifier unit 200 is , the input impedance of the Q-path gain amplifier unit 300 ; Input to the scattering matrix of I-way gain amplifier unit 200 , input to the scattering matrix of the Q-path gain amplifier unit 300 ; Phase of I differential signal , the phase of the Q-path differential signal , the two have the same amplitude and a phase difference of 90°.

[0058] Thus, the phase difference between the I-channel differential signal in step S1 and step S3 is , the phase difference between the Q-path differential signal in step S1 and step S3 ,Right now, , the two are equal; In the case of , with equal amplitudes, take appropriate values ​​of K and J to satisfy Since the input impedance of the variable gain amplifier remains unchanged in different states, the phase difference between step S1 and step S3 remains unchanged, and high-precision phase shifting can be obtained.

[0059] Figure 4 FIG. 1 shows a specific implementation of the phase shifter circuit 10 of the present embodiment, wherein N=1; the final result of switching control based on the I-way switch capacitor array 500 and the Q-way switch capacitor array 600 is as follows: Figure 5As shown, SI capacitor on represents the phase of the I-channel differential signal corresponding to when the I-channel switch capacitor array 500 is turned on, SI capacitor off represents the phase of the I-channel differential signal corresponding to when the I-channel switch capacitor array 500 is turned off, SQ capacitor on represents the phase of the Q-channel differential signal corresponding to when the Q-channel switch capacitor array 600 is turned on, SQ capacitor off represents the phase of the Q-channel differential signal corresponding to when the Q-channel switch capacitor array 600 is turned off, SI capacitor switch difference represents the phase difference of the I-channel differential signal corresponding to when the I-channel switch capacitor array 500 is turned on and off, SQ capacitor switch difference represents the phase difference of the Q-channel differential signal corresponding to when the Q-channel switch capacitor array 600 is turned on and off, Figure 5 It can be seen that in the frequency range of 60 GHz to 90 GHz, a phase shift of 2.2° to 3.0° can be introduced through the switched capacitor array, thereby achieving the highest precision phase shift.

[0060] In fact, by using a switched capacitor array to assist a variable gain amplifier, the phase shift range of the phase shifter based on the variable gain amplifier can be doubled, the phase shift accuracy can be doubled, and a higher precision phase shift can be achieved. Figure 4 Taking the variable gain amplifier shown as being able to achieve 64 phase shift positions with a phase shift accuracy of 5.625° as an example, by adding a switch capacitor array, the phase shifter circuit 10 can ultimately achieve 128 phase shift positions with a phase shift accuracy of 2.8125°.

[0061] This embodiment also provides an electronic chip, including a phase shifter circuit 10; wherein the phase shifter circuit 10 is implemented using the circuit structure described above. In one implementation, the electronic chip is a millimeter wave chip; in practical applications, the millimeter wave chip may include a low noise amplifier, a radio frequency filter, a power amplifier, etc. in addition to the phase shifter circuit 10, which is determined by specific application requirements and is not limited thereto.

[0062] In summary, the phase shifter circuit, electronic chip and phase shift control method of the present invention can achieve higher precision phase shifting by introducing a switch capacitor array and improving the structure of a variable gain amplifier, using a variable gain amplifier for coarse phase adjustment and then using a switch capacitor array for fine phase adjustment; the scheme of the present invention has low complexity and good performance, and is suitable for millimeter wave radar chips in various application directions. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0063] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A phase shifter circuit, characterized in that: The phase shifter circuit comprises: A coupler unit receives an input differential signal and converts the input differential signal into an orthogonal I-channel differential signal and a Q-channel differential signal; An I-channel gain amplification unit receives the I-channel differential signal and adjusts the gain of the I-channel differential signal to obtain an I-channel adjustment signal; A Q-path gain amplifying unit receives the Q-path differential signal and adjusts the gain of the Q-path differential signal to obtain a Q-path adjustment signal; A synthesis unit receives the I-path adjustment signal and the Q-path adjustment signal, and synthesizes the I-path adjustment signal and the Q-path adjustment signal to obtain an output differential signal; An I-channel switch capacitor array, which adjusts the size of the capacitor connected to the input end of the I-channel gain amplifier unit by switch control to change the phase of the I-channel differential signal input to the I-channel gain amplifier unit; The Q-path switch capacitor array adjusts the size of the capacitor connected to the input end of the Q-path gain amplifier unit through switch control to change the phase of the Q-path differential signal input to the Q-path gain amplifier unit.

2. The phase shifter circuit according to claim 1, characterized in that: The I-channel gain amplification unit includes an I-channel input matching network and an I-channel variable gain amplifier, wherein the I-channel input matching network is used to match the input impedance of the I-channel variable gain amplifier, and the I-channel variable gain amplifier is used to adjust the gain of the I-channel differential signal to obtain the I-channel adjustment signal; The Q-path gain amplification unit includes a Q-path input matching network and a Q-path variable gain amplifier, wherein the Q-path input matching network is used to match the input impedance of the Q-path variable gain amplifier, and the Q-path variable gain amplifier is used to adjust the gain of the Q-path differential signal to obtain the Q-path adjustment signal.

3. The phase shifter circuit according to claim 2, characterized in that: The I-path input matching network and the Q-path input matching network are both implemented by transformers.

4. The phase shifter circuit according to claim 2, characterized in that: The I-channel variable gain amplifier and the Q-channel variable gain amplifier both include a first MOS tube part, a second MOS tube part, a third MOS tube part and a fourth MOS tube part, the first MOS tube part input end and the second MOS tube part input end are connected in parallel as the positive input end of the corresponding variable gain amplifier, the third MOS tube part input end and the fourth MOS tube part input end are connected in parallel as the negative input end of the corresponding variable gain amplifier, the first MOS tube part output end and the third MOS tube part output end are connected in parallel as the positive output end of the corresponding variable gain amplifier, and the second MOS tube part output end and the fourth MOS tube part output end are connected in parallel as the negative output end of the corresponding variable gain amplifier; wherein each MOS tube part includes M MOS tubes, M first capacitors and M resistors, the gate of each MOS tube is connected to the first end of each first capacitor and the first end of each resistor respectively, the source of each MOS tube is connected to the reference ground, the drain of each MOS tube is connected in parallel as the output end of the corresponding MOS tube part, the second end of each first capacitor is connected in parallel as the input end of the corresponding MOS tube part, and the second end of each resistor receives each control signal, and M is a natural number greater than or equal to 2.

5. The phase shifter circuit according to claim 1, characterized in that: The I-path switch capacitor array includes a positive I-path switch capacitor unit and a negative I-path switch capacitor unit, and the Q-path switch capacitor array includes a positive Q-path switch capacitor unit and a negative Q-path switch capacitor unit, and each switch capacitor unit adjusts the capacitance of the corresponding input end connected to the corresponding gain amplifier unit through switch control; wherein each switch capacitor unit includes N second capacitors and N switches, and the N second capacitors and the N switches are respectively connected in series and then connected in parallel to the corresponding input end of the corresponding gain amplifier unit, and N is a natural number greater than or equal to 1.

6. The phase shifter circuit according to claim 1, characterized in that: The phase shifter circuit further includes: A single-ended-to-differential converter receives an input single-ended signal and converts the input single-ended signal into the input differential signal; And / or, a differential-to-single-ended converter receives the output differential signal and converts the output differential signal into an output single-ended signal.

7. An electronic chip, characterized in that: The electronic chip comprises: a phase shifter circuit as described in any one of claims 1 to 6.

8. The electronic chip according to claim 7, characterized in that: The electronic chip is a millimeter wave chip.

9. A phase shift control method for a phase shifter circuit according to any one of claims 1 to 6, characterized in that: The phase shift control method comprises: Step S1, performing switch control on the I-path switch capacitor array and the Q-path switch capacitor array, and connecting J capacitors to two input ends of the I-path gain amplifier unit and two input ends of the Q-path gain amplifier unit respectively; Step S2, obtaining a phase shift θi=2i*θ0 by adjusting the gain of the I-path gain amplifier unit and the gain of the Q-path gain amplifier unit; Step S3, keeping the gain of the I-path gain amplifier unit and the gain of the Q-path gain amplifier unit unchanged, switching and regulating the I-path switch capacitor array and the Q-path switch capacitor array, respectively connecting K capacitors to the two input ends of the I-path gain amplifier unit and the two input ends of the Q-path gain amplifier unit, so as to obtain a phase shift phase θi=(2i+1)*θ0; Wherein, J is a natural number greater than or equal to 0 and less than K, K is a natural number greater than J and less than or equal to N, N is the number of capacitors in the corresponding switch capacitor array, i represents the i-th phase shift position, θi represents the phase shift phase under the i-th phase shift position, and θ0 represents the target step size.

10. The phase shift control method according to claim 9, characterized in that: The I-channel variable gain amplifier in the I-channel gain amplification unit and the Q-channel variable gain amplifier in the Q-channel gain amplification unit both include a first MOS tube portion, a second MOS tube portion, a third MOS tube portion, and a fourth MOS tube portion, and each MOS tube portion includes M MOS tubes, M first capacitors, and M resistors. When the gain is adjusted in step S2: The total width of the MOS tubes turned on in the first MOS tube section and the fourth MOS tube section is controlled to be W1, and the total width of the MOS tubes turned off is controlled to be W2; the total width of the MOS tubes turned on in the second MOS tube section and the third MOS tube section is controlled to be W2, and the total width of the MOS tubes turned off is controlled to be W1; wherein, W1+W2=W, W is the sum of the widths of the M MOS tubes.

11. The phase shift control method according to claim 10, characterized in that: When W1=W2=W / 2, the gain of the corresponding variable gain amplifier is the smallest; when W1=0 or W2=0, the gain of the corresponding variable gain amplifier is the largest.

12. The phase shift control method according to claim 9, characterized in that: In step S1, the input impedance of the I-channel gain amplifier unit is , the input impedance of the Q-path gain amplifier unit , input to the scattering matrix of the I-way gain amplifier unit , input to the scattering matrix of the Q-path gain amplifier unit , the phase of the I differential signal , the phase of the Q-path differential signal ; In step S3: the input impedance of the I-channel gain amplifier unit , the input impedance of the Q-path gain amplifier unit , input to the scattering matrix of the I-way gain amplifier unit , input to the scattering matrix of the Q-path gain amplifier unit , the phase of the I differential signal , the phase of the Q-path differential signal ; The phase difference of the I-channel differential signal in step S1 and step S3 , the phase difference of the Q-path differential signal in step S1 and step S3 ; exist In the case of , with equal amplitudes; Wherein, Z0 represents the characteristic impedance of the coupler unit, Cd represents the capacitance of the second capacitor, s represents a complex frequency domain variable, ω represents the operating frequency, and j represents an imaginary unit.

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