Multi-channel single-double sampling point conversion device compatible with any sampling rate
By designing a multi-channel single and double sample point conversion device that is compatible with arbitrary sampling rate, using asynchronous FIFO and a combiner for cross-clock domain processing, the problems of high coupling degree and delay in multi-channel reception are solved, and high compatibility and Low latency processing effect.
Patent Information
- Application Number
- CN202411276904.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-12
- Publication Date
- 2024-12-31
AI Technical Summary
In the prior art, due to the multiple relationships of different sampling rates in multi-channel reception, the coupling degree is large, the adaptability is poor, the link delay is long, and it is not conducive to transplantability, making it difficult to compatible with multi-channel processing at any sampling rate.
Design a multi-channel single and double sample point conversion device compatible with arbitrary sampling rates, including a multi-channel formatting module and a merging module with a tree structure, using asynchronous FIFO and a combiner for cross-clock domain processing and ping-pong selection output, reducing coupling and link delay.
Compatibility with arbitrary clock/sampling rates between different channels is achieved, processing delay is reduced, adaptability and portability is improved, and development time and storage resources are saved.
Smart Images
Figure CN119232158A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of communication technology, and in particular to a multi-channel single-to-double sample point conversion device compatible with any sampling rate. Background Art
[0002] As 5G / satellite wireless communication technology enters the commercial era, the demand for multi-carrier and multi-channel reception in various application scenarios is gradually increasing. As a key part of the RRU in the wireless system, the digital front end (DFE) mainly completes digital up / down conversion technology and multi-rate digital signal processing, including frequency conversion, filtering, extraction / interpolation of signals. The DFE link includes an uplink path and a downlink path. In the uplink path, there are usually multiple uplink channels, and each uplink channel contains multiple carriers. Multiple uplink channels will introduce digital front-end processing problems with multiple sampling rates. The commonly used method is multi-channel combined polling processing. However, when implementing the existing technology, the multiple relationship between different sampling rates needs to be considered, the coupling degree between channels is large, and the adaptability is poor. In addition, the header information needs to be aligned before starting, and the link processing delay is large. Once multi-channel expansion is involved, the implementation process needs to be reconstructed, which is not conducive to portability. Summary of the invention
[0003] The technical problem to be solved by the present invention is to provide a multi-channel single-to-double sample point conversion device compatible with any sampling rate, which can improve compatibility, reduce link delay and improve portability.
[0004] The technical solution adopted by the present invention to solve the technical problem is: to provide a multi-channel single-to-double sample point conversion device compatible with any sampling rate, comprising:
[0005] A multi-channel formatting module, corresponding to each channel, is used to convert the input data into single and double samples;
[0006] A merging module, comprising a plurality of dual-input single-output merging units, wherein the plurality of dual-input single-output merging units form a tree structure, wherein the tree structure is divided into log2(N) levels, wherein when the number of channels is an even number, N is the number of channels, and when the number of channels is an odd number, N is the number of channels plus one; the i-th level of the tree structure comprises The first-level merging unit is used for cross-clock domain processing and ping-pong selection output of two adjacent channels, and the merging units after the second level are used for ping-pong selection output.
[0007] The merging unit includes a first asynchronous FIFO, a second asynchronous FIFO and a combiner, the input ends of the first asynchronous FIFO and the second asynchronous FIFO serve as two input ends of the merging unit respectively, and the output ends of the first asynchronous FIFO and the second asynchronous FIFO are connected to the input end of the combiner.
[0008] The input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit are different; the input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the merging units after the second level are the same.
[0009] The output clocks of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit meet Wherein, M(n) represents the input clock of the nth channel.
[0010] The depth of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit is 2 N .
[0011] Beneficial Effects
[0012] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art: the present invention can support the input of any clock / sampling rate between different channels, including split / non-split scenarios, and the data format between the output channels is relatively uniform, with strong compatibility advantages. When processing, only the data relationship between two adjacent channels needs to be considered, with low coupling and strong adaptability. For data arriving at different times, the longest and shortest channel data arrival time N cycles are used as the calculation. Compared with the prior art, the present invention can save N-2 cycles, where 2 cycles is the ping-pong decision of the cache fifo and the input / output processing delay. The present invention can be iterated in a parameterized manner, which is conducive to IPization, saves development time, has high link parallelism, strong compatibility with the types of input sampling rates, small overall link delay, and less storage resources than the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 2 is a schematic diagram of the structure of a multi-channel single-to-double sample point conversion device compatible with any sampling rate according to an embodiment of the present invention;
[0014] Figure 2 is a timing diagram of embodiment 1 of the present invention;
[0015] Figure 3 This is a timing diagram of embodiment 2 of the present invention. DETAILED DESCRIPTION
[0016] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0017] The embodiments of the present invention relate to a multi-channel single-to-double sample point conversion device compatible with any sampling rate, such as Figure 1 As shown, including:
[0018] The multi-channel formatting module, corresponding to each channel, is used to convert the input data into single and double samples. This module implements single and double sample conversion, format adjustment and frame header alignment. For each input channel, the clock / sampling rate is consistent with the channel entry.
[0019] A merging module, comprising a plurality of dual-input single-output merging units, wherein the plurality of dual-input single-output merging units form a tree structure, wherein the tree structure is divided into log2(N) levels, wherein when the number of channels is an even number, N is the number of channels, and when the number of channels is an odd number, N is the number of channels plus one; the i-th level of the tree structure comprises The first-level merging unit is used for cross-clock domain processing and ping-pong selection output of two adjacent channels, and the merging units after the second level are used for ping-pong selection output.
[0020] The merging unit includes a first asynchronous FIFO, a second asynchronous FIFO and a combiner, the input ends of the first asynchronous FIFO and the second asynchronous FIFO serve as two input ends of the merging unit respectively, and the output ends of the first asynchronous FIFO and the second asynchronous FIFO are connected to the input end of the combiner.
[0021] Figure 1 The inputs of different colors represent different sampling rates / clocks of the inputs. It can be found that the input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit of the merging module in this embodiment are different; the input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the merging units after the second level are the same.
[0022] The depth of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit is 2 N , the output clock meets Wherein, M(n) represents the input clock of the nth channel.
[0023] It is not difficult to find that the present embodiment adopts the processing idea of asynchronous fifo, the channels and the asynchronous fifo in the first-level merging unit correspond one to one, receive the data of their respective channels, and under the channel clock, the channel enable is used as the input enable of the fifo to write data, so that the device of the present embodiment can be compatible with inputs of any sampling rate. Since the merging unit in the present embodiment is a dual-input merging unit, it only performs ping-pong judgment between adjacent channels. Once it is identified which asynchronous fifo has data, it is read out, and the ping-pong judgment will not cause the blocking of a certain channel data, reducing the coupling between channels. The combining module in the present embodiment adopts a tree structure for step-by-step transmission, so that the channel data that arrives first is output first, and the whole process does not need to be aligned. It is calculated by the arrival time of the longest and shortest channel data N cycles, which can save N-2 cycles, where 2 cycles is the ping-pong judgment and input / output processing delay of the cache fifo, which speeds up the processing process and reduces the delay of the combining processing link. The present invention adopts the application of simple asynchronous fifo, and the cache resource occupies 2^N*Kbit resources at most, wherein K is the input data bit width, and the hardware resource amount is relatively small. In addition, the present invention can be iterated in a parameterized manner, which is conducive to IPization, saves development time, has high link parallelism, and has strong compatibility with the types of input sampling rates.
[0024] The present invention is further illustrated by two specific embodiments below.
[0025] Embodiment 1: Two-channel input, each channel sampling rate and clock have a 1:1 relationship, channel 0 input clock ch0_clk = 245.76MHz, channel 2 input clock ch1_clk = 491.52MHz.
[0026] After the device of this embodiment is used for processing, Figure 2 As shown, after 2 beats, the timing of the two data channels between the output channels is relatively fixed, the first data channel and the clock are connected to the first asynchronous fifo, and the second data channel and the clock are connected to the second asynchronous fifo. The output clocks of the two asynchronous fifos need to meet the bandwidth and are configured to be 491.52 MHz. In theory, they can be configured to be greater than or equal to 368.64 MHz, and the combining processing module performs adaptive processing.
[0027] Embodiment 2: Two-channel input, the sampling rate and clock of each channel have a 1:1 relationship, channel 0 input clock ch0_clk = 7.68MHz, channel 2 input clock ch1_clk = 245.76MHz.
[0028] After the device of this embodiment is used for processing, Figure 3As shown, after 2 beats, the timing of the two data channels between the output channels is relatively fixed. The first data and clock are connected to the first asynchronous fifo, and the second data and clock are connected to the second asynchronous fifo. The output clocks of the two asynchronous fifos need to meet the bandwidth and are configured to 245.76MHz. Theoretically, they can be configured to be greater than or equal to 126.72MHz. Here, the largest clock configuration of the two input channels is used, and the combining processing module performs adaptive processing.
Claims
1. A multi-channel single-to-double sample point conversion device compatible with any sampling rate, characterized in that: include: A multi-channel formatting module, corresponding to each channel, is used to convert the input data into single and double samples; A merging module, comprising a plurality of dual-input single-output merging units, wherein the plurality of dual-input single-output merging units form a tree structure, wherein the tree structure is divided into log2(N) levels, wherein when the number of channels is an even number, N is the number of channels, and when the number of channels is an odd number, N is the number of channels plus one; the i-th level of the tree structure comprises The first-level merging unit is used for cross-clock domain processing and ping-pong selection output of two adjacent channels, and the merging units after the second level are used for ping-pong selection output.
2. The multi-channel single-to-double sample point conversion device compatible with any sampling rate according to claim 1, characterized in that: The merging unit includes a first asynchronous FIFO, a second asynchronous FIFO and a combiner, the input ends of the first asynchronous FIFO and the second asynchronous FIFO serve as two input ends of the merging unit respectively, and the output ends of the first asynchronous FIFO and the second asynchronous FIFO are connected to the input end of the combiner.
3. The multi-channel single-to-double sample point conversion device compatible with any sampling rate according to claim 2, characterized in that: The input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit are different; the input clock and output clock of the first asynchronous FIFO and the second asynchronous FIFO in the merging units after the second level are the same.
4. The multi-channel single-to-double sample point conversion device compatible with any sampling rate according to claim 2, characterized in that: The output clocks of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit meet Wherein, M(n) represents the input clock of the nth channel.
5. The multi-channel single-to-double sample point conversion device compatible with any sampling rate according to claim 1, characterized in that: The depth of the first asynchronous FIFO and the second asynchronous FIFO in the first-level merging unit is 2 N .