Test circuit and memory

Abstract

The invention provides a test circuit and a memory, in an aging test mode, a test pre-charge command or an initial refresh command is output as an intermediate signal, and in a centralized refresh stage, one test refresh command is generated based on each received initial refresh command; and in a normal mode, outputting the test clock signal as an intermediate signal, and generating one test refresh command by using the received first initial refresh command every preset duration.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to a test circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have put forward higher and higher requirements on the data transmission speed when manufacturing and using computers and other equipment. Taking Dynamic Random Access Memory (DRAM) as an example, in order to ensure the correctness of its storage function, the memory needs to be tested, such as memory built-in self test (MBIST). MBIST circuit needs to support various test modes and various commands therein need to meet the provisions of industry standards, so its specific circuit design becomes a difficult problem. Summary of the invention

[0003] The present disclosure provides a test circuit and a memory.

[0004] The technical solution of the present disclosure is achieved as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a test circuit, which is applied to a memory, and the test circuit includes:

[0006] A first command circuit is configured to generate an initial refresh command based on a received test clock signal, and a time interval between two adjacent initial refresh commands is a first time length;

[0007] a selection circuit connected to the first command circuit and configured to receive a test precharge command, the initial refresh command and the test clock signal; in an aging test mode, output the test precharge command or the initial refresh command as an intermediate signal; in a normal mode, output the test clock signal as the intermediate signal;

[0008] A first counter, connected to the selection circuit, configured to count the intermediate signal to generate a first count value;

[0009] The second command circuit is connected to both the first command circuit and the first counter, and is configured to receive the first count value and the initial refresh command. In the aging test mode, if the first count value represents the value of the initial refresh command generated by the memory in the concentrated refresh phase, then one test refresh command is generated based on each received initial refresh command; in the normal mode, after each time the first count value represents a preset time period, one test refresh command is generated using the first received initial refresh command.

[0010] In some embodiments, the first duration is a fixed value; and the first command circuit includes:

[0011] a second counter configured to count the received test clock signal and output a second count value;

[0012] a first decoding unit connected to the second counter and configured to output a first refresh command when the second count value reaches a first threshold;

[0013] a second decoding unit connected to the second counter and configured to output a second refresh command if the second count value reaches the second threshold for the first time; and, after the second count value reaches the second threshold for the first time, output a second refresh command if the second count value reaches the second threshold a preset number of times;

[0014] A first selector is connected to the first decoding unit and the second decoding unit, and is configured to receive a frequency indication signal, and output the first refresh command as the initial refresh command when the frequency indication signal indicates that the frequency of the test clock signal is a first frequency; and output the second refresh command as the initial refresh command when the frequency indication signal indicates that the frequency of the test clock signal is a second frequency.

[0015] In some embodiments, the memory is alternately in the concentrated refresh phase and the working phase in the aging test mode, and the selection circuit includes:

[0016] a second selector configured to output the received initial refresh command as a preselection signal if the memory is in the centralized refresh phase; and to output the received test precharge command as the preselection signal if the memory is in the working phase;

[0017] The third selector is connected to the second selector and configured to receive the preselected signal and the test clock signal, and output the preselected signal as the intermediate signal in the aging test mode; and output the test clock signal as the intermediate signal in the normal mode.

[0018] In some embodiments, the second command circuit is further configured to generate a test activation command based on the first received initial refresh command in the aging test mode if the first count value indicates that the concentrated refresh phase has ended; or, in the normal mode, generate a test activation command based on the second received initial refresh command after each time the first count value indicates a preset time period.

[0019] In some embodiments, the second command circuit comprises:

[0020] A main control circuit is configured to receive the initial refresh command, the test precharge command and the first count value, generate and output a first window signal and an activation indication signal; wherein, in the stage where the memory allows a refresh operation to be performed, the first window signal is in a valid state; and in the stage where the memory allows an activation operation to be performed, the activation indication signal is in a valid state;

[0021] a sampling circuit configured to sample the initial refresh command twice in succession based on the test clock signal to generate a delayed refresh command;

[0022] A first gating unit is connected to both the main control circuit and the sampling circuit, and is configured to generate one test refresh command using one delayed refresh command only when the first window signal is in a valid state;

[0023] The second gating unit is connected to both the main control circuit and the sampling circuit, and is configured to generate a test refresh command using one delayed refresh command only when the activation indication signal is in a valid state.

[0024] In some embodiments, the main control circuit includes:

[0025] A first control circuit is connected to the first counter and configured to decode the first count value in an aging test mode, and generate a first switching pulse when the decoding result indicates that the centralized refresh phase is ended or the working phase is ended;

[0026] The signal generating circuit is connected to the first control circuit and configured to generate the first window signal; in the aging test mode, the state of the first window signal is changed once each time the first switching pulse is received.

[0027] In some embodiments, the first control circuit is specifically configured to receive the first window signal; when the first window signal is in a valid state, if the first count value reaches a third threshold, one first switching pulse is generated; or when the first window signal is in an invalid state, if the first count value reaches a fourth threshold, one first switching pulse is generated;

[0028] Wherein, in the aging test mode, when the first window signal is valid, it indicates that the memory is in a centralized refresh phase, and when the first window signal is invalid, it indicates that the memory is in a working phase.

[0029] In some embodiments, the main control circuit further includes:

[0030] a second control circuit connected to the first counter and configured to decode the first count value in a normal mode; and generate a second switching pulse when one of the test precharge commands is received or two of the initial refresh commands are received, when the decoding result indicates that the preset time has passed;

[0031] The signal generating circuit is also connected to the second control circuit and is configured to change the state of the first window signal once each time the second switching pulse is received in a normal mode.

[0032] In some embodiments, the second control circuit comprises:

[0033] A third decoding unit is configured to decode the first count value, and generate a decoding pulse if the decoding result indicates that the preset time length has passed;

[0034] a latch unit connected to the third decoding unit, configured to receive the decoding pulse and the test activation command, generate and output a second window signal; wherein, each time the decoding pulse is received, the second window signal is controlled to change from an invalid state to a valid state, and each time the test activation command is received, the second window signal is controlled to change from a valid state to an invalid state;

[0035] a first logic unit connected to the latch unit and configured to generate a second end pulse by receiving the first test precharge command if the second window signal is in a valid state;

[0036] a refresh counting unit connected to the latch unit and the first command generating circuit, and configured to generate a third end pulse if two initial refresh commands are received when the second window signal is in a valid state;

[0037] The second logic unit is configured to generate and output one of the second switching pulses whenever one of the second end pulses or one of the third end pulses is received.

[0038] In some embodiments, the preset duration has multiple values; the third decoding unit includes:

[0039] A second decoder is configured to receive the first count value, and generate a first pulse when the first count value reaches a fifth threshold;

[0040] A third decoder is configured to receive the first count value, and generate a second pulse when the first count value reaches a sixth threshold;

[0041] a fourth selector configured to receive an interval selection signal, and generate the decoding pulse using the first pulse or the second pulse based on the interval selection signal;

[0042] The frequency of the interval selection signal and the test clock signal jointly determine the value of the preset duration.

[0043] In some embodiments, the refresh counting unit includes:

[0044] A third counter is configured to count the received initial refresh command to generate a third count value;

[0045] The first decoder is connected to the third counter, and is configured to generate one third end pulse when the third count value is 2.

[0046] In some embodiments, the memory further includes a first control input gate, the output end of the first control transmission gate is connected to the input end of the third counter; wherein the first control transmission gate is configured to receive the second window signal and the initial refresh command; when the second window signal is in a valid state, the initial refresh command is transmitted to the third counter; when the second window signal is in an invalid state, the initial refresh command is shielded so that the third count value remains unchanged.

[0047] In some embodiments, the signal generating circuit includes a fifth selector and a first flip-flop;

[0048] a fifth selector, configured to receive a mode flag signal, and to generate a reset command using one of the first switching pulses when the mode flag signal indicates an aging test mode; and to generate a reset command using one of the second switching pulses when the mode flag signal indicates a normal mode;

[0049] The clock end of the first trigger receives the reset command, the input end of the first trigger is connected to the clock end of the first trigger and its own inverting output end, and the output end of the first trigger outputs the first window signal.

[0050] In some embodiments, the reset command is further used to reset the first count value to a first default value, and the reset command is further used to reset the third count value to a third default value;

[0051] The first control circuit is further configured to receive the first window signal, and output a first activation signal in a valid state when the first window signal is in an invalid state and the first count value is a first default value;

[0052] The refresh counting unit is further configured to output a second activation signal in a valid state when the third count value is a third default value;

[0053] The main control circuit also includes a third selector, which is connected to both the first control circuit and the refresh counting unit and is configured to receive the mode flag signal, and output the first activation signal as the activation indication signal when the mode flag signal represents an aging test mode; and output the second activation signal as the activation indication signal when the mode flag signal represents a normal mode.

[0054] In some embodiments, when the effective states of the first window signal and the activation indication signal are both at high levels, the first gating unit includes a first AND gate, the second gating unit includes a second AND gate; the first control transmission gate is an eighth AND gate;

[0055] When the valid state of the second window signal is a high level, the first logic unit includes a third AND gate;

[0056] When the second end pulse and the third end pulse are both positive pulses, the second logic unit includes a first OR gate.

[0057] In some embodiments, the selection end of the second selector receives the first window signal, the two input ends of the second selector receive the initial refresh command and the test precharge command respectively, and the output end of the second selector outputs the preselection signal;

[0058] The selection end of the third selector receives the mode mark signal, the two input ends of the third selector receive the preselection signal and the test clock signal respectively, and the output end of the third selector outputs the intermediate signal.

[0059] In some embodiments, the second count value includes an A-bit count sub-signal, and the second counter includes A second flip-flops and a first XOR gate;

[0060] The input terminal of the first second trigger is connected to the output terminal of the Ath second trigger; for the 2nd to A-1th triggers, the input terminal of each second trigger is connected to the positive phase output terminal of the previous second trigger; the first input terminal of the first XOR gate is connected to the output terminal of the A-1th trigger, the second input terminal of the first XOR gate is connected to the output terminal of the Ath trigger, and the output terminal of the first XOR gate is connected to the input terminal of the Ath second trigger;

[0061] The clock end of each second-hand trigger receives the test clock signal, and the output end of the i-th second-hand trigger outputs the i-th counting sub-signal, where i is a positive integer less than or equal to A; wherein the reset command is also used to reset the second counting value to a second default value, and the second default value is an all-1 state.

[0062] In some embodiments, the second frequency is an integral multiple of the first frequency; and the second decoding unit comprises:

[0063] a fourth decoder, configured to output a command to be selected when the second count value reaches a second threshold;

[0064] A sampling circuit is configured to perform cyclic counting of the pending commands; generate one second refresh command based on the first pending command; and, starting from the second pending command, output one second refresh command every time a preset number of pending commands are spaced;

[0065] Among them, for the test clock signal of the first frequency, the timing duration for the second count value to reach the first threshold from the second default value is the first timing duration; for the test clock signal of the second frequency, the timing duration for the second count value to reach the second threshold from the second default value is the second timing duration; the delayed refresh command is delayed by 2 clock cycles compared to the initial refresh command, and the clock cycle refers to the clock cycle of the test clock signal; the first timing duration + 2 / first frequency = the second timing duration + 2 / second frequency.

[0066] In some embodiments, when A=6 and the preset number is 2, the first decoding unit includes a first NAND gate, a second NAND gate, a first NOR gate, a second NOR gate, and a fourth AND gate; two input ends of the first NAND gate receive the 4th-bit counting sub-signal and the 3rd-bit counting sub-signal respectively, two input ends of the second NAND gate receive the 2nd-bit counting sub-signal and the 0th-bit counting sub-signal respectively, a first input end of the first NOR gate receives the 5th-bit counting sub-signal, a second input end of the first NOR gate receives the 1st-bit counting sub-signal, a first input end of the second NOR gate is connected to the output end of the first NAND gate, a second input end of the second NOR gate is connected to the output end of the second NAND gate, a first input end of the fourth AND gate is connected to the output end of the first NOR gate, a second input end of the fourth AND gate is connected to the output end of the second NOR gate, and the output end of the fourth AND gate outputs the first refresh command;

[0067] The fourth decoder comprises a fifth AND gate, a third NOR gate, and a sixth AND gate, wherein three input terminals of the fifth AND gate receive the 0th counting sub-signal, the 1st counting sub-signal, and the 3rd counting sub-signal respectively, and three input terminals of the third NOR gate receive the 5th counting sub-signal, the 4th counting sub-signal, and the 2nd counting sub-signal respectively, and the first input terminal of the sixth AND gate is connected to the output terminal of the fifth AND gate, the second input terminal of the sixth AND gate is connected to the output terminal of the third NOR gate, and the output terminal of the sixth AND gate outputs the command to be selected;

[0068] The selection circuit includes a third trigger, a delay unit, and a seventh AND gate. The clock end of the third trigger and the input end of the delay unit both receive the command to be selected. The input end of the third trigger is connected to its own inverting output end. The first input end of the seventh AND gate is connected to the output end of the third trigger. The second input end of the seventh AND gate is connected to the output end of the delay unit. The output end of the seventh AND gate outputs the second refresh command.

[0069] In a second aspect, an embodiment of the present disclosure provides a memory, which includes the memory as described in the first aspect.

[0070] The embodiments of the present disclosure provide a test circuit and a memory, which can generate test refresh commands under different test requirements, and have a small circuit area and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 A schematic diagram of a test circuit provided in an embodiment of the present disclosure;

[0072] Figure 2 A schematic diagram of the structure of a first command circuit provided in an embodiment of the present disclosure;

[0073] Figure 3 A schematic diagram of the specific structure of the first command circuit provided in an embodiment of the present disclosure;

[0074] Figure 4 A schematic diagram of the structure of another test circuit provided by an embodiment of the present disclosure;

[0075] Figure 5 A structural schematic diagram of another test circuit provided in an embodiment of the present disclosure;

[0076] Figure 6 A schematic diagram of the structure of a second command circuit provided in an embodiment of the present disclosure;

[0077] Figure 7 A schematic diagram of the specific structure of the second command circuit provided in the embodiment of the present disclosure;

[0078] Figure 8A partial structure diagram of a second command circuit provided in an embodiment of the present disclosure Figure 1 ;

[0079] Fig. 9 A partial structure diagram of a second command circuit provided in an embodiment of the present disclosure Figure 2 ;

[0080] Fig.10 A schematic diagram of a signal waveform change provided by an embodiment of the present disclosure;

[0081] Fig.11 A schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that shown or described.

[0083] The following are explanations of professional terms involved in the embodiments of the present disclosure and the corresponding relationships of some terms:

[0084] Dynamic Random Access Memory (DRAM);

[0085] Synchronous Dynamic Random Access Memory (SDRAM);

[0086] Double Data Rate SDRAM (DDR);

[0087] Fifth generation DDR (5th DDR, DDR5);

[0088] Low Power DDR (LPDDR);

[0089] Standby state (IDLE);

[0090] Burn in test;

[0091] millisecond (ms);

[0092] Microsecond (us)

[0093] Nanosecond (ns);

[0094] Megahertz (MHz)

[0095] Joint Electron Device Engineering Council (JEDEC)

[0096] Memory row address strobe precharge time (tRP);

[0097] Delay time for memory row address to be transferred to column address (tRCD);

[0098] Write recovery delay (tWR).

[0099] The minimum time interval (tCCD) between two read commands for performing two read operations consecutively.

[0100] MBIST is a memory built-in self-test technology, which is integrated inside the memory and tests the memory (using DRAM as an example) by generating read and write commands and address information. According to the DDR5 standard (DDR5JEDEC) provided by JEDEC, each memory cell must be refreshed within 32ms. At the same time, before and after the refresh command is executed, the DRAM must be in the standby state (IDLE), that is, before and after the refresh command is executed, the DRAM needs to execute the activation command ACT to be in the IDLE state.

[0101] In the aging (Burn in) test mode or the test that puts pressure on the retention time, the required refresh time will change. Specifically, during the Burn in test, there are a working phase (3ms) and a concentrated refresh phase (1ms), and the working phase and the concentrated refresh phase exist alternately. The DRAM is not refreshed in the working phase, but multiple refreshes are concentrated in the concentrated refresh phase. In this mode, the interval of the refresh command and the interval of the pre-charge command are fixed. Therefore, the duration of this phase can be mastered by counting the pre-charge commands in the working phase, and the duration of this phase can be mastered by counting the refresh commands in the concentrated refresh phase. Specifically, the interval of the pre-charge command is 268tck×5ns=1340ns, and the end of the working phase can be known by counting 2240 pre-charge commands; at the same time, the interval of the refresh command is tRFC, which is 315ns, and the end of the concentrated refresh phase can be known by counting 3200 refresh commands.

[0102] In addition, MBIST circuit also supports timing adjustment, and some command intervals (such as tRP, tRCD, tWR, tCCD, etc.) are no longer fixed at this time, so it is impossible to grasp the time by counting the precharge command and the refresh command. At the same time, in order to support the data retention time (Retention) test and the column priority read-write mode (Y FAST test), it is necessary to perform an average refresh operation, that is, insert a refresh command once every certain time, and the interval time needs to be adjustable. Finally, the generation of the refresh command is generated according to the test clock signal, and the frequency of the test clock signal also has a variety of values.

[0103] That is to say, for the MBIST circuit, the following rules need to be followed to generate refresh commands and activate commands:

[0104] (1) In the Burn-in test mode, 3200 refresh commands are generated in the centralized refresh phase, with a fixed refresh interval (e.g., 315 ns); no refresh commands are generated in the working phase;

[0105] (2) In normal mode, a refresh command is generated every certain time interval by averaging refresh, and the interval time is adjustable and fixed (for example, 1.95us, 3.9us, 7.8us);

[0106] (3) after the last refresh command in the concentrated refresh phase of the Burn-in mode and after each refresh command in the average refresh, an activation command is generated at a specified interval, so that the memory is in the IDLE state;

[0107] (4) The initial source of the refresh command needs to be generated based on a test clock signal with a variable frequency.

[0108] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0109] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a test circuit 10 provided in an embodiment of the present disclosure. The test circuit 10 can be applied to a memory to generate some operation commands involved in a BIST test. The memory can be DRAM, SDRAM, DDR, LPDDR, etc. The embodiment of the present disclosure only takes DDR5 as an example for illustration but does not constitute a specific limitation.

[0110] like Figure 1 As shown, the test circuit 10 includes:

[0111] The first command circuit 11 is configured to generate an initial refresh command based on the received test clock signal, and the time interval between two adjacent initial refresh commands is a first time length;

[0112] The selection circuit 12 is connected to the first command circuit 11 and configured to receive a test precharge command, an initial refresh command and a test clock signal; in a burn-in test mode, the test precharge command or the initial refresh command is output as an intermediate signal; in a normal mode, the test clock signal is output as an intermediate signal;

[0113] A first counter 13, connected to the selection circuit 12, configured to count the intermediate signal to generate a first count value;

[0114] The second command circuit 14 is connected to both the first command circuit 11 and the first counter 13, and is configured to receive a first count value and an initial refresh command. In the aging test mode, if the first count value represents the value of the initial refresh command generated by the memory in the centralized refresh phase, a test refresh command is generated based on each initial refresh command received; in the normal mode, after each first count value represents a preset time period, a test refresh command is generated using the first initial refresh command received.

[0115] Here, the test refresh command is the refresh command in MBIST, which is used to instruct the memory to perform a refresh operation.

[0116] Thus, (1) in the Burn-in test mode, the test precharge command or the initial refresh command is used as the timing basis to distinguish whether the memory is currently in the centralized refresh stage or the working stage; and when the memory is in the centralized refresh stage, each initial refresh command is used to generate a test refresh command, thereby achieving the aforementioned 3200 refreshes; (2) in the normal mode, the test clock signal is used as the timing basis, and each interval of a preset duration is used to generate a test refresh command using one initial refresh command, thereby achieving an average refresh operation. Thus, the same circuit can simultaneously support the generation requirements of refresh commands in the aging test mode and the normal mode, without the need to design two circuits separately, which can save circuit area and support a variety of test requirements.

[0117] It should be noted that, as mentioned above, for the Burn test mode, in the centralized refresh phase, the first counter 13 needs to count 3200 initial refresh commands; in the working phase, the first counter 13 needs to count 2240 test pre-charge commands. Therefore, in a specific embodiment, the first counter 13 can be embodied as a linear feedback shift register (LFSR) formed by 12 triggers and XOR gates, that is, the first count value can be expressed as CNT<11:0>, which can achieve 2 12 -1 = 4095 counting states, meeting the counting requirements.

[0118] In the embodiment of the present disclosure, the test pre-charge command, the initial refresh command, and the test refresh command are all embodied in the form of pulses; in other embodiments, they may also be embodied as other signal change characteristics.

[0119] In the embodiment of the present disclosure, the first duration is a fixed value, for example, 315ns; the preset duration is a non-fixed value (allowing the user to adjust), for example, 1.95us, 3.9us, 7.8us.

[0120] In addition, the frequency of the test clock signal has multiple values. Specifically, the test circuit 10 also receives a frequency indication signal and generates a corresponding test clock signal according to the frequency indication signal. In other words, the frequency indication signal is used to adjust the frequency value of the test clock signal transmitted to the first command circuit 11.

[0121] That is to say, the first command circuit 11 needs to generate an initial refresh command with a fixed time interval of the first time length according to the test clock signal with a variable frequency.

[0122] Therefore, see Figure 2 , the first command circuit 11 comprises:

[0123] The second counter 111 is configured to count the received test clock signal and output a second count value;

[0124] The first decoding unit 112 is connected to the second counter 111 and configured to output a first refresh command when the second count value reaches a first threshold;

[0125] The second decoding unit 113 is connected to the second counter 111 and configured to output a second refresh command if the second count value reaches the second threshold for the first time; and after the second count value reaches the second threshold for the first time, if the second count value reaches the second threshold for a preset number of times, output a second refresh command; the preset number is a positive integer greater than 1;

[0126] The first selector 114 is connected to the first decoding unit 112 and the second decoding unit 113, and is configured to receive a frequency indication signal, and output the first refresh command as an initial refresh command when the frequency indication signal represents that the frequency of the test clock signal is a first frequency; and output the second refresh command as an initial refresh command when the frequency indication signal represents that the frequency of the test clock signal is a second frequency.

[0127] In this way, when the test clock signal is of the first frequency, a first refresh command is generated by the first decoding unit 112, and the time interval of the first refresh command is the aforementioned first duration; when the test clock signal is of the second frequency, a second refresh command is generated by the second decoding unit 113, and the time interval of the second refresh command is also the aforementioned first duration; the first selector 114 selects the first refresh command / the second refresh command as the initial refresh command according to the frequency of the test clock signal, so that the time interval of the initial refresh command is fixed to the first duration.

[0128] It should be understood that if the frequency of the test clock signal can also be a third frequency, a fourth frequency..., it can be analogous to the first decoding unit 112 or the second decoding unit 113 or any conventional decoding unit to design a corresponding third decoding unit, a fourth decoding unit... and select the required initial refresh command through the first selector 114.

[0129] Correspondingly, such as Figure 2 As shown, the second frequency is an integral multiple of the first frequency; the second decoding unit 113 includes:

[0130] The fourth decoder 1131 is configured to output one pending command when the second count value reaches a second threshold value; the sampling circuit 1132 is configured to perform cyclic counting on the pending commands; generate one second refresh command based on the first pending command, and, starting from the second pending command, output one second refresh command every time a preset number of pending commands are separated.

[0131] In this way, no matter how the frequency of the test clock signal changes, the number of counts performed by the second counter 111 in one counting cycle is fixed, and the second counter 111 forms a counting cycle from a certain counting state (e.g., all 1s) to the next same counting state (e.g., all 1s). In this way, for a test clock signal of a first frequency, one first refresh command is generated in each counting cycle; for a test clock signal of a second frequency, one second refresh command is generated only after a preset number of counting cycles (preset number = second frequency / first frequency).

[0132] In addition, for the test clock signal of the first frequency, the timing duration for the second count value to reach the first threshold from the second default value is the first timing duration; for the test clock signal of the second frequency, the timing duration for the second count value to reach the second threshold from the second default value is the second timing duration, and the second default value is the value after the second count value is reset; at the same time, the delayed refresh command is delayed by 2 clock cycles compared to the initial refresh command, and the clock cycle refers to the clock cycle of the test clock signal; the first timing duration + 2 / first frequency = the second timing duration + 2×2 / second frequency. The reason for this is that after each reset operation of the first count value, regardless of the test clock signal of the first frequency or the second frequency, the time point at which the first test refresh command is generated must be the same, that is, a certain amount of time needs to be reserved before the refresh operation to perform the precharge operation (tRP) to meet the JEDEC regulations.

[0133] In a specific embodiment, see Figure 3 , the second count value includes an A-bit count sub-signal ( Figure 3 Take A=6 as an example) CNT_R <a-1:0>, the second counter 111 includes A second flip-flops 201 and a first XOR gate 202; the input end of the 1st second flip-flop 201 is connected to the output end of the Ath second flip-flop 201; for the 2nd to A-1st flip-flops, the input end of each second flip-flop 201 is connected to the positive phase output end of the previous second flip-flop 201; the first input end of the first XOR gate 202 is connected to the output end of the A-1th flip-flop, the second input end of the first XOR gate 202 is connected to the output end of the Ath flip-flop, and the output end of the first XOR gate 202 is connected to the input end of the Ath second flip-flop 201; the clock end of each second flip-flop 201 receives the test clock signal BIST_CLK, and the output end of the i-th second flip-flop 201 outputs the i-th counting sub-signal CNT_R <i-1>, i is a positive integer less than or equal to A; wherein the reset command REF_RST is also used to reset the second count value to a second default value, and the second default value is an all-1 state.

[0134] It should be noted that the following describes the specific structure of the first command circuit 11 by taking the first frequency as 200 MHz (clock cycle as 5 ns), the second frequency as 400 MHz (clock cycle as 2.5 ns), the preset number as 2, the first duration as 315 nanoseconds, and the second default value as all-1 state as an example.

[0135] In this scenario, if Figure 3 As shown, the second counter 111 includes 6 second flip-flops 201 and a first XOR gate 202; the second count value includes a 6-bit sub-signal CNT_R<5:0>. In this way, there are a total of 63 counts in each counting cycle. In addition, after resetting the second counter 111, the second count value CNT_R<5:0>=111111 (all 1 state).

[0136] The first decoding unit 112 includes a first NAND gate 211, a second NAND gate 212, a first NOR gate 214, a second NOR gate 215, and a fourth AND gate 216. The two input terminals of the first NAND gate 211 receive the fourth counting sub-signal CNT_R. <4> and the 3rd bit counting sub-signal CNT_R <3> The two input terminals of the second NAND gate 212 receive the second counting sub-signal CNT_R <3> and the 0th bit counting sub-signal CNT_R <0> , the first input terminal of the first NOR gate 214 receives the fifth counting sub-signal CNT_R <5> The second input terminal of the first NOR gate 214 receives the first bit counting sub-signal CNT_R <1> , a first input terminal of the second NOR gate 215 is connected to the output terminal of the first NAND gate 211, a second input terminal of the second NOR gate 215 is connected to the output terminal of the second NAND gate 212, a first input terminal of the fourth AND gate 216 is connected to the output terminal of the first NOR gate 214, a second input terminal of the fourth AND gate 216 is connected to the output terminal of the second NOR gate 215, and the output terminal of the fourth AND gate 216 outputs the first refresh command REF_A.

[0137] In brief, please refer to Table 1, the first decoding unit 112 decodes the second count value CNT<5:0>, and generates a first refresh command REF_A when the second count value CNT<5:0>=011101 (the third count state other than the second default value); that is, the first first refresh command REF_A is generated after a delay of 3 tcks (clock cycles of the test clock signal) after reset, and there will be a delay of 2 tcks when the test refresh command is generated later (please refer to the subsequent description for details). Therefore, for the test clock signal BIST_CLK of the first frequency (clock cycle is 5ns), after reset, the first test refresh command will be generated after 5×5=25ns; the interval between the first refresh command REF_A generated later and the previous first refresh command REF_A is one round of counting cycle, that is, 63×5=315ns.

[0138] Table 1

[0139]

[0140] like Figure 3 As shown, for the second decoding unit 113, the fourth decoder 1131 includes a fifth AND gate 221 ( Figure 3 The third NOR gate 222 and the sixth AND gate 223 ( Figure 3 The third input terminal of the fifth AND gate 221 receives the 0th bit counting sub-signal CNT_R <0> , the first bit counting sub-signal CNT_R <1> and the 3rd bit counting sub-signal CNT_R <3> , the three input terminals of the third NOR gate 222 receive the 5th counting sub-signal, the 4th counting sub-signal and the 2nd counting sub-signal respectively, the first input terminal of the sixth AND gate 223 is connected to the output terminal of the fifth AND gate 221, the second input terminal of the sixth AND gate 223 is connected to the output terminal of the third NOR gate 222, and the output terminal of the sixth AND gate 223 outputs the command to be selected REF_b; the selection circuit 1132 includes a third trigger 231, a delay unit 232, and a seventh AND gate 233, the clock terminal of the third trigger 231 and the input terminal of the delay unit 232 both receive the command to be selected REF_b, the input terminal of the third trigger 231 is connected to its own inverting output terminal, the first input terminal of the seventh AND gate 233 is connected to the output terminal of the third trigger 231, the second input terminal of the seventh AND gate 233 is connected to the output terminal of the delay unit 232, and the output terminal of the seventh AND gate 233 outputs the second refresh command REF_B.

[0141] Similarly, see Table 1, the fourth decoder 1131 decodes the second count value CNT<5:0>, and generates a pending command REF_b when the second count value CNT<5:0>=001011 (the 8th count state other than the default value), and the first pending command REF_b fixedly generates the first second refresh command REF_B, that is, the first second refresh command REF_B is generated after a delay of 8 tcks, and there will be a delay of 2 tcks when the test refresh command is generated later (see the subsequent description for details); therefore, after reset, the first test refresh command will be generated after 10×2.5=25ns. That is to say, for the test clock signal BIST_CLK of the second frequency (clock period is 2.5ns), the test refresh command will be generated after 10×2.5=25ns.

[0142] The interval between the subsequently generated pending command REF_b and the previous pending command REF_b is one counting cycle, that is, 63×2.5=157.5ns; at the same time, the first pending command REF_b will be output as the second refresh command REF_B, and thereafter, the next pending command REF_b in every pending command REF_b will be output as the second refresh command REF_B, and at this time, the interval between the second refresh command REF_B is still 315ns.

[0143] In this way, no matter the frequency of the test clock signal BIST_CLK is the first frequency or the second frequency, the first test refresh command always appears 25ns after reset (meeting the tRP requirement), and the interval between the subsequent initial refresh command REF and the previous initial refresh command REF is always 315ns.

[0144] As mentioned above, in the aging test mode, the memory is alternately in the concentrated refresh stage and the working stage. In the concentrated refresh stage, the initial refresh command REF is used as the timing basis to grasp the working progress; in the working stage, the test pre-charge command is used as the timing basis to grasp the working progress; in the normal mode, the memory needs to use the test clock signal BIST_CLK as the timing basis to achieve subsequent average refresh operation.

[0145] Based on this, Figure 4 As shown, the selection circuit 12 includes:

[0146] The second selector 121 is configured to output the received initial refresh command REF as a preselection signal if the memory is in the centralized refresh phase; and to output the received test precharge command BIST_PRE as a preselection signal if the memory is in the working phase;

[0147] The third selector 122 is connected to the second selector 121 and configured to receive the preselected signal and the test clock signal BIST_CLK, and outputs the preselected signal as the intermediate signal REF_CLK in the aging test mode; and outputs the test clock signal BIST_CLK as the intermediate signal REF_CLK in the normal mode.

[0148] Specifically, see Figure 4 , the second selector 121 is also used to receive the first window signal REF_WINDOW, which is used to indicate that the memory is in the concentrated refresh stage or the working stage in the aging mode; the third selector 122 is also used to receive the mode flag signal, which is used to indicate that the memory is in the aging test mode or the normal mode. That is to say, in some embodiments, the selection end of the second selector 121 receives the first window signal REF_WINDOW, the two input ends of the second selector 121 respectively receive the initial refresh command REF and the test precharge command BIST_PRE, and the output end of the second selector 121 outputs the preselection signal; the selection end of the third selector 122 receives the mode flag signal, the two input ends of the third selector 122 respectively receive the preselection signal and the test clock signal BIST_CLK, and the output end of the third selector 122 outputs the intermediate signal REF_CLK. Here, the second selector 121 and the third selector 122 can both be implemented using a two-to-one data selector.

[0149] As mentioned above, for the aging test mode, it is necessary to generate a test activation command at a specified time (315ns) after the concentrated refresh phase ends, so that the memory is in the IDLE state; in the normal mode, it is necessary to generate a test activation command at a specified time (315ns) after each test refresh command, so that the memory is in the IDLE state. In this way, since the interval time between the test refresh command and the test activation command is completely consistent with the interval time between two consecutive initial refresh commands REF, this point can be used to design the generation mechanism of the test activation command.

[0150] In some embodiments, Figure 5 As shown, the second command circuit 14 is further configured to generate a test activation command BIST_ACT based on the received first initial refresh command REF in the aging test mode if the first count value represents the end of the concentrated refresh phase; or, in the normal mode, generate a test activation command BIST_ACT based on the received second initial refresh command REF after each first count value representation has passed a preset time.

[0151] Thus, for the aging test mode, after executing the last test refresh command BIST_REF (generated based on an initial refresh command REF) of the centralized refresh phase, the next initial refresh command REF will be used to generate a test activation command BIST_ACT, thereby generating a test activation command BIST_ACT 315ns after the centralized refresh phase ends. For the normal mode, after each first count value represents a preset time, the first initial refresh command REF received subsequently will be used to generate a test refresh command BIST_REF, and the second initial refresh command REF received subsequently will be used to generate a test activation command BIST_ACT, so that a test activation command BIST_ACT will also be generated 315ns after the test refresh command BIST_REF, meeting the timing requirements.

[0152] In some embodiments, Figure 6 As shown, the second command circuit 14 includes:

[0153] The main control circuit 141 is configured to receive an initial refresh command REF, a test precharge command BIST_PRE and a first count value, generate and output a first window signal REF_WINDOW and an activation indication signal REF_ACT; wherein, in the stage where the memory allows a refresh operation to be performed, the first window signal REF_WINDOW is in a valid state; in the stage where the memory allows an activation operation to be performed, the activation indication signal REF_ACT is in a valid state;

[0154] The sampling circuit 142 is configured to sample the initial refresh command REF based on the test clock signal BIST_CLK to generate a delayed refresh command; the sampled initial refresh command REF and the delayed refresh command generated by the sampling are separated by 2 clock cycles (2tck), where the clock cycle refers to the clock cycle of the test clock signal BIST_CLK;

[0155] The first gating unit 143 is connected to both the main control circuit 141 and the sampling circuit 142, and is configured to generate a test refresh command BIST_REF using a delayed refresh command only when the first window signal REF_WINDOW is in a valid state;

[0156] The second gating unit 144 is connected to both the main control circuit 141 and the sampling circuit 142 , and is configured to generate a test refresh command BIST_REF using a delayed refresh command only when the activation indication signal REF_ACT is in a valid state.

[0157] Here, the function of the sampling circuit 142 is to delay the corresponding initial refresh command REF to generate a delayed refresh command to match the delay generated when the main control circuit 141 performs logic processing. Figure 7 As shown, the sampling circuit 142 includes a fourth trigger 1421 and a fifth trigger 1422, the input end of the fourth trigger 1421 receives the initial refresh command REF, the input end of the fifth trigger 1422 is connected to the output end of the fourth trigger 1421, the clock ends of the fourth trigger 1421 and the fifth trigger 1422 both receive the test clock signal BIST_CLK, and the fifth trigger 1422 outputs a delayed refresh command. In this way, the sampling circuit 142 delays the initial refresh command REF by 2 clock cycles (tck) in total, which not only matches the processing delay of the main control circuit 141, but also meets the tRP time requirement.

[0158] In this way, the stage in which the refresh operation is allowed to be performed is identified by the first window signal REF_WINDOW, and the initial refresh command REF in this stage will be used to generate the test refresh command BIST_REF; the stage in which the activation operation is allowed to be performed is identified by the activation indication signal REF_ACT, and the initial refresh command REF in this stage will be used to generate the test activation command BIST_ACT.

[0159] The changing principle of the first window signal REF_WINDOW is described below.

[0160] In some embodiments, Figure 7 As shown, the main control circuit 141 includes:

[0161] The first control circuit 1411 is connected to the first counter 13 and is configured to decode the first count value in the aging test mode, and generate a first switching pulse when the decoding result indicates that the concentrated refresh phase is over or the working phase is over;

[0162] The signal generating circuit 1412 is connected to the first control circuit 1411 and configured to generate a first window signal REF_WINDOW; in the aging test mode, the state of the first window signal REF_WINDOW is changed once each time a first switching pulse is received.

[0163] In this way, in the aging test mode, the state of the first window signal REF_WINDOW is switched by the first switching pulse to indicate that the memory is currently in the centralized refresh phase or the working phase.

[0164] It should be noted that, in the aging test mode, when the first window signal REF_WINDOW is valid, it indicates that the memory is in the centralized refresh stage, and when the first window signal REF_WINDOW is invalid, it indicates that the memory is in the working stage. In this way, for the centralized refresh stage, each time the initial refresh command REF passes the third threshold (for example, 3200 count states), it means that 1ms has passed, thereby generating 1 switching pulse, adjusting the first window signal REF_WINDOW to invalid, thereby entering the working stage; in the working stage, each time the test pre-charge command BIST_PRE passes the fourth threshold (for example, 2240 count states) (the time interval between each 2 test pre-charge commands BIST_PRE is 268tck×5ns=1340ns), it means that 3ms has passed, thereby generating 1 switching pulse again, adjusting the first window signal REF_WINDOW to valid, thereby entering the centralized refresh stage.

[0165] Based on this, in some embodiments, the first control circuit 1411 is specifically configured to receive a first window signal REF_WINDOW; when the first window signal REF_WINDOW is in a valid state, if the first count value reaches a third threshold value, a first switching pulse is generated; or, when the first window signal REF_WINDOW is in an invalid state, if the first count value reaches a fourth threshold value, a first switching pulse is generated.

[0166] Meanwhile, in the normal mode, a test refresh command and a test activation command need to be generated only after the decoding result of the first count value indicates that a preset time has passed, that is, the state of the first window signal REF_WINDOW may be switched.

[0167] In some embodiments, Figure 7 As shown, the main control circuit 141 also includes:

[0168] The second control circuit 1413 is connected to the first counter 13 and configured to decode the first count value in the normal mode; when the decoding result indicates that a preset time has passed, when one test precharge command BIST_PRE is received or two initial refresh commands REF are received, one second switching pulse is generated;

[0169] The signal generating circuit 1412 is also connected to the second control circuit 1413 and is configured to change the state of the first window signal REF_WINDOW once each time it receives a second switching pulse in the normal mode.

[0170] In this way, in normal mode, at every preset time interval, based on the received test pre-charge command BIST_PRE (the next refresh or activation operation can be performed only after the pre-charge operation is completed), the first window signal REF_WINDOW is adjusted to valid, that is, the refresh operation is allowed; after receiving two initial refresh commands REF, the first window signal REF_WINDOW is adjusted to an invalid state, that is, the refresh operation is not allowed.

[0171] In some embodiments, Figure 7 As shown, the second control circuit 1413 includes:

[0172] The third decoding unit 31 is configured to decode the first count value, and generate a decoding pulse if the decoding result indicates that a preset time has passed;

[0173] The latch unit 32 is connected to the third decoding unit 31, and is configured to receive a decoding pulse and a test activation command BIST_ACT, and generate and output a second window signal REF_WINDOW0; wherein, each time a decoding pulse is received, the second window signal REF_WINDOW0 is controlled to change from an invalid state to a valid state, and each time a test activation command BIST_ACT is received, the second window signal REF_WINDOW0 is controlled to change from a valid state to an invalid state;

[0174] The first logic unit 33 is connected to the latch unit 32 and is configured to generate a second end pulse PRE_END by receiving the first test precharge command BIST_PRE if the second window signal REF_WINDOW0 is in a valid state;

[0175] The refresh counting unit 34 is connected to the latch unit 32 and the first command generating circuit 11, and is configured to generate a third end pulse REF_END if two initial refresh commands REF are received;

[0176] The second logic unit 35 is configured to generate and output a second switching pulse whenever receiving a second end pulse PRE_END or a third end pulse REF_END.

[0177] It should be noted that the second window signal REF_WINDOW0 is meaningful only in normal mode, and its function is to generate the second window signal REF_WINDOW0 based on a fixed interval (second duration) so that the state of the first window signal REF_WINDOW is switched within the second window signal REF_WINDOW0 in normal mode.

[0178] exist Figure 7 In the embodiment, when the first window signal REF_WINDOW and the activation indication signal REF_ACT are both at high levels, the first gating unit 143 includes a first AND gate, and the second gating unit 144 includes a second AND gate; when the second window signal REF_WINDOW0 is at a high level, the first logic unit 34 includes a third AND gate; when the second end pulse PRE_END and the third end pulse REF_END are both positive pulses, the second logic unit 35 includes a first OR gate. However, this does not constitute a corresponding limitation.

[0179] It should be noted that the latch unit 32 can at least be implemented using an SR latch; according to the specific control logic adopted, corresponding logic gates such as an AND gate, an OR gate, a NOT gate, etc. can also be introduced.

[0180] In this way, the working process of the normal mode is as follows: (1) If the decoding result of the second count value indicates that the preset time has passed, the latch unit 32 will adjust the second window signal REF_WINDOW0 to be valid; (2) Thereafter, if the test pre-charge command BIST_PRE is received, the first logic unit 33 will output a second switching pulse to adjust the first window signal REF_WINDOW to be valid, that is, to allow the refresh operation to be performed, so the first initial refresh command REF received next will be used to generate a test refresh command BIST_REF; (3) Thereafter, after receiving the second initial refresh command REF, the refresh count unit 34 outputs a third end pulse REF_END and generates a second switching pulse again, thereby causing the second window signal REF_WINDOW to be adjusted to be invalid, so that the second initial refresh command REF is used to generate the test activation command BIST_ACT, and the generated test activation command BIST_ACT adjusts the second window signal REF_WINDOW0 to be invalid.

[0181] In some embodiments, see Figure 8 The refresh counting unit 34 includes: a third counter 341, configured to count the initial refresh command REF and generate a third count value; a first decoder 342, connected to the third counter, configured to generate a third end pulse REF_END when the third count value is 2. Exemplarily, the third counter 341 may include an asynchronous counter composed of two flip-flops.

[0182] In particular, see Fig. 9 The test circuit 10 also includes a first control transmission gate 151, and the output end of the first control transmission gate 151 is connected to the input end of the third counter 341; wherein the first control transmission gate 151 is configured to receive the second window signal REF_WINDOW0 and the initial refresh command REF; when the second window signal REF_WINDOW0 is in a valid state, the initial refresh command is transmitted to the third counter 341; when the second window signal is in an invalid state, the initial refresh command is shielded to keep the third count value unchanged.

[0183] That is, the third counter 341 will count only when the second window signal REF_WINDOW0 is valid. Exemplarily, if the valid state of the second window signal REF_WINDOW0 is high, the first control transmission gate 151 can be implemented by an AND gate, but this does not constitute a relevant limitation.

[0184] It is worth noting that in normal mode, only at intervals of a preset duration will two initial refresh commands REF be used to generate one test refresh command BIST_REF and one test activation command BIST_ACT; during the duration of the "preset duration", the initial refresh command REF is actually not needed. Therefore, during this period, the initial refresh command REF does not need to be generated, thereby reducing power consumption.

[0185] Here, if the valid state of the second window signal REF_WINDOW0 refers to a high level, the first control transmission gate 151 can be implemented by an eighth AND gate.

[0186] As mentioned above, the preset duration has multiple values. Figure 7 As shown, the third decoding unit 31 includes:

[0187] The second decoder 311 is configured to receive the first count value, and generate a first pulse CNT_780 when the first count value reaches a fifth threshold;

[0188] The third decoder 312 is configured to receive the first count value, and generate a second pulse CNT_1560 when the first count value reaches a sixth threshold;

[0189] a fourth selector 313 configured to receive an interval selection signal, and generate a decoding pulse using the first pulse or the second pulse based on the interval selection signal;

[0190] The frequency of the interval selection signal and the test clock signal BIST_CLK jointly determine the value of the preset duration.

[0191] Exemplarily, it is assumed that the fifth threshold value may be the second count value corresponding to the 780th count state, and the sixth threshold value may be the second count value corresponding to the 1560th count state. When the frequency of the test clock signal BIST_CLK is 400MHz (clock cycle is 2.5ns), the time interval between each two decoding pulses is 1.95us or 3.9us (determined by the interval selection signal); when the frequency of the test clock signal BIST_CLK may be 200MHz (clock cycle is 5ns), the time interval between each two decoding pulses is 3.9us or 7.8us (determined by the interval selection signal). The interval selection signal can be adjusted as required.

[0192] In some embodiments, Figure 7 As shown, the signal generating circuit 1412 includes a fifth selector 36 and a first trigger 37; the fifth selector 36 is configured to receive a mode flag signal, and when the mode flag signal indicates an aging test mode, use a first switching pulse to generate a reset command REF_RST; when the mode flag signal indicates a normal mode, use a second switching pulse to generate a reset command REF_RST;

[0193] The clock terminal of the first trigger 37 receives the reset command REF_RST, the input terminal of the first trigger 37 is connected to the clock terminal of the first trigger 37 and its own inverting output terminal, and the output terminal of the first trigger 37 outputs the first window signal REF_WINDOW.

[0194] In some embodiments, the reset command REF_RST is further used to reset the first count value to a first default value, and the reset command REF_RST is further used to reset the third count value to a third default value;

[0195] The first control circuit 1411 is further configured to receive the first window signal REF_WINDOW, and output a first activation signal REF_ACT0 in a valid state when the first window signal REF_WINDOW is in an invalid state and the first count value is a first default value;

[0196] The refresh counting unit 34 is further configured to output a second activation signal REF_ACT1 in a valid state when the third counting value is a third default value;

[0197] The main control circuit 141 also includes a third selector 122, which is connected to the first control circuit and the refresh counting unit, and is configured to receive a mode flag signal, and when the mode flag signal represents an aging test mode, output the first activation signal REF_ACT0 as an activation indication signal REF_ACT; when the mode flag signal represents a normal mode, output the second activation signal REF_ACT1 as an activation indication signal REF_ACT.

[0198] Here, the first default value may be an all-1 state, the second default value may be an all-1 state, and the third default value may be an all-0 state.

[0199] It should be noted that the first control circuit 1411 also has a decoding unit for the first default value (for example, an all-1 decoder); the refresh counting unit 34 also has a decoding unit for the third default value (for example, Figure 8 The all-0 decoder 343 in ).

[0200] Thus, each time the first window signal REF_WINDOW becomes invalid (ie, the centralized refresh phase ends), the activation indication signal will be briefly changed to a valid state, so that the next initial refresh command REF will be used to generate the test activation command BIST_ACT.

[0201] See also Fig.10 , the following provides a specific signal waveform for the scenario in normal mode, with a refresh interval of 3.9us and a clock period of the test clock signal BIST_CLK of 2.5ns to further illustrate the working principle of the test circuit.

[0202] like Fig.10 As shown, 3.9us after the last refresh operation, the second pulse CNT_1560 generates 1 pulse, and at this time the second window signal REF_WINDOW0 switches to a valid state; after receiving the next test pre-charge command BIST_PRE, a second switching pulse is generated to switch the first window signal REF_WINDOW to a valid state; after a delay of 8 tck times, the first command circuit 11 generates 3 selected commands REF_b, and the third selected command REF_b generates a second switching pulse again to switch the first window signal REF_WINDOW to an invalid state, and at the same time switches the activation indication signal REF_ACT to a valid state. At the same time, the first and third selected commands REF_b subsequently generate initial refresh commands REF respectively, and the second selected command REF_b is lost; the first initial refresh command REF generates the first delayed refresh command after delay, which generates the test refresh command BIST_REF after a logical operation with the first window signal REF_WINDOW; the second initial refresh command REF generates the second delayed refresh command after delay, which generates the test activation command BIST_ACT after a logical operation with the activation indication signal REF_ACT, and the test activation command BIST_ACT is also used to switch the second window signal REF_WINDOW0 to an invalid state.

[0203] In summary, the test circuit 10 provided by the present disclosure can be applied to the built-in self-test MBIST module, which not only can not support the centralized refresh mechanism under the Burn in test mode, but also can support the average refresh mechanism of adjustable interval (currently supported time interval is 1.95us, 3.9us, 7.8us) under the normal mode, i.e. insert a refresh command at regular intervals. Compared with centralized refresh, average refresh can make the retention time of each row consistent, make test more accurate, and can also avoid the problem of unstable power supply caused by continuous refresh in addition. Concrete, normal mode and aging test mode reuse the first counter (for example 12 LFSR). In normal test, it is necessary to select test clock signal BIST_CLK as the counting source of LFSR, decode the 780th state and the 1560th state respectively, and cooperate with state decoding to realize that the refresh interval is the average refresh operation of 1.95 / 3.9 / 7.8us simultaneously. When the system clock signal BIST_CLK is selected as 5ns, the design of the test refresh command that meets the tRP timing requirements generated by the second counter (such as a 6-bit LFSR) and the related decoding circuit remains unchanged. It only needs to change the third end pulse REF_END, so that the third counter counts twice to generate REF_END, and uses the decoded 0 state to generate the test activation command BIST_ACT to meet the tRFC requirements. When BIST_CLK is selected as 2.5ns, tRP can be achieved by decoding the 9th state of the second counter, and the first initial refresh command REF generated in the subsequent counting cycle is used as BIST_REF, ignoring the second initial refresh command REF, and selecting the third initial refresh command REF as BIST_ACT can achieve tRFC (315ns).

[0204] The disclosed embodiments relate to a memory built-in self-test circuit in an integrated circuit design, and more particularly to the generation and insertion of refresh commands when performing MBIST operations on a DDR5 chip. The design includes the generation of refresh commands under various conditions, and is applied to the generation and insertion of refresh commands when a DDR5 chip is tested by an ATE, but is not limited to this scope. Other command planning and generation circuits and counting timing control circuits may adopt this design.

[0205] In another embodiment of the present disclosure, see Fig.11 , which shows a schematic diagram of the structure of a memory 50 provided by an embodiment of the present disclosure. Fig.11 As shown, the memory 50 at least includes the aforementioned test circuit 10 .

[0206] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the existence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A test circuit, characterized in that: Applied to a memory, the test circuit comprises: A first command circuit is configured to generate an initial refresh command based on a received test clock signal, and a time interval between two adjacent initial refresh commands is a first time length; a selection circuit connected to the first command circuit and configured to receive a test precharge command, the initial refresh command and the test clock signal; in an aging test mode, output the test precharge command or the initial refresh command as an intermediate signal; in a normal mode, output the test clock signal as the intermediate signal; A first counter, connected to the selection circuit, configured to count the intermediate signal to generate a first count value; The second command circuit is connected to both the first command circuit and the first counter, and is configured to receive the first count value and the initial refresh command. In the aging test mode, if the first count value represents the value of the initial refresh command generated by the memory in the concentrated refresh phase, then one test refresh command is generated based on each received initial refresh command; in the normal mode, after each time the first count value represents a preset time period, one test refresh command is generated using the first received initial refresh command.

2. The test circuit according to claim 1, characterized in that: The first duration is a fixed value; the first command circuit includes: a second counter configured to count the received test clock signal and output a second count value; a first decoding unit connected to the second counter and configured to output a first refresh command when the second count value reaches a first threshold; a second decoding unit connected to the second counter and configured to output a second refresh command if the second count value reaches the second threshold for the first time; and, after the second count value reaches the second threshold for the first time, output a second refresh command if the second count value reaches the second threshold a preset number of times; A first selector is connected to the first decoding unit and the second decoding unit, and is configured to receive a frequency indication signal, and output the first refresh command as the initial refresh command when the frequency indication signal indicates that the frequency of the test clock signal is a first frequency; and output the second refresh command as the initial refresh command when the frequency indication signal indicates that the frequency of the test clock signal is a second frequency.

3. The test circuit according to claim 2, characterized in that: The memory is alternately in the centralized refresh phase and the working phase in the aging test mode, and the selection circuit includes: a second selector configured to output the received initial refresh command as a preselection signal if the memory is in the centralized refresh phase; and to output the received test precharge command as the preselection signal if the memory is in the working phase; The third selector is connected to the second selector and configured to receive the preselected signal and the test clock signal, and output the preselected signal as the intermediate signal in the aging test mode; and output the test clock signal as the intermediate signal in the normal mode.

4. The test circuit according to claim 3, characterized in that: The second command circuit is further configured to generate a test activation command based on the first received initial refresh command in the aging test mode if the first count value indicates that the concentrated refresh phase is over; Alternatively, in the normal mode, after each time the first count value represents a lapse of a preset time period, one test activation command is generated based on the second received initial refresh command.

5. The test circuit according to claim 4, characterized in that: The second command circuit comprises: A main control circuit is configured to receive the initial refresh command, the test precharge command and the first count value, generate and output a first window signal and an activation indication signal; wherein, in the stage where the memory allows a refresh operation to be performed, the first window signal is in a valid state; and in the stage where the memory allows an activation operation to be performed, the activation indication signal is in a valid state; a sampling circuit configured to sample the initial refresh command twice in succession based on the test clock signal to generate a delayed refresh command; A first gating unit is connected to both the main control circuit and the sampling circuit, and is configured to generate one test refresh command using one delayed refresh command only when the first window signal is in a valid state; The second gating unit is connected to both the main control circuit and the sampling circuit, and is configured to generate a test refresh command using one delayed refresh command only when the activation indication signal is in a valid state.

6. The test circuit according to claim 5, characterized in that: The main control circuit comprises: A first control circuit is connected to the first counter and configured to decode the first count value in an aging test mode, and generate a first switching pulse when the decoding result indicates that the centralized refresh phase is ended or the working phase is ended; The signal generating circuit is connected to the first control circuit and configured to generate the first window signal; in the aging test mode, the state of the first window signal is changed once each time the first switching pulse is received.

7. The test circuit according to claim 6, characterized in that: The first control circuit is specifically configured to receive the first window signal; when the first window signal is in a valid state, if the first count value reaches a third threshold, generate one first switching pulse; or when the first window signal is in an invalid state, if the first count value reaches a fourth threshold, generate one first switching pulse; Wherein, in the aging test mode, when the first window signal is valid, it indicates that the memory is in a centralized refresh phase, and when the first window signal is invalid, it indicates that the memory is in a working phase.

8. The test circuit according to claim 6, characterized in that: The main control circuit also includes: a second control circuit connected to the first counter and configured to decode the first count value in a normal mode; and generate a second switching pulse when one of the test precharge commands is received or two of the initial refresh commands are received, when the decoding result indicates that the preset time has passed; The signal generating circuit is also connected to the second control circuit and is configured to change the state of the first window signal once each time the second switching pulse is received in a normal mode.

9. The test circuit according to claim 8, characterized in that: The second control circuit comprises: A third decoding unit is configured to decode the first count value, and generate a decoding pulse if the decoding result indicates that the preset time length has passed; a latch unit connected to the third decoding unit, configured to receive the decoding pulse and the test activation command, generate and output a second window signal; wherein, each time the decoding pulse is received, the second window signal is controlled to change from an invalid state to a valid state, and each time the test activation command is received, the second window signal is controlled to change from a valid state to an invalid state; a first logic unit connected to the latch unit and configured to generate a second end pulse by receiving the first test precharge command if the second window signal is in a valid state; a refresh counting unit connected to the latch unit and the first command generating circuit, and configured to generate a third end pulse if two initial refresh commands are received when the second window signal is in a valid state; The second logic unit is configured to generate and output one of the second switching pulses whenever one of the second end pulses or one of the third end pulses is received.

10. The test circuit according to claim 9, characterized in that: The preset duration has multiple values; the third decoding unit includes: A second decoder is configured to receive the first count value, and generate a first pulse when the first count value reaches a fifth threshold; A third decoder is configured to receive the first count value, and generate a second pulse when the first count value reaches a sixth threshold; a fourth selector configured to receive an interval selection signal, and generate the decoding pulse using the first pulse or the second pulse based on the interval selection signal; The frequency of the interval selection signal and the test clock signal jointly determine the value of the preset duration.

11. The test circuit according to claim 9, characterized in that: The refresh counting unit comprises: A third counter is configured to count the received initial refresh command to generate a third count value; The first decoder is connected to the third counter, and is configured to generate one third end pulse when the third count value is 2.

12. The test circuit according to claim 11, characterized in that: The memory also includes a first control input gate, and the output end of the first control transmission gate is connected to the input end of the third counter; wherein the first control transmission gate is configured to receive the second window signal and the initial refresh command; when the second window signal is in a valid state, the initial refresh command is transmitted to the third counter; when the second window signal is in an invalid state, the initial refresh command is shielded so that the third count value remains unchanged.

13. The test circuit according to claim 11, characterized in that: The signal generating circuit includes a fifth selector and a first trigger; a fifth selector, configured to receive a mode flag signal, and generate a reset command using one of the first switching pulses when the mode flag signal indicates an aging test mode; When the mode flag signal indicates a normal mode, using one of the second switching pulses to generate one of the reset commands; The clock end of the first trigger receives the reset command, the input end of the first trigger is connected to the clock end of the first trigger and its own inverting output end, and the output end of the first trigger outputs the first window signal.

14. The test circuit according to claim 13, characterized in that: The reset command is further used to reset the first count value to a first default value, and the reset command is further used to reset the third count value to a third default value; The first control circuit is further configured to receive the first window signal, and output a first activation signal in a valid state when the first window signal is in an invalid state and the first count value is a first default value; The refresh counting unit is further configured to output a second activation signal in a valid state when the third count value is a third default value; The main control circuit also includes a third selector, which is connected to both the first control circuit and the refresh counting unit and is configured to receive the mode flag signal, and output the first activation signal as the activation indication signal when the mode flag signal represents an aging test mode; and output the second activation signal as the activation indication signal when the mode flag signal represents a normal mode.

15. The test circuit according to claim 12, characterized in that: In the case that the effective states of the first window signal and the activation indication signal are both at high levels, the first gating unit includes a first AND gate, and the second gating unit includes a second AND gate; When the valid state of the second window signal is a high level, the first logic unit includes a third AND gate, and the first control transmission gate is an eighth AND gate; When the second end pulse and the third end pulse are both positive pulses, the second logic unit includes a first OR gate.

16. The test circuit according to claim 5, characterized in that: The selection end of the second selector receives the first window signal, the two input ends of the second selector receive the initial refresh command and the test precharge command respectively, and the output end of the second selector outputs the preselection signal; The selection end of the third selector receives the mode mark signal, the two input ends of the third selector receive the preselection signal and the test clock signal respectively, and the output end of the third selector outputs the intermediate signal.

17. The test circuit according to claim 13, characterized in that: The second count value includes an A-bit count sub-signal, and the second counter includes A second flip-flops and a first XOR gate; The input terminal of the first second trigger is connected to the output terminal of the Ath second trigger; for the 2nd to A-1th triggers, the input terminal of each second trigger is connected to the positive phase output terminal of the previous second trigger; the first input terminal of the first XOR gate is connected to the output terminal of the A-1th trigger, the second input terminal of the first XOR gate is connected to the output terminal of the Ath trigger, and the output terminal of the first XOR gate is connected to the input terminal of the Ath second trigger; The clock end of each second-hand trigger receives the test clock signal, and the output end of the i-th second-hand trigger outputs the i-th counting sub-signal, where i is a positive integer less than or equal to A; wherein the reset command is also used to reset the second counting value to a second default value, and the second default value is an all-1 state.

18. The test circuit according to claim 17, characterized in that: The second frequency is an integral multiple of the first frequency; and the second decoding unit comprises: a fourth decoder, configured to output a command to be selected when the second count value reaches a second threshold; A sampling circuit is configured to perform cyclic counting of the pending commands; generate one second refresh command based on the first pending command; and, starting from the second pending command, output one second refresh command every time a preset number of pending commands are spaced; Wherein, for the test clock signal of the first frequency, the timing duration for the second count value to reach the first threshold from the second default value is the first timing duration; for the test clock signal of the second frequency, the timing duration for the second count value to reach the second threshold from the second default value is the second timing duration; The delayed refresh command is delayed by 2 clock cycles compared to the initial refresh command, and the clock cycle refers to the clock cycle of the test clock signal; The first timing duration+2 / first frequency=the second timing duration+2 / second frequency.

19. The test circuit according to claim 18, characterized in that: When A=6 and the preset number is 2, the first decoding unit includes a first NAND gate, a second NAND gate, a first NOR gate, a second NOR gate, and a fourth AND gate; two input ends of the first NAND gate receive the 4th-bit counting sub-signal and the 3rd-bit counting sub-signal respectively, two input ends of the second NAND gate receive the 2nd-bit counting sub-signal and the 0th-bit counting sub-signal respectively, a first input end of the first NOR gate receives the 5th-bit counting sub-signal, a second input end of the first NOR gate receives the 1st-bit counting sub-signal, a first input end of the second NOR gate is connected to the output end of the first NAND gate, a second input end of the second NOR gate is connected to the output end of the second NAND gate, a first input end of the fourth AND gate is connected to the output end of the first NOR gate, a second input end of the fourth AND gate is connected to the output end of the second NOR gate, and the output end of the fourth AND gate outputs the first refresh command; The fourth decoder comprises a fifth AND gate, a third NOR gate, and a sixth AND gate, wherein three input terminals of the fifth AND gate receive the 0th counting sub-signal, the 1st counting sub-signal, and the 3rd counting sub-signal respectively, and three input terminals of the third NOR gate receive the 5th counting sub-signal, the 4th counting sub-signal, and the 2nd counting sub-signal respectively, and the first input terminal of the sixth AND gate is connected to the output terminal of the fifth AND gate, the second input terminal of the sixth AND gate is connected to the output terminal of the third NOR gate, and the output terminal of the sixth AND gate outputs the command to be selected; The selection circuit includes a third trigger, a delay unit, and a seventh AND gate. The clock end of the third trigger and the input end of the delay unit both receive the command to be selected. The input end of the third trigger is connected to its own inverting output end. The first input end of the seventh AND gate is connected to the output end of the third trigger. The second input end of the seventh AND gate is connected to the output end of the delay unit. The output end of the seventh AND gate outputs the second refresh command.

20. A memory, characterized in that: Comprising a test circuit as claimed in any one of claims 1-19.

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