Semiconductor device, manufacturing method thereof, and memory system

Abstract

The embodiment of the invention provides a semiconductor device, a manufacturing method thereof and a memory system. The semiconductor device comprises a first chip; the plurality of semiconductor structures are positioned on the surface of one side of the first chip in the first direction and are coupled with the first chip; the plurality of semiconductor structures are arranged at intervals in a second direction, and / or are arranged at intervals in a third direction; the second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction; the heat dissipation structure covers the first chip and the plurality of semiconductor structures in a shape-preserving manner. Therefore, when heat is generated in the first chip and / or the semiconductor structure, the heat can be quickly dissipated through the heat dissipation structure, so that the temperature of the semiconductor device is reduced, and the yield and the reliability of the semiconductor device are improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a memory system. Background Art

[0002] With the increasing demand for big data analysis efficiency and miniaturization in the fields of Internet of Things (IoT), Artificial Intelligence (AI), and 3D imaging (3D), 3D stacked memory based on Through Silicon Via (TSV) is considered to be the mainstream architecture for next-generation storage due to its advantages such as high density, high bandwidth, low power interface, and small size.

[0003] However, as the number of stacked layers increases, the heat dissipation problem of the memory becomes an urgent issue to be solved. Summary of the invention

[0004] In view of this, in order to solve one or more of the existing technical problems, the embodiments of the present disclosure propose a semiconductor device and a manufacturing method thereof, and a memory system; wherein, the semiconductor device proposed in the embodiments of the present disclosure includes: a first chip; a plurality of semiconductor structures, which are located on a side surface of the first chip in a first direction, and are all coupled to the first chip; the plurality of semiconductor structures are arranged at intervals in a second direction, and / or, are arranged at intervals in a third direction; the second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction; a heat dissipation structure, conformally covering the first chip and the plurality of semiconductor structures.

[0005] In some embodiments, the thermal conductivity of the heat dissipation structure is greater than the thermal conductivity of the semiconductor structure.

[0006] In some embodiments, the heat dissipation structure includes: a barrier layer conformally covering the first chip and the semiconductor structure; a seed layer conformally covering the barrier layer; and a heat dissipation layer conformally covering the seed layer.

[0007] In some embodiments, the material of the barrier layer includes tantalum or tantalum nitride; the material of the seed layer includes at least one of gold, silver, copper, aluminum, iron and graphite; the material of the heat dissipation layer includes at least one of gold, silver, copper, aluminum, iron and graphite.

[0008] In some embodiments, the seed layer and the heat dissipation layer are made of the same material.

[0009] In some embodiments, the first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the semiconductor structures includes a second chip; the second chip includes a memory cell array and a second bonding layer stacked along the first direction; the second bonding layer of each of the multiple semiconductor structures is bonded to the first bonding layer.

[0010] In some embodiments, the first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the semiconductor structures includes a plurality of second chips stacked along the first direction; each of the second chips includes a memory cell array and a second bonding layer stacked along the first direction; the second bonding layer in the second chip closest to the first chip among the plurality of second chips of each of the semiconductor structures is bonded to the first bonding layer.

[0011] In some embodiments, the semiconductor device further includes: a plastic packaging layer located between the heat dissipation structures on adjacent sides of the semiconductor structure.

[0012] In some embodiments, the material of the molding layer includes silicon oxide or epoxy resin.

[0013] An embodiment of the present disclosure further provides a memory system, comprising the semiconductor device as described in the above embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0014] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor device, the method comprising: providing a first chip; providing a plurality of semiconductor structures, coupling the plurality of semiconductor structures to a side surface of the first chip in a first direction; arranging the plurality of semiconductor structures at intervals in a second direction, and / or arranging the plurality of semiconductor structures at intervals in a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; forming a heat dissipation structure that conformally covers the first chip and the plurality of semiconductor structures.

[0015] In some embodiments, the thermal conductivity of the heat dissipation structure is greater than the thermal conductivity of the semiconductor structure.

[0016] In some embodiments, the heat dissipation structure formed to conformally cover the first chip and the multiple semiconductor structures includes: forming a barrier layer conformally covering the first chip and the multiple semiconductor structures; forming a seed layer conformally covering the barrier layer; and forming a heat dissipation layer conformally covering the seed layer.

[0017] In some embodiments, the first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the multiple semiconductor structures includes a second chip; the second chip includes a memory cell array and a second bonding layer stacked along the first direction; coupling the multiple semiconductor structures to a side surface of the first chip in the first direction includes: bonding the second bonding layer of each of the multiple semiconductor structures to the first bonding layer.

[0018] In some embodiments, the first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the plurality of semiconductor structures includes a plurality of second chips stacked along the first direction; each of the second chips includes a memory cell array and a second bonding layer stacked along the first direction; coupling the plurality of semiconductor structures to a side surface of the first chip in the first direction includes: bonding the second bonding layer in the second chip closest to the first chip among the plurality of second chips of each of the semiconductor structures to the first bonding layer.

[0019] In some embodiments, the method further includes: forming a plastic encapsulation layer between the heat dissipation structures on adjacent sides of the semiconductor structure.

[0020] The embodiments of the present disclosure provide a semiconductor device and a manufacturing method thereof, and a memory system; the semiconductor device includes: a first chip; a plurality of semiconductor structures, which are located on a side surface of the first chip in a first direction and are all coupled to the first chip; the plurality of semiconductor structures are arranged at intervals in a second direction, and / or arranged at intervals in a third direction; the second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction; a heat dissipation structure, which conformally covers the first chip and the plurality of semiconductor structures. In the embodiments of the present disclosure, by coupling a plurality of semiconductor structures on one side of the first chip, arranging the plurality of semiconductor structures at intervals, and conformally setting a heat dissipation structure on the surface and side of the semiconductor structure, and on the surface of the first chip between adjacent semiconductor structures, when heat is generated in the first chip and / or the semiconductor structure, the heat can be quickly dissipated through the heat dissipation structure, so as to reduce the temperature of the semiconductor device and improve the yield and reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of an electronic device provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present disclosure;

[0024] Figure 4 for Figure 2 or Figure 3 A partial enlarged schematic diagram of the heat dissipation structure;

[0025] Figure 5 A schematic cross-sectional view of a local heat dissipation structure provided in one embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of a manufacturing process of a semiconductor device provided by an embodiment of the present disclosure;

[0027] Figure 7 A schematic cross-sectional structure diagram of a first chip provided in an embodiment of the present disclosure;

[0028] Figure 8 A schematic cross-sectional view of a semiconductor structure provided by an embodiment of the present disclosure;

[0029] Fig. 9 A schematic cross-sectional view of a semiconductor structure provided by another embodiment of the present disclosure;

[0030] Fig.10 A schematic diagram of a bonding structure between a first chip and a semiconductor structure provided in an embodiment of the present disclosure;

[0031] Fig.11 A schematic diagram of a bonding structure between a first chip and a semiconductor structure provided in another embodiment of the present disclosure;

[0032] Fig.12 A schematic diagram of a semiconductor device structure with a heat dissipation structure provided in accordance with an embodiment of the present disclosure;

[0033] Fig.13 A schematic diagram of a semiconductor device structure with a heat dissipation structure provided by another embodiment of the present disclosure;

[0034] Fig.14 A schematic diagram of the structure of a semiconductor device with a plastic packaging material provided in one embodiment of the present disclosure;

[0035] Fig.15 A schematic diagram of the structure of a semiconductor device with a plastic packaging material provided by another embodiment of the present disclosure;

[0036] Fig.16 A schematic diagram of the structure of a semiconductor device with a plastic packaging layer provided in one embodiment of the present disclosure;

[0037] Fig.17 A schematic diagram of the structure of a semiconductor device with a plastic packaging layer provided in another embodiment of the present disclosure.

[0038] Reference numerals

[0039] 1-electronic device; 10-memory system; 20-host; 110-memory controller; 120-memory; 111-command generator; 112-address generator; 113-device interface; 114-host interface; 121-storage cell array; 122-peripheral circuit; 201-first chip; 2012-peripheral circuit; 2014-first bonding layer; 2016-first bonding contact; 2018-first dielectric layer; 2020-first interconnection structure; 202-semiconductor structure; 2021-second chip; 2022-storage cell array; 2023-third bonding layer; 2024-second bonding layer; 2026-second bonding contact; 2028-second dielectric; 2030-second interconnection structure; 2036-third bonding contact; 2038-third dielectric layer; 2040-third interconnection structure; 203-heat dissipation structure; 2031- Barrier layer; 2032-seed layer; 2033-heat dissipation layer; 203a-first part; 203b-second part; 203c-third part; 204-plastic layer; 701-first chip; 7012-peripheral circuit; 7014-first bonding layer; 7016-first bonding contact; 7018-first dielectric layer; 7020-first interconnect structure; 702-semiconductor structure; 7021-second chip; 7022-storage Storage unit array; 7023-third bonding layer; 7024-second bonding layer; 7026-second bonding contact; 7028-second dielectric; 7030-second interconnection structure; 7036-third bonding contact; 7038-third dielectric layer; 7040-third interconnection structure; 703-heat dissipation structure; 7031-barrier layer; 7032-seed layer; 7033-heat dissipation layer; 704-plastic encapsulation layer; 705-plastic encapsulation material.

[0040] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0041] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0042] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0043] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0044] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0045] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0046] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0047] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0048] Figure 1 Schematic diagram of an electronic device provided by an embodiment of the present disclosure. The electronic device 1 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0049] like Figure 1 As shown, the electronic device 1 may include a memory system 10 and a host 20, and the memory system 10 may include a memory controller 110 and a memory 120. The host 20 may include a processor of the electronic device 1, for example, a central processing unit (CPU) or a system on chip (SoC) (for example, an application processor (AP)). The memory controller 110 is coupled to both the host 20 and the memory 120, and the memory controller 110 may be configured to communicate with the host 20 and control the memory 120.

[0050] In some embodiments, the memory controller 110 may be configured to control operations of the memory 120, such as a read operation, an erase operation, a write operation, a refresh operation, etc. In some embodiments, the memory controller 110 is further configured to process an error correction code (ECC) on data read from or written to the memory 120. In other embodiments, the memory controller 110 may also be configured to perform any other suitable operations, such as formatting the memory 120.

[0051] In some embodiments, the memory controller 110 may receive data, commands, and addresses from the host 20, and may send data, commands, and addresses to the memory 120. Specifically, the memory controller 110 may include a command generator 111, an address generator 112, a device interface 113, and a host interface 114. The memory controller 110 may receive data, commands, and addresses from the host 20 through the host interface 114, decode the command received from the host 20 through the command generator 111 to generate an access command CMD, and may provide the access command CMD to the memory 120 through the device interface 113. The memory controller 110 may generate an address ADDR to be accessed in the memory cell array 121 by decoding the address received from the host interface 114 through the address generator 112, and may provide the address ADDR to be accessed to the memory 120 through the device interface 113. The access command may be a signal instructing the memory 120 to write or read data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR. In addition, the memory controller 110 may also send a refresh command to the memory 120 . The refresh command may be a signal instructing the memory 120 to read out and rewrite data by accessing one or more memory cells in the memory cell array 121 corresponding to the address ADDR.

[0052] In some embodiments, the memory 120 includes a memory cell array 121 and a peripheral circuit 122. The memory cell array 121 includes a plurality of memory cells arranged in an array. The peripheral circuit 122 includes a sense amplifier circuit, a row decoder, a column decoder, a data input / output buffer, etc. The peripheral circuit 122 is used to receive an access command CMD and an address ADDR. Based on the analysis of the access command CMD and the address ADDR, each memory cell in the memory cell array 121 can be independently accessed, and a read operation, a write operation, or a refresh operation, etc., can be performed on the data stored in the accessed memory cell.

[0053] In some specific examples, the memory 120 can be a NAND Flash, a random access memory (RAM), such as a dynamic random access memory, a synchronous dynamic random access memory (SDRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a double data rate SDRAM (DDR SDRAM), a phase-change random access memory (PRAM), a resistive random access memory (ReRAM), a magnetic random access memory (MRAM), etc.

[0054] In some embodiments, in order to increase the storage density of the memory and improve the data transmission efficiency, the dies are stacked vertically on the wafer, that is, the die to wafer structure (D2W), or the chips are stacked vertically on the wafer, that is, the chip to wafer structure (C2W), or multiple memory cell arrays are stacked vertically on the peripheral circuit, and the through silicon via (TSV) technology is used to realize the vertical interconnection of multiple stacked structures. However, as the number of stacked layers gradually increases, a large amount of heat will be generated when the memory is working. If the heat cannot be effectively dissipated, the yield and reliability of the memory will be affected.

[0055] Based on this, in order to solve one or more of the above problems, the present disclosure provides a semiconductor device in an embodiment, such as Figure 2 and Figure 3 As shown, Figure 2 A schematic cross-sectional structure diagram of a semiconductor device provided in an embodiment of the present disclosure, Figure 3 A schematic cross-sectional structure diagram of another semiconductor device provided by an embodiment of the present disclosure is shown in FIG. Figure 2 and Figure 3 As shown, the semiconductor device includes: a first chip 201; a plurality of semiconductor structures 202, which are located on a side surface of the first chip 201 in a first direction and are all coupled to the first chip 201; the plurality of semiconductor structures 202 are arranged at intervals in a second direction, and / or are arranged at intervals in a third direction; the second direction intersects with the third direction, and the second direction and the third direction are both perpendicular to the first direction; and a heat dissipation structure 203, which conformally covers the first chip 201 and the plurality of semiconductor structures 202.

[0056] Thus, on one hand, by arranging the heat dissipation structure 203 on one side away from the first chip 201 among the two sides of the semiconductor structure 202 opposite to each other along the first direction, the side of the semiconductor structure 202 along the second direction and the third direction, and between adjacent semiconductor structures, when heat is generated in the first chip and / or the semiconductor structure, the heat can be quickly dissipated through the heat dissipation structure to reduce the temperature of the semiconductor device and improve the yield and reliability of the semiconductor device. On the other hand, the heat dissipation structure 203 conformally covers the first chip 201 and the semiconductor structure 202, which can make the contact between the heat dissipation structure and the device to be dissipated (such as the first chip and / or the semiconductor structure) more closely fitted, that is, the contact area is larger and the heat dissipation efficiency is higher, so that the heat dissipation efficiency of the heat dissipation structure can be further improved.

[0057] Before describing the semiconductor device shown in the figure below in detail, various directions that may be used in the following description are defined. In the present disclosure, the stacking direction of multiple chips in the semiconductor device is defined as a first direction (i.e., the Z-axis direction). In a plane perpendicular to the Z-direction, an intersecting second direction (i.e., the X-axis direction) and a third direction (i.e., the Y-axis direction) are defined. In some embodiments, the X-axis direction, the Y-axis direction, and the Z-axis direction may be perpendicular to each other.

[0058] Exemplary, reference Figure 2 and Figure 3 The semiconductor device includes a first chip 201 and a plurality of semiconductor structures 202 stacked on a surface of one side of the first chip 201 along the Z-axis direction, wherein each of the plurality of semiconductor structures 202 is coupled to the first chip 201; wherein the plurality of semiconductor structures 202 may be arranged at intervals along the X-axis direction, or the plurality of semiconductor structures 202 may be arranged at intervals along the Y-axis direction, or the plurality of semiconductor structures 202 may be arranged in an array along the X-axis direction and the Y-axis direction. Here, the plurality of semiconductor structures 202 may be arranged uniformly or non-uniformly.

[0059] In the embodiment of the present disclosure, the first chip 201 and each of the plurality of semiconductor structures 202 may be connected by hybrid bonding, wherein each of the plurality of semiconductor structures 202 may be bonded at a bonding interface between the corresponding semiconductor structure and the first chip ( Figure 2 The AA' line shown in the figure, Figure 3 BB' line) in a face-to-face manner (such as Figure 2 , Figure 3 , and is coupled to the first chip 201 (in the direction indicated by the arrow shown in FIG. 1 ).

[0060] In some specific embodiments, the first chip 201 may include a peripheral circuit 2012 and a first bonding layer 2014 stacked along the Z-axis direction; the peripheral circuit 2012 may include a plurality of complementary metal oxide semiconductor (CMOS) transistors and control circuits related to CMOS transistors, such as control logic, sensing amplifier circuits, row decoders, column decoders, data input / output buffers, drivers, and read-write circuits, etc., wherein, when the control logic receives read-write operation commands and address data, under the action of the control logic, the row decoder or the column decoder can apply the corresponding voltage generated by the driver to the corresponding bit line and word line based on the decoded address to realize data reading or writing, and perform data interaction with external devices through the data input / output buffer.

[0061] The first bonding layer 2014 may include a plurality of first bonding contacts 2016, a plurality of first interconnect structures 2020, and a first dielectric 2018 for electrically isolating adjacent first bonding contacts 2016 and adjacent first interconnect structures 2020, wherein the plurality of first bonding contacts 2016 correspond to and are connected to the plurality of first interconnect structures 2020 one by one, that is, each first bonding contact 2016 is connected to one first interconnect structure 2020, and one end of the first interconnect structure 2020, which is away from the first bonding contact 2016, on two opposite sides along the Z-axis direction is coupled to the peripheral circuit 2012, where the connected first bonding contacts 2016 and the first interconnect structure 2020 can be used to implement electrical signal transmission of COMS transistors and related control circuits in the peripheral circuit 2012. The first bonding contacts 2016 in the first bonding layer 2014 and the surrounding first dielectric 2018 can be used for hybrid bonding. The materials of the first bonding contact 2016 and the first interconnect structure 2020 may include but are not limited to copper (Cu), and the material of the first dielectric layer 2018 may include but are not limited to silicon oxide (SiO 2 ) or silicon carbonitride (SiCN).

[0062] In some specific embodiments, each semiconductor structure 202 of the plurality of semiconductor structures 202 may include one second chip 2021 , or may include a plurality of second chips 2021 stacked along the Z-axis direction.

[0063] refer to Figure 2 Each semiconductor structure 202 includes a second chip 2021. The second chip 2021 may include a memory cell array 2022 and a second bonding layer 2024 stacked along the Z-axis direction. The second bonding layer 2024 of each semiconductor structure in the plurality of semiconductor structures is bonded to the first bonding layer 2014. The second bonding contact 2026 is at the bonding interface between the first chip 201 and the semiconductor structure 202 ( Figure 2 In other words, the first bonding layer 2014 is located on the side of the peripheral circuit 2012 close to the semiconductor structure 202, and the second bonding layer 2024 is located on the side of the memory cell array 2022 close to the first chip 201, that is, the first bonding layer 2014 is located between the peripheral circuit 2012 and the second bonding layer 2024, and the second bonding layer 2024 is located between the memory cell array 2022 and the first bonding layer 2014, that is, the first chip 201 and the second chip 2021 are bonded and connected in a face-to-face manner.

[0064] refer to Figure 3 , each semiconductor structure 202 includes a plurality of second chips 2021 stacked along the Z-axis direction. Each second chip 2021 includes a memory cell array 2022 and a second bonding layer 2024 stacked along the Z-axis direction. Moreover, among the plurality of second chips 2021 of each semiconductor structure 202, except for the second chip 2021 farthest from the first chip 201, the remaining second chips 2021 also include a third bonding layer 2023; at this time, among the plurality of second chips including the third bonding layer, the third bonding layer in each second chip is located on one side of the memory cell array in the second chip that is opposite to each other along the first direction and is far away from the second bonding layer in the second chip. In other words, the second chip 2021 farthest from the first chip 201 along the Z-axis direction among the multiple second chips 2021 only includes a memory cell array 2022 and a second bonding layer 2024 stacked in sequence along the Z-axis direction; the second chip located between the farthest second chip and the first chip includes a second bonding layer 2024, a memory cell array 2022 and a third bonding layer 2023 stacked in sequence along the Z-axis direction.

[0065] The second bonding layer 2024 may include a plurality of second bonding contacts 2026, a plurality of second interconnect structures 2030, and a second dielectric 2028 for electrically isolating adjacent second bonding contacts 2026 and adjacent second interconnect structures 2030. The plurality of second bonding contacts 2026 correspond to and are connected to the plurality of second interconnect structures 2030 one by one, and one end of the second interconnect structure 2030 away from the second bonding contact 2026 on both sides opposite to each other along the Z-axis direction is coupled to the memory cell array 2022 of the second chip to which it belongs, and the connected second bonding contacts 2026 and the second interconnect structure 2030 are used to realize the transmission of electrical signals in the memory cell array 2022 of the second chip to which it belongs. Here, the second bonding contacts 2026 in the second bonding layer 2024 and the surrounding second dielectric 2028 can be used for hybrid bonding. The materials of the second bonding contacts 2026 and the second interconnect structure 2030 can include but are not limited to copper, and the materials of the second dielectric layer 2028 can include but are not limited to silicon oxide or silicon carbonitride.

[0066] The third bonding layer 2023 includes a plurality of third bonding contacts 2036, a plurality of third interconnect structures 2040, and a third dielectric 2038 for electrically isolating adjacent third bonding contacts 2036 and adjacent third interconnect structures 2040, wherein the plurality of third bonding contacts 2036 correspond to and are connected to the plurality of third interconnect structures 2040 one by one, and one end of the third interconnect structure 2040 away from the third bonding contact 2036 on two opposite sides along the Z-axis direction is coupled to the memory cell array 2022 of the second chip to which it belongs, and the connected third bonding contacts 2036 and third interconnect structures 2040 are used to lead out electrical signals in the memory cell array 2022 of the second chip to which it belongs.

[0067] In some specific embodiments, the multiple second chips 2021 stacked in the Z-axis direction in each semiconductor structure 202 can be divided into a second chip located at an upper end and a second chip located at a lower end, and the upper end and the lower end are two opposite ends of the semiconductor structure along the Z-axis direction; one side surface of the storage unit array in the second chip located at the upper end is exposed, and one side surface of the second bonding layer in the second chip located at the lower end is exposed. At this time, the exposed second bonding layer in the second chip located at the lower end is bonded to the first bonding layer of the first chip, so that the first chip is connected to the semiconductor structure in a face-to-face manner.

[0068] More specifically: the second bonding contact 2026 in the second bonding layer of the second chip at the lower end of each semiconductor structure contacts the first bonding contact 2016 in the first bonding layer at the bonding interface between the first chip 201 and the semiconductor structure 202. Between the second chip at the upper end of each semiconductor structure 202 and the second chip between the upper end and the lower end, the third bonding contact 2036 in the third bonding layer of the previous second chip is bonded to the second bonding contact 2026 in the second bonding layer of the next second chip. In this way, electrical signal connection between the first chip and each semiconductor structure can be achieved.

[0069] refer to Figure 3 The second chips 2021 are arranged face to back (eg Figure 3 Specifically, the second bonding layer 2024 in the second chip 2021 closest to the first chip 201 among the plurality of second chips 2021 of each semiconductor structure 202 is connected to the first bonding layer 2014 at the coupling point between the first chip and the semiconductor structure ( Figure 3 The first bonding contact 2016 is connected to the second bonding contact 2026. The third bonding layer of the second chip connected to the first chip is connected to the second bonding layer in the next second chip at the coupling point of the two second chips ( Figure 3 The third bonding contact 2036 is connected to the second bonding contact 2026 of the next second chip by a CC' line) bonding connection shown in FIG.

[0070] In other specific embodiments, a portion of the multiple semiconductor structures includes a second chip, and another portion of the semiconductor structures includes multiple second chips stacked along the Z-axis direction. In this case, the bonding method between the multiple semiconductor structures and the first chip can refer to the bonding method described in the above embodiments.

[0071] In the embodiment of the present disclosure, the memory cell array 2022 may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc.

[0072] It should be noted that, in the above embodiments, the first chip includes a peripheral circuit and the second chip includes a memory cell array. In other embodiments, the first chip may be a die, a chip, a wafer, etc., and the second chip may be a die, a chip, a wafer, etc. Alternatively, the first chip and the second chip may be the same.

[0073] In some other embodiments, the first chip may further include a first substrate, the first substrate being located on a side of the peripheral circuit away from the first bonding layer along the Z-axis direction; and / or the second chip may further include a second substrate, the second substrate being located on a side of the memory cell array away from the second bonding layer along the Z-axis direction. The materials of the first substrate and the second substrate may include at least one of semiconductor materials such as silicon, germanium, and silicon germanium.

[0074] In some other embodiments, the first chip 201 and the semiconductor structure 202 may not be connected by bonding, but may be integrated on the same substrate and directly connected by one or more interconnection layers between the first chip 201 and each semiconductor structure 202. In this case, the first bonding layer and the first bonding contact may not be set in the first chip 201; the second bonding layer and the second bonding contact, the third bonding layer and the third bonding contact may not be set in the second chip 2021.

[0075] In the embodiments of the present disclosure, reference Figure 2 , Figure 3 and Figure 4 , Figure 4 for Figure 2 or Figure 3A partial enlarged schematic diagram of the heat dissipation structure is shown in FIG. 2 , in which the heat dissipation structure 203 may include three parts: a first part 203a located on a side surface of the semiconductor structure 202 away from the first chip 201 along the Z-axis direction, a second part 203b located on the side of the semiconductor structure 202, and a third part 203c located between adjacent semiconductor structures 202; wherein the third part 203c covers a portion of the surface of the first chip 201, and the third part 203c is connected to both the first part 203a and the second part 203b.

[0076] In other embodiments, the heat dissipation structure 203 may be disposed only on the surface and side of some of the semiconductor structures 202 among the multiple semiconductor structures 202, or may be disposed only on the surface of some or all of the semiconductor structures 202 among the multiple semiconductor structures 202, or may be disposed only on the side of some or all of the semiconductor structures 202 among the multiple semiconductor structures 202, etc. Moreover, the heat dissipation structure 203 may include only the first portion 203a located on the surface of the semiconductor structure 202; may also include only the second portion 203b located on the side of the semiconductor structure 202; or may also include only the third portion 203c located between two adjacent semiconductor structures 202. However, it should be understood that when the heat dissipation structure 203 is disposed on the surface and side of all semiconductor structures 202 and between adjacent semiconductor structures 202, the heat in the semiconductor device can be dissipated more quickly and efficiently, thereby further improving the heat dissipation efficiency of the semiconductor device.

[0077] In some embodiments, the thermal conductivity of the heat dissipation structure 203 is greater than the thermal conductivity of the semiconductor structure 202. It should be noted that the larger the value of the thermal conductivity of a device, the stronger the conductive heat dissipation capability of the device.

[0078] In the embodiment of the present disclosure, the heat dissipation structure 203 may include only one layer of heat dissipation material, or may include multiple layers of heat dissipation material.

[0079] Exemplary, reference Figure 2 , Figure 3 and Figure 5 , Figure 5 for Figure 2 or Figure 3An enlarged schematic diagram of a local heat dissipation structure shown in a dotted box; wherein the heat dissipation structure 203 includes a barrier layer 2031 that conformally covers the first chip 201 and the semiconductor structure 202, a seed layer 2032 that conformally covers the barrier layer 2031, and a heat dissipation layer 2033 that conformally covers the seed layer 2032. In other words, the barrier layer 2031 is located on the surface of the semiconductor structure 202 away from the first chip 201 along the Z-axis direction, and on the side of the semiconductor structure 202 along the X-axis direction and the Y-axis direction; the seed layer 2032 is located on the surface of the barrier layer 2031 away from the semiconductor structure 202; and the heat dissipation layer 2033 is located on the surface of the seed layer 2032 away from the barrier layer 2031.

[0080] The barrier layer 2031 is used to prevent the material in the seed layer 2032 or the heat dissipation layer 2033 from diffusing into the semiconductor structure. The material of the barrier layer 2031 includes, but is not limited to, tantalum (Ta), tantalum nitride (TaN), or a combination of the two. The method of forming the barrier layer 2031 includes, but is not limited to, physical vapor deposition (PVD) processes, such as vacuum evaporation, sputtering, plasma coating, and molecular beam epitaxy; atomic layer deposition (ALD) processes.

[0081] The seed layer 2032 covers the surface of the barrier layer 2031, and is used to provide a starting point for crystal growth for forming a heat dissipation layer in the subsequent process, and guide or control the crystal phase of the heat dissipation layer. The seed layer 2032 can also control the shape and size of the final crystal (such as the heat dissipation layer) by selecting seed crystals of different shapes and sizes. In this way, defects in the crystal growth process, such as dislocations, lattice distortions, and uneven distribution and stress of impurities, can be reduced, thereby improving the overall quality of the crystal. Here, the material of the seed layer 2032 includes but is not limited to copper. The PVD process, ALD process, etc. for forming the seed layer 2032.

[0082] The heat dissipation layer 2033 is used to quickly dissipate the heat generated in the first chip and / or the semiconductor structure. The material of the heat dissipation layer 2033 includes at least one of gold, silver, copper, aluminum, iron and graphite; in other embodiments, the material of the heat dissipation layer can also be any other suitable material. The method of forming the heat dissipation layer 2033 includes but is not limited to the electrochemical plating (ECP) process.

[0083] It should be noted that the thicknesses of the barrier layer 2031 , the seed crystal layer 2032 and the heat dissipation layer 2033 can be selected and set according to actual needs, and are not limited in the present disclosure.

[0084] In some embodiments, reference Figure 2 , Figure 3, the semiconductor device further includes: a molding layer (Molding) 204, the molding layer 204 is located between the heat dissipation structures on the side of the adjacent semiconductor structure 202. That is, the molding layer 204 is located on the side of the second part of the heat dissipation structure away from the semiconductor structure 202 along the X-axis direction and / or along the Y-axis direction, and the molding layer 204 fills the gap between the two adjacent semiconductor structures. Here, the molding layer 204 can be used to fix the adjacent semiconductor structures to ensure the stability and reliability of the semiconductor device. The material of the molding layer 204 includes silicon oxide or epoxy resin. The method of forming the molding layer includes but is not limited to a coating process and a deposition process; wherein the coating process includes spin coating. The deposition process includes but is not limited to chemical vapor deposition (Chemical Vapor Deposition, CVD), low pressure chemical vapor deposition (Low Pressure Chemical Vapor Deposition, LPCVD), plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD), PVD and ALD processes.

[0085] In the embodiment of the present disclosure, a plurality of semiconductor structures are coupled to a surface of one side of a first chip along the Z-axis direction, and the plurality of semiconductor structures are arranged at intervals, and a heat dissipation structure is provided on the surface of the semiconductor structure along the Z-axis direction and the side surfaces along the X-axis direction and / or along the Y-axis direction, and on a portion of the surface of the first chip between adjacent semiconductor structures, so that the heat generated in the first chip and / or the semiconductor structure can be quickly dissipated through the heat dissipation structure, so as to reduce the temperature of the semiconductor device and improve the yield and reliability of the semiconductor device.

[0086] Based on the above semiconductor device, the present disclosure also provides a method for manufacturing a semiconductor device. Figure 6 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device in an embodiment of the present disclosure; Figure 6 As shown, the manufacturing method comprises the following steps:

[0087] Step S601: providing a first chip.

[0088] Step S602: provide multiple semiconductor structures, and couple the multiple semiconductor structures to a side surface of the first chip in a first direction; the multiple semiconductor structures are arranged at intervals in the second direction, and / or, arranged at intervals in a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction.

[0089] Step S603: forming a heat dissipation structure conformally covering the first chip and the plurality of semiconductor structures.

[0090] It should be understood that Figure 6The steps shown in the operation are not exclusive, and other steps may be performed before, after or between any steps in the operation shown; Figure 6 The steps shown in the figure can be adjusted in sequence according to actual needs. Figures 7 to 17 The structure diagram of the manufacturing process of the semiconductor device provided in the embodiment of the present disclosure is as follows. Figures 6 to 17 A method for manufacturing a semiconductor device provided in an embodiment of the present disclosure is introduced.

[0091] In some embodiments, reference Figure 7 , providing a first chip 701. The first chip 701 includes a peripheral circuit 7012 and a first bonding layer 7014 stacked along the Z-axis direction. The peripheral circuit 7012 includes a plurality of CMOS transistors and a control circuit related to the CMOS transistors, and the control circuit has been described above and will not be repeated here. The first bonding layer 7014 may include a plurality of first bonding contacts 7016, a plurality of first interconnect structures 7020, and a first dielectric 7018 for electrically isolating the first bonding contacts 7016 and the first interconnect structures 7020. The plurality of first bonding contacts 7016 correspond to and are connected to the plurality of first interconnect structures 7020 one by one. The first interconnect structure 7020 is connected to the peripheral circuit at one end away from the first bonding contacts 7016 along the Z-axis direction. The first bonding contacts 7016 in the first bonding layer 7014 and the surrounding first dielectric 7018 can be used for hybrid bonding. The method for forming the peripheral circuit 7012 and the first bonding layer 7014 is relatively mature and will not be repeated here. It should be noted that, in some other embodiments, the first chip may further include a first substrate located on a side of the peripheral circuit away from the first bonding layer along the Z-axis direction.

[0092] In some embodiments, reference Figure 8 and Fig. 9 , providing a plurality of semiconductor structures 702. Figure 8 The semiconductor structure 702 shown in FIG. 7 includes a second chip 7021. The second chip 7021 may include a memory cell array 7022 and a second bonding layer 7024 stacked along the Z-axis direction.

[0093] Fig. 9The semiconductor structure 702 shown in the figure includes a plurality of second chips 7021, and the plurality of second chips 7021 are stacked along the Z-axis direction. The second chip 7021 farthest from the first chip 701 along the Z-axis direction among the plurality of stacked second chips 7021 includes a memory cell array 7022 and a second bonding layer 7024; the second chip located between the farthest second chip and the first chip includes a third bonding layer 7023, a memory cell array 7022, and a second bonding layer 7024 stacked in sequence along the Z-axis direction. In other words, the plurality of second chips 7021 are stacked in a face-to-back manner; wherein, the memory cell array at one end of the plurality of stacked second chips 7021 is exposed, and the second bonding layer at the other end is exposed.

[0094] The second bonding layer 7024 may include a plurality of second bonding contacts 7026, a plurality of second interconnect structures 7030, and a second dielectric 7028 for electrically isolating the second bonding contacts 7026 and the second interconnect structures 7030. The plurality of second bonding contacts 7026 correspond to and are connected to the plurality of second interconnect structures 7030 one by one, and the second bonding contacts 7026 and the second interconnect structures 7030 are used to realize the transmission of electrical signals in the memory cell array 7022 of the second chip. Here, the second bonding contacts 7026 in the second bonding layer 7024 and the surrounding second dielectric 7028 may be used for hybrid bonding. The materials of the second bonding contacts 7026 and the second interconnect structures 7030 may include but are not limited to copper, and the materials of the second dielectric layer 7028 may include but are not limited to silicon oxide or silicon carbonitride. The third bonding layer 7023 includes a plurality of third bonding contacts 7036, a plurality of third interconnect structures 7040, and a third dielectric 7038 for electrically isolating the third bonding contacts 7036 and the third interconnect structures 7040, wherein the plurality of third bonding contacts 7036 correspond to and are connected to the plurality of third interconnect structures 7040 one by one, and the third bonding contacts 7036 and the third interconnect structures 7040 are used to lead out electrical signals in the storage cell array 7022 of the second chip.

[0095] The memory cell array 7022 may include a plurality of memory cells, which may be NAND memory cells, PCM memory cells, DRAM memory cells, etc. It should be noted that in other embodiments, the second chip may further include a second substrate located on a side of the memory cell array away from the second bonding layer along the Z-axis direction.

[0096] refer to Fig.10 and Fig.11 , a plurality of semiconductor structures 702 are bonded on a surface of one side of the first chip 701 . Fig.10 Each semiconductor structure 702 shown in the figure includes a second chip 7021; Fig.11Each semiconductor structure 702 shown in FIG. 1 includes a plurality of second chips 7021 .

[0097] like Fig.10 As shown, the method includes: connecting the exposed second bonding layer 7024 of each semiconductor structure in the plurality of semiconductor structures 702 to the first bonding layer 7014 at the coupling point between the semiconductor structure and the first chip ( Fig.10 In this way, the electrical signal connection between the first chip 701 and each semiconductor structure 702 can be achieved.

[0098] like Fig.11 As shown, the method includes: connecting the exposed second bonding layer 7024 of the plurality of second chips 7021 of each semiconductor structure 702 to the first bonding layer 7014 at the coupling point between the first chip and the semiconductor structure ( Fig.11 The second chip connected to the first chip has a third bonding layer connected to the second bonding layer of the next second chip at the coupling point of the two second chips ( Fig.11 In this way, the electrical signal connection between the first chip 701 and each semiconductor structure 702 can be achieved.

[0099] It should be noted that when coupling a semiconductor structure having multiple second chips to a first chip, the multiple second chips can be stacked and bonded first, and then the bonded multiple second chips can be bonded to the first chip to complete the stacking and coupling of the multiple second chips to the first chip. It is also possible to first bond the first second chip to the first bonding layer of the first chip, and then bond and couple the second to more second chips one by one to the first second chip to complete the stacking and coupling of the multiple second chips to the first chip. In addition, the first chip and the multiple semiconductor structures can also be coupled in other ways (such as non-hybrid bonding), which is not limited in the present disclosure.

[0100] Next, refer to Fig.12 and Fig.13 , forming a heat dissipation structure that conformally covers the first chip and the plurality of semiconductor structures. Fig.12 Each semiconductor structure shown in the figure includes a second chip; Fig.13Each semiconductor structure shown in the figure includes a plurality of second chips. Here, the heat dissipation structure 703 includes a barrier layer 7031 that conformally covers the first chip 701 and the plurality of semiconductor structures 702, a seed layer 7032 that conformally covers the surface of the barrier layer 7031, and a heat dissipation layer 7033 that conformally covers the surface of the seed layer 7032. Based on this, the specific method of forming the heat dissipation structure includes: forming a barrier layer 7031 that conformally covers the first chip 701 and the plurality of semiconductor structures 702; forming a seed layer 7032 that conformally covers the barrier layer 7031; and forming a heat dissipation layer 7033 that conformally covers the seed layer 7032.

[0101] The barrier layer 7031 is used to prevent the material in the seed layer 7032 or the heat dissipation layer 7033 from diffusing into the semiconductor structure. The material of the barrier layer 7031 includes but is not limited to tantalum, tantalum nitride or a combination of the two. The method of forming the barrier layer 7031 includes but is not limited to PVD process and ALD process.

[0102] The seed layer 7032 covers the surface of the barrier layer 7031 and is used to provide a starting point for crystal growth for forming a heat dissipation layer in the subsequent process, and guide or control the crystal phase of the heat dissipation layer. The seed layer 7032 can also control the shape and size of the final crystal (such as the heat dissipation layer) by selecting seed crystals of different shapes and sizes. In this way, defects in the crystal growth process, such as dislocations, lattice distortions, and uneven distribution and stress of impurities, can be reduced, thereby improving the overall quality of the crystal. Here, the material of the seed layer 7032 includes but is not limited to copper. The PVD process, ALD process, etc. for forming the seed layer 7032.

[0103] The heat dissipation layer 7033 is used to quickly dissipate the heat generated in the first chip and / or the semiconductor structure. The material of the heat dissipation layer 7033 includes at least one of gold, silver, copper, aluminum, iron and graphite; in other embodiments, the material of the heat dissipation layer can also be any other suitable material. The method of forming the heat dissipation layer 7033 includes but is not limited to the ECP process.

[0104] In some embodiments, reference Fig.14 , Fig.15 , Fig.16 and Fig.17 , Fig.14 and Fig.16 Each semiconductor structure shown in the figure includes a second chip; Fig.15 and Fig.17 Each semiconductor structure shown in FIG. 7 includes a plurality of second chips. The method further includes: forming a plastic encapsulation layer 704 between the heat dissipation structures on the sides of adjacent semiconductor structures 702 .

[0105] The method specifically includes: forming a plastic encapsulation material 705 (refer to FIG. 1 ) on the surface of the heat dissipation structure 703 located on the surface of the semiconductor structure 702 on two opposite sides along the Z-axis direction, which is away from the semiconductor structure 702, and in the gap between the heat dissipation structures located on the side of the adjacent semiconductor structure 702. Fig.14 and Fig.15 Then, the plastic encapsulation material on the side away from the semiconductor structure 702 on the two opposite sides of the heat dissipation structure 703 along the Z-axis direction is removed (refer to Fig.16 and Fig.17 ), so as to form a plastic encapsulation layer 704 between the heat dissipation structures on the sides of the adjacent semiconductor structures 702. Here, the plastic encapsulation layer 704 fills the gap between the two adjacent semiconductor structures. At this time, the top surface of the plastic encapsulation layer 704 is substantially flush with the surface of the exposed heat dissipation structure 703 along the X-axis direction.

[0106] It should be understood that the “substantially flush” mentioned here can be understood as flush or approximately flush, wherein the non-fluctuation caused by errors in the actual manufacturing process is within the range of substantially flush or approximately flush.

[0107] The material of the plastic layer 704 includes but is not limited to silicon oxide or epoxy resin. The method of forming the plastic material 705 includes but is not limited to a spin coating process and a deposition process. The deposition process includes but is not limited to CVD, LPCVD, PECVD, PVD and ALD. The removal process includes but is not limited to dry etching, chemical mechanical polishing (CMP) process, etc.

[0108] It should be noted that when the heat dissipation structure is only arranged above the surface of one side away from the first chip on the two opposite sides of the semiconductor structure along the Z-axis direction, only the plastic encapsulation layer can be arranged in the gap between adjacent semiconductor structures. At this time, the plastic encapsulation layer can be used to fill the gap between adjacent semiconductor structures.

[0109] Based on this, in the embodiments of the present disclosure, a conformal semiconductor structure and a heat dissipation structure of the first chip are formed on the semiconductor structure and the first chip, so that the heat generated in the first chip and / or the semiconductor structure can be quickly dissipated through the heat dissipation structure, thereby reducing the temperature of the semiconductor device and improving the yield and reliability of the semiconductor device.

[0110] Based on the above-mentioned semiconductor device and its manufacturing method, the embodiment of the present disclosure also provides a memory system, including the semiconductor device as described in the above-mentioned embodiment of the present disclosure; and a memory controller coupled to the semiconductor device and used to control the semiconductor device.

[0111] It should be noted that: "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In addition, the technical solutions recorded in the embodiments of the present disclosure can be combined arbitrarily without conflict.

[0112] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: First chip; A plurality of semiconductor structures are located on a side surface of the first chip in a first direction and are coupled to the first chip; the plurality of semiconductor structures are arranged at intervals in a second direction and / or are arranged at intervals in a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; The heat dissipation structure conformally covers the first chip and the plurality of semiconductor structures.

2. The semiconductor device according to claim 1, characterized in that The thermal conductivity of the heat dissipation structure is greater than the thermal conductivity of the semiconductor structure.

3. The semiconductor device according to claim 2, characterized in that The heat dissipation structure comprises: a barrier layer conformally covering the first chip and the semiconductor structure; a seed layer conformally covering the barrier layer; and A heat dissipation layer conformally covers the seed layer.

4. The semiconductor device according to claim 3, characterized in that The material of the barrier layer includes tantalum or tantalum nitride; the material of the seed layer includes at least one of gold, silver, copper, aluminum, iron and graphite; the material of the heat dissipation layer includes at least one of gold, silver, copper, aluminum, iron and graphite.

5. The semiconductor device according to claim 4, characterized in that The seed layer and the heat dissipation layer are made of the same material.

6. The semiconductor device according to claim 1, wherein: The first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the semiconductor structures includes a second chip; the second chip includes a memory cell array and a second bonding layer stacked along the first direction; The second bonding layer of each of the semiconductor structures in the plurality of semiconductor structures is bonded to the first bonding layer.

7. The semiconductor device according to claim 1, wherein: The first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the semiconductor structures includes a plurality of second chips stacked and arranged along the first direction; each of the second chips includes a memory cell array and a second bonding layer stacked along the first direction; The second bonding layer in the second chip closest to the first chip among the plurality of second chips in each of the semiconductor structures is bonded to the first bonding layer.

8. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: The plastic sealing layer is located between the heat dissipation structures on the sides of the adjacent semiconductor structures.

9. The semiconductor device according to claim 8, characterized in that The material of the plastic sealing layer includes silicon oxide or epoxy resin.

10. A memory system, characterized in that: A semiconductor device comprising any one of claims 1 to 9; and The memory controller is coupled to the semiconductor device and is used to control the semiconductor device.

11. A method for manufacturing a semiconductor device, characterized in that: The method comprises: providing a first chip; Providing a plurality of semiconductor structures, coupling the plurality of semiconductor structures to a side surface of the first chip in a first direction; the plurality of semiconductor structures are arranged at intervals in a second direction, and / or arranged at intervals in a third direction; the second direction intersects the third direction, and the second direction and the third direction are both perpendicular to the first direction; A heat dissipation structure is formed to conformally cover the first chip and the plurality of semiconductor structures.

12. The manufacturing method according to claim 11, characterized in that: The thermal conductivity of the heat dissipation structure is greater than the thermal conductivity of the semiconductor structure.

13. The manufacturing method according to claim 11, characterized in that: The forming of a heat dissipation structure conformally covering the first chip and the plurality of semiconductor structures comprises: forming a barrier layer conformally covering the first chip and the plurality of semiconductor structures; forming a seed layer conformally covering the barrier layer; and A heat dissipation layer is formed conformally covering the seed layer.

14. The manufacturing method according to claim 11, characterized in that: The first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the plurality of semiconductor structures includes a second chip; the second chip includes a memory cell array and a second bonding layer stacked along the first direction; The step of coupling the plurality of semiconductor structures to a surface of one side of the first chip in a first direction includes: The second bonding layer of each of the semiconductor structures is bonded to the first bonding layer.

15. The manufacturing method according to claim 11, characterized in that: The first chip includes a peripheral circuit and a first bonding layer stacked along the first direction; each of the plurality of semiconductor structures includes a plurality of second chips stacked and arranged along the first direction; each of the second chips includes a memory cell array and a second bonding layer stacked along the first direction; The step of coupling the plurality of semiconductor structures to a surface of one side of the first chip in a first direction includes: The second bonding layer in the second chip closest to the first chip among the plurality of second chips in each of the semiconductor structures is bonded to the first bonding layer.

16. The manufacturing method according to claim 11, characterized in that: The method further comprises: A plastic sealing layer is formed between the heat dissipation structures on the sides of the adjacent semiconductor structures.

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