Semiconductor testing device, equipment and semiconductor testing method

Abstract

The invention provides a semiconductor testing device, equipment and a semiconductor testing method, the semiconductor testing device comprises a first path, a second path and a main control unit, the main control unit is connected with to-be-tested equipment through a signal transmission line, and the first path and the second path each comprise an analog-to-digital converter; a first signal end of the first path is connected to the main control unit, and a second signal end is connected to a to-be-tested device; the first path is used for measuring the voltage and / or current of the to-be-measured equipment; a first signal end of the second path is connected to the signal transmission line, and a second signal end is connected to the analog-to-digital converter; the second path is used for collecting the communication signal transmitted by the signal transmission line to obtain a collected signal; the analog-to-digital converter is used for sending the acquired signal to the main control unit; the semiconductor testing device realizes waveform acquisition based on function multiplexing of an analog-to-digital converter; according to the invention, real-time communication signal waveform acquisition of the signal transmission line is realized in a device function multiplexing mode, the test efficiency is improved, and the cost is reduced.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and in particular, relates to a semiconductor testing device, equipment and semiconductor testing method. Background Art

[0002] During the manufacturing and testing of semiconductors, ATE (Automatic Test Equipment) testers or test boxes are required to complete the testing of DUT (Device Under Test) and distinguish good and bad products based on the tested circuit performance indicators and digital functions. ATE usually consists of a master control unit and a large number of slave devices. The master control unit has a central processor that provides control and data processing services for the entire device. The slave devices are controlled by the master control unit and are used to complete various tests on the DUT.

[0003] Most DUTs need to perform communication tests of bus communication protocols such as I2C, SPI, and UART during the chip probe (CP) test or function test (FT) stage. At the same time, the master control unit and slave devices inside the ATE also need to communicate and interact through protocols such as I2C, SPI, and UART. Therefore, there are a large number of signal transmission lines based on protocols such as I2C, SPI, and UART in the ATE equipment, both inside and outside the equipment. These bus protocols complete data transmission by sending digital signals on the data line according to the agreed timing.

[0004] During the CP test or FT test phase, when the bus communication protocol between the ATE equipment and the DUT is being tested, communication anomalies may occur. The cause of the anomaly may be that the DUT itself cannot work. In this case, the DUT needs to be judged as a defective product and discarded. However, the cause of the anomaly may also be due to an abnormality in the ATE control program or interference on the data line. In order to prevent the DUT from being misjudged as a defective product, it is necessary to accurately determine the cause of the communication anomaly. The most direct and effective way to locate the communication problem is to observe the waveform on the signal transmission line in real time. However, in the actual CP or FT test environment, the bus to be measured is often inside the equipment or even inside the circuit board. In addition, the chip packaging and testing factory has requirements for production efficiency and environmental cleanliness, so the method of disassembling the equipment is not feasible. Even if the measured bus is outside the ATE equipment, due to the large number of wafers and probes on the wafers of the chip to be tested (for example, up to tens of thousands), and the size of the chip to be tested is too small, and the operating space is too small, so there is no condition for accessing waveform observation equipment such as an oscilloscope inside and outside. Therefore, how to collect the bus communication signal waveform is a problem currently faced. Summary of the invention

[0005] The present application provides a semiconductor testing device, equipment and semiconductor testing method, which realizes real-time communication signal waveform acquisition of signal transmission lines in a device function multiplexing manner, improves testing efficiency and reduces costs.

[0006] In a first aspect, the present application provides a semiconductor testing device, comprising a first path, a second path and a main control unit, wherein the main control unit is connected to a device under test via a signal transmission line, and the first path and the second path both comprise an analog-to-digital converter;

[0007] The first signal end of the first path is connected to the main control unit, and the second signal end is connected to the device under test; the first path is used to measure the voltage and / or current of the device under test;

[0008] The first signal end of the second path is connected to the signal transmission line, and the second signal end is connected to the analog-to-digital converter; the second path is used to collect the communication signal transmitted by the signal transmission line to obtain a collection signal; the analog-to-digital converter is used to send the collection signal to the main control unit; the semiconductor test device realizes waveform collection based on the functional multiplexing of the analog-to-digital converter;

[0009] When the semiconductor testing device needs to collect the communication signal waveform on the signal transmission line, the main control unit sends a waveform collection instruction to the analog-to-digital converter and controls the second path to be turned on.

[0010] In a possible implementation manner of the first aspect, the semiconductor testing apparatus further includes a plurality of slave devices, and the slave devices are connected to the signal transmission line.

[0011] In a possible implementation manner of the first aspect, the first path and the second path both include electronic switches, the electronic switches respectively control the opening or closing of the first path and the second path, and the main control unit controls the opening and closing of the electronic switches.

[0012] In a possible implementation manner of the first aspect, the main control unit controls both the first path and the second path to be turned on.

[0013] In a possible implementation manner of the first aspect, the signal transmission line includes a plurality of parallel conductive wires, each conductive wire transmits a signal, and each conductive wire is correspondingly provided with one of the electronic switches.

[0014] In a possible implementation manner of the first aspect, the main control unit is further configured to send the acquisition signal to an external display device, so that the display device displays the acquisition signal.

[0015] In a possible implementation manner of the first aspect, the main control unit is further configured to store the collected signal.

[0016] In a possible implementation manner of the first aspect, the signal transmission line is a bus.

[0017] In a second aspect, the present application provides a semiconductor testing device, comprising the semiconductor testing apparatus described in any one of the above-mentioned first aspects.

[0018] In a third aspect, the present application provides a semiconductor testing method, which is applied to the semiconductor testing device described in any one of the first aspects above, and the method comprises the steps of:

[0019] The main control unit sends a waveform acquisition instruction to the analog-to-digital converter and controls the second path to be turned on;

[0020] In response to the waveform acquisition instruction, the analog-to-digital converter acquires the communication signal on the signal transmission line to obtain an acquisition signal, and sends the acquisition signal to the main control unit.

[0021] In a possible implementation manner of the third aspect, the method further includes the steps of:

[0022] The main control unit sends a voltage and current measurement instruction to the analog-to-digital converter, and controls the first path to be turned on;

[0023] In response to the voltage and current measurement instruction, the analog-to-digital converter measures the voltage and / or current corresponding to the device under test, and sends the measured voltage and / or current to the main control unit.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] During the chip probe test phase or the functional test phase, when conducting a communication test of the bus communication protocol between the ATE device and the DUT, the present application utilizes the electronic switch inside the ATE device and the built-in analog-to-digital converter. On the one hand, this realizes real-time communication signal waveform acquisition of the signal transmission line in a device function multiplexing manner, without the need to disassemble the device or connect external instruments, thereby improving test efficiency and reducing costs. On the other hand, it facilitates rapid analysis and accurate determination of the cause of communication anomalies, effectively reducing the situation where the DUT is misjudged as a defective product, and is beneficial to improving the yield, accuracy and reliability of DUT testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0027] Figure 1 is a structural schematic diagram of a semiconductor testing device provided by an embodiment of the present application;

[0028] Figure 2 is a structural schematic diagram of a semiconductor testing device provided by another embodiment of the present application;

[0029] Figure 3 It is a schematic diagram of the process of collecting the waveform of a communication signal on a signal transmission line by a semiconductor test device;

[0030] Figure 4 is a schematic structural diagram of an ATE device, a device under test, and a display device after being connected according to another embodiment of the present application;

[0031] Figure 5 is a flow chart of a semiconductor testing method provided by an embodiment of the present application;

[0032] Figure 6 It is a flow chart of a semiconductor testing method provided by another embodiment of the present application. DETAILED DESCRIPTION

[0033] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0034] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, wholes, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or combinations thereof.

[0035] It should also be understood that the term “and / or” used in the specification and appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0036] As used in the specification and appended claims of this application, the term "if" can be interpreted as "when" or "uponce" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "uponce it is determined" or "in response to determining" or "uponce [described condition or event] is detected" or "in response to detecting [described condition or event]", depending on the context.

[0037] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0038] References to "one embodiment" or "some embodiments" etc. described in the specification of this application mean that one or more embodiments of the present application include specific features, structures or characteristics described in conjunction with the embodiment. Therefore, the statements "in one embodiment", "in some embodiments", "in some other embodiments", "in some other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0039] An embodiment of the present application discloses a semiconductor testing device. Figure 1 As shown, the semiconductor testing device includes a first path 11, a second path 12 and a main control unit 13. The main control unit 13 is connected to a device under test 14 (DUT) through a signal transmission line. The first path 11 and the second path 12 are respectively connected to the device under test 14. The present application is particularly suitable for the case where the device under test 14 is a CMOS image sensor.

[0040] In this embodiment, the semiconductor test device is a partial structure in the ATE equipment. ATE is a collection of test instruments controlled by a high-performance computer. It is a test system composed of a tester and a computer. The computer controls the test hardware by running the instructions of the test program. The semiconductor chip tester is used to detect the integrity of the function and performance of the integrated circuit. It is an important equipment to ensure the quality of the integrated circuit in the integrated circuit production process.

[0041] In this embodiment, the first path 11 and the second path 12 both include an analog to digital converter (ADC). The first signal end of the first path 11 is connected to the main control unit 13, and the second signal end is connected to the device under test 14. The first path 11 is used to measure the voltage and / or current of the device under test 14. The first signal end of the second path 12 is connected to the signal transmission line, and the second signal end is connected to the analog to digital converter. The second path 12 is used to collect the communication signal transmitted by the signal transmission line to obtain the collected signal. The main control unit 13 and the device under test 14 are connected to the above-mentioned signal transmission line, that is, communication is carried out based on the above-mentioned signal transmission line, and the above-mentioned signal transmission line is the signal line that needs to be analyzed for waveform collection.

[0042] The analog-to-digital converter sends the collected signal to the main control unit 13. That is, in the present application, the ADC can not only measure the voltage and / or current of the device under test 14 based on the first path 11, but also collect the communication signal waveform on the signal transmission line based on the second path 12. In this way, the waveform collection function of the semiconductor test device itself is utilized to realize the function multiplexing of the ADC device, and there is no need to add other hardware for collecting signal waveforms, thereby reducing hardware costs and improving test efficiency.

[0043] When the semiconductor test device needs to collect the communication signal waveform on the signal transmission line, the main control unit 13 of the semiconductor test device sends a waveform collection instruction to the analog-to-digital converter and controls the second path 12 to be turned on. In response to the waveform collection instruction, the analog-to-digital converter collects the communication signal on the signal transmission line, obtains the collection signal, and sends the collection signal to the main control unit 13. The main control unit 13 can store the collection signal locally, or send it to a display device externally connected to the semiconductor test device for display, so that relevant personnel can observe the signal waveform and accurately locate the cause of the communication abnormality, effectively reduce the situation where the DUT is misjudged as a defective product, and improve the yield, accuracy and reliability of the DUT test.

[0044] When the semiconductor testing device needs to obtain the voltage and / or current value of the device under test 14, the main control unit 13 of the semiconductor testing device sends a related measurement instruction to the analog-to-digital converter and controls the first path 11 to be turned on. In response to the measurement instruction, the analog-to-digital converter measures the voltage and / or current corresponding to the device under test 14, and sends the measured voltage and / or current to the main control unit 13.

[0045] The first path 11 and the second path 12 can be in a conducting state in the same period or in different periods. That is, the communication signal waveform acquisition task and the voltage and current measurement task can be executed simultaneously or asynchronously.

[0046] In the present application, the sampling rate of the ADC is related to the specific ADC chip model used, and its sampling rate needs to be high enough to ensure that the waveform data collected will not be distorted and affect the analysis. The number of sampling channels of the ADC is also related to the ADC chip model used. The more sampling channels there are, the more signal lines can be sampled simultaneously. All channels should be used as much as possible during circuit design. The data after ADC sampling is processed by the main control unit 13, and the main control can choose to display the data on the display device, or save the data for subsequent analysis. In some optional embodiments, some prior data on the correlation between the completeness of the collected waveform and the sampling rate can be obtained based on experiments, and then the sampling rate matching it can be determined based on the waveform completeness required by this embodiment, and then the relevant ADC chip model can be determined based on the above-mentioned prior data; this is conducive to ensuring the success rate of the test.

[0047] In this embodiment, the signal transmission line is a bus. The communication protocol of the bus may be an I2C protocol, etc. In other embodiments, the signal transmission line may also be other types of signal lines, such as a serial communication line, etc., which is not limited in this application.

[0048] In the chip probe test stage or the functional test stage, when conducting a communication test of the bus communication protocol between the semiconductor test device and the DUT, the electronic switch inside the semiconductor test device and the built-in analog-to-digital converter (ADC) are utilized to realize real-time waveform acquisition of the signal transmission line in a device function multiplexing manner. There is no need to disassemble the equipment and connect external instruments, nor is there any need to connect other waveform acquisition devices. The semiconductor test device itself can complete the waveform acquisition of the signal line, which greatly facilitates the abnormality troubleshooting work during equipment debugging and use, improves test efficiency and reduces costs.

[0049] On the other hand, it is easy to quickly analyze and accurately determine the cause of communication anomalies, effectively reducing the situation where DUT is misjudged as defective, and improving the yield, accuracy and reliability of DUT testing.

[0050] Moreover, most ATE equipment has network connection function, so workers do not need to be on-site and can complete signal waveform acquisition and abnormality analysis remotely, reducing the operation and maintenance costs of semiconductor testing equipment.

[0051] In another embodiment of the present application, Figure 2As shown, the semiconductor test apparatus further includes a plurality of slave devices 15, and the slave devices 15 are connected to the above-mentioned signal transmission line. Therefore, the slave devices 15 can communicate with the main control unit and the device under test based on the signal transmission line. The functions of the slave devices in the ATE system include executing test commands, that is, the slave devices receive test instructions issued by the main control unit and perform corresponding test operations according to these instructions.

[0052] Figure 3 The following is a workflow of semiconductor testing equipment to collect communication signal waveforms from signal transmission lines. Figure 3 The main control unit sends data to the device under test or the slave device through the signal transmission line. The main control unit controls the analog-to-digital converter 31 to collect the communication signal on the signal transmission line to obtain the collected signal, and the analog-to-digital converter sends the collected signal to the main control unit.

[0053] In another embodiment of the present application, the isolation of the first path and the second path is achieved based on the above-mentioned electronic switch. Specifically, the first path and the second path both include electronic switches, and the electronic switches control the conduction or disconnection of the first path and the second path respectively, and the main control unit controls the opening and closing of the electronic switches. Figure 4 As shown, the first path includes a first electronic switch 41, and the first electronic switch 41 controls the conduction or disconnection of the first path. The second path includes a second electronic switch 42, and the second electronic switch 42 controls the conduction or disconnection of the second path. The control unit controls the opening and closing of the first electronic switch 41 and the second electronic switch 42. When the first electronic switch 41 is closed, the semiconductor test device can collect the voltage and / or current value of the device under test. When the second electronic switch 42 is closed, the semiconductor test device can collect the communication signal waveform on the signal transmission line. Figure 4 The internal analog circuit in the first path 11 is also shown.

[0054] In some optional embodiments, the signal transmission line includes multiple parallel wires, each wire transmits a signal, and each wire is correspondingly provided with an electronic switch. Figure 4 The bus in includes 4 wires, and 4 second electronic switches 42 are correspondingly provided. For another example, for the bus of the I2C protocol, the protocol only uses two data lines, SDA and SCL, for data transmission. The SCL line is completely controlled by the master control unit, and the SDA line is a bidirectional signal line, which is controlled by the master control unit and the slave device. In order to accurately locate the communication abnormality point, it is necessary to collect the waveforms on the two wires, the SCL line and the SDA line.

[0055] In some optional embodiments, such as Figure 4As shown, the semiconductor test device may further include a power supply unit and other electrical test circuits. The power supply unit and other electrical test circuits are respectively connected to the main control unit. The power supply unit is used to provide power to the semiconductor test device, and the other electrical test circuits are used to measure some electrical index values ​​for subsequent related data analysis.

[0056] Another embodiment of the present application discloses a semiconductor testing device, which includes the semiconductor testing apparatus disclosed in any of the above embodiments. In this embodiment, the device is an ATE device.

[0057] Another embodiment of the present application discloses a semiconductor testing method. The method is applied to the semiconductor testing device disclosed in any of the above embodiments. Figure 5 As shown, the above test method includes the steps of:

[0058] S110, the main control unit sends a waveform acquisition instruction to the analog-to-digital converter and controls the second path to be turned on.

[0059] S120, in response to the waveform acquisition instruction, the analog-to-digital converter acquires the communication signal on the signal transmission line to obtain an acquisition signal, and sends the acquisition signal to the main control unit.

[0060] In some optional embodiments, in the above Figure 5 Based on the corresponding embodiment, Figure 6 As shown, the steps include:

[0061] S130, the main control unit sends a voltage and current measurement instruction to the analog-to-digital converter, and controls the first path to be turned on.

[0062] S140, in response to the voltage and current measurement instruction, the analog-to-digital converter measures the voltage and / or current corresponding to the device under test, and sends the measured voltage and / or current to the main control unit.

[0063] For the specific implementation logic of the semiconductor testing method, reference may be made to the description of the relevant embodiments of the semiconductor testing device mentioned above, and this application will not go into details here.

[0064] The semiconductor testing method provided in the above-mentioned embodiments of the present application utilizes the electronic switch inside the ATE device and the built-in analog-to-digital converter during the chip probe testing stage or the functional testing stage when conducting the communication test of the bus communication protocol between the ATE device and the DUT. On the one hand, it realizes the real-time communication signal waveform acquisition of the signal transmission line in a device function multiplexing manner, without the need to disassemble the device and connect external instruments, thereby improving the testing efficiency and reducing the cost. On the other hand, it facilitates the rapid analysis and accurate determination of the cause of the communication anomaly, effectively reduces the situation where the DUT is misjudged as a defective product, and is beneficial to improving the yield, accuracy and reliability of the DUT test.

[0065] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0066] It should be noted that the above-mentioned various semiconductor testing device embodiments disclosed in the present application can be freely combined, and the technical solutions obtained after the free combination are also within the protection scope of the present application.

[0067] Corresponding to the semiconductor testing method described in the above embodiment, an embodiment of the present application provides another semiconductor testing device, the semiconductor testing device comprising:

[0068] In the waveform acquisition module, the main control unit sends a waveform acquisition instruction to the analog-to-digital converter and controls the conduction of the second path.

[0069] The waveform sending module responds to the waveform acquisition instruction, and the analog-to-digital converter acquires the communication signal on the signal transmission line to obtain the acquisition signal, and sends the acquisition signal to the main control unit.

[0070] In some optional embodiments, the semiconductor testing device further includes:

[0071] The voltage and current measurement module, the main control unit sends a voltage and current measurement instruction to the analog-to-digital converter, and controls the first path to be turned on.

[0072] The voltage and current sending module responds to the voltage and current measurement instruction, and the analog-to-digital converter measures the voltage and / or current corresponding to the device under test, and sends the measured voltage and / or current to the main control unit.

[0073] It should be noted that the information interaction, execution process, etc. between the above-mentioned devices / units are based on the same concept as the method embodiment of the present application. Their specific functions and technical effects can be found in the method embodiment part and will not be repeated here.

[0074] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0075] The embodiment of the present application further provides a semiconductor testing device, which implements the testing of at least one device under test by executing the testing method described in any of the above embodiments.

[0076] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A semiconductor testing device, characterized in that: It includes a first path, a second path and a main control unit, the main control unit is connected to the device under test through a signal transmission line, and the first path and the second path both include an analog-to-digital converter; The first signal end of the first path is connected to the main control unit, and the second signal end is connected to the device under test; the first path is used to measure the voltage and / or current of the device under test; The first signal end of the second path is connected to the signal transmission line, and the second signal end is connected to the analog-to-digital converter; The second path is used to collect the communication signal transmitted by the signal transmission line to obtain a collection signal; the analog-to-digital converter is used to send the collection signal to the main control unit; the semiconductor test device realizes waveform collection based on the functional multiplexing of the analog-to-digital converter; When the semiconductor testing device needs to collect the communication signal waveform on the signal transmission line, the main control unit sends a waveform collection instruction to the analog-to-digital converter and controls the second path to be turned on.

2. The semiconductor testing device according to claim 1, wherein: The semiconductor testing device further includes a plurality of slave devices connected to the signal transmission line.

3. The semiconductor testing device according to claim 1, wherein: The first path and the second path both include electronic switches, and the electronic switches control the conduction or disconnection of the first path and the second path respectively, and the main control unit controls the opening and closing of the electronic switches.

4. The semiconductor testing device according to claim 1, wherein: The main control unit controls the first path and the second path to be turned on.

5. The semiconductor testing device according to claim 3, wherein: The signal transmission line includes a plurality of parallel conducting wires, each conducting wire transmits a signal, and each conducting wire is correspondingly provided with one of the electronic switches.

6. The semiconductor testing device according to any one of claims 1 to 5, characterized in that: The main control unit is further used to send the acquisition signal to an external display device, so that the display device displays the acquisition signal.

7. The semiconductor testing device according to any one of claims 1 to 5, characterized in that: The main control unit is also used to store the collected signal.

8. A semiconductor testing device, characterized in that: The semiconductor testing device comprises the semiconductor testing device as claimed in any one of claims 1 to 7.

9. A semiconductor testing method, characterized in that: The semiconductor testing device according to any one of claims 1 to 8, wherein the method comprises the steps of: The main control unit sends a waveform acquisition instruction to the analog-to-digital converter and controls the second path to be turned on; In response to the waveform acquisition instruction, the analog-to-digital converter acquires the communication signal on the signal transmission line to obtain an acquisition signal, and sends the acquisition signal to the main control unit.

10. The semiconductor testing method according to claim 9, wherein: The method further comprises the steps of: The main control unit sends a voltage and current measurement instruction to the analog-to-digital converter, and controls the first path to be turned on; In response to the voltage and current measurement instruction, the analog-to-digital converter measures the voltage and / or current corresponding to the device under test, and sends the measured voltage and / or current to the main control unit.

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